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ARM: rmobile: Clean up ad-hoc clock macros

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As we have a proper clock framework driver, these macros are not
needed, so drop them and clean up the whitelist.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut
2017-11-27 06:38:12 +01:00
parent 8c1b52f4b0
commit 61e2ff8e82
3 changed files with 2 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
include/configs/salvator-x.h
View File

@@ -17,7 +17,6 @@
/* SCIF */
#define CONFIG_CONS_SCIF2
#define CONFIG_CONS_INDEX 2
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
/* [A] Hyper Flash */
/* use to RPC(SPI Multi I/O Bus Controller) */
@@ -28,14 +27,7 @@
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define RCAR_XTAL_CLK 33333333u
#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK
/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */
#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2)
#define CONFIG_S3D2_CLK_FREQ (266666666u/2)
#define CONFIG_S3D4_CLK_FREQ (266666666u/4)
#define CONFIG_SYS_CLK_FREQ 33333333u
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
@@ -52,9 +44,6 @@
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30
/* SDHI */
#define CONFIG_SH_SDHI_FREQ 200000000
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 1

13
include/configs/ulcb.h
View File

@@ -17,7 +17,6 @@
/* SCIF */
#define CONFIG_CONS_SCIF2
#define CONFIG_CONS_INDEX 2
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
/* [A] Hyper Flash */
/* use to RPC(SPI Multi I/O Bus Controller) */
@@ -28,14 +27,7 @@
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define RCAR_XTAL_CLK 33333333u
#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK
/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */
#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2)
#define CONFIG_S3D2_CLK_FREQ (266666666u/2)
#define CONFIG_S3D4_CLK_FREQ (266666666u/4)
#define CONFIG_SYS_CLK_FREQ 33333333u
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
@@ -65,9 +57,6 @@ unsigned char ulcb_softspi_read(void);
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30
/* SDHI */
#define CONFIG_SH_SDHI_FREQ 200000000
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 1

3
scripts/config_whitelist.txt
View File

@@ -346,7 +346,6 @@ CONFIG_CPU_SH7785
CONFIG_CPU_SH_TYPE_R
CONFIG_CPU_TYPE_R
CONFIG_CPU_VR41XX
CONFIG_CP_CLK_FREQ
CONFIG_CQSPI_DECODER
CONFIG_CQSPI_REF_CLK
CONFIG_CRC32
@@ -1886,8 +1885,6 @@ CONFIG_RUN_FROM_DDR1
CONFIG_RUN_FROM_IRAM_ONLY
CONFIG_RX_DESCR_NUM
CONFIG_S32V234
CONFIG_S3D2_CLK_FREQ
CONFIG_S3D4_CLK_FREQ
CONFIG_S5P
CONFIG_S5PC100
CONFIG_S5PC110