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mtd: spi-nor: Add parallel and stacked memories support

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In parallel mode, the current implementation assumes that a maximum of
two flashes are connected. The QSPI controller splits the data evenly
between both the flashes so, both the flashes that are connected in
parallel mode should be identical.
During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in
nor->flags.

In stacked mode the current implementation assumes that a maximum of two
flashes are connected and both the flashes are of same make but can
differ in sizes. So, except the sizes all other flash parameters of both
the flashes are identical

Spi-nor will pass on the appropriate flash select flag to low level
driver, and it will select pass all the data to that particular flash.

Write operation in parallel mode are performed in page size * 2 chunks as
each write operation results in writing both the flashes. For doubling
the address space each operation is performed at addr/2 flash offset,
where addr is the address specified by the user.

Similarly for read and erase operations it will read from both flashes,
so size and offset are divided by 2 and send to flash.

Adding the config option SPI_ADVANCE for non SPL code.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
This commit is contained in:
Venkatesh Yadav Abbarapu
2024-09-26 10:25:02 +05:30
committed by Tom Rini
parent 8a64a88a78
commit 5d40b3d384
4 changed files with 300 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
include/linux/mtd/spi-nor.h
View File

@@ -13,6 +13,9 @@
#include <linux/mtd/mtd.h>
#include <spi-mem.h>
/* In parallel configuration enable multiple CS */
#define SPI_NOR_ENABLE_MULTI_CS (BIT(0) | BIT(1))
/*
* Manufacturer IDs
*
@@ -177,6 +180,12 @@
/* Status Register 2 bits. */
#define SR2_QUAD_EN_BIT7 BIT(7)
/*
* Maximum number of flashes that can be connected
* in stacked/parallel configuration
*/
#define SNOR_FLASH_CNT_MAX 2
/* For Cypress flash. */
#define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
#define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
@@ -294,6 +303,13 @@ enum spi_nor_option_flags {
SNOR_F_BROKEN_RESET = BIT(6),
SNOR_F_SOFT_RESET = BIT(7),
SNOR_F_IO_MODE_EN_VOLATILE = BIT(8),
#if defined(CONFIG_SPI_ADVANCE)
SNOR_F_HAS_STACKED = BIT(9),
SNOR_F_HAS_PARALLEL = BIT(10),
#else
SNOR_F_HAS_STACKED = 0,
SNOR_F_HAS_PARALLEL = 0,
#endif
};
struct spi_nor;
@@ -551,6 +567,7 @@ struct spi_nor {
u8 bank_read_cmd;
u8 bank_write_cmd;
u8 bank_curr;
u8 upage_prev;
#endif
enum spi_nor_protocol read_proto;
enum spi_nor_protocol write_proto;