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driver/ddr/freescale: Fix DDR3 driver for ARM
Reading DDR register should use ddr_in32() for proper endianess. This patch fixes incorrect waiting time for ARM platforms. Signed-off-by: York Sun <yorksun@freescale.com>
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@@ -194,7 +194,7 @@ step2:
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* For example, 2GB on 666MT/s 64-bit bus takes about 402ms
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* For example, 2GB on 666MT/s 64-bit bus takes about 402ms
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* Let's wait for 800ms
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* Let's wait for 800ms
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*/
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*/
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bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
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bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
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>> SDRAM_CFG_DBW_SHIFT);
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>> SDRAM_CFG_DBW_SHIFT);
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timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
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timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
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(get_ddr_freq(0) >> 20)) << 1;
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(get_ddr_freq(0) >> 20)) << 1;
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