diff --git a/Kconfig b/Kconfig index 4462432956..1c408b6bec 100644 --- a/Kconfig +++ b/Kconfig @@ -369,6 +369,16 @@ config PLATFORM_ELFENTRY default "__start" if MIPS default "_start" +config STACK_SIZE + hex "Define max stack size that can be used by U-Boot" + default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP + default 0x200000 if MICROBLAZE + default 0x1000000 + help + Define Max stack size that can be used by U-Boot. This value is used + by the UEFI sub-system. On some boards initrd_high is calculated as + base stack pointer minus this stack size. + endmenu # General setup menu "Boot images" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3e11ddfa9b..6b8a32c38d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -503,23 +503,6 @@ config TPL_USE_ARCH_MEMSET Such an implementation may be faster under some conditions but may increase the binary size. -config SET_STACK_SIZE - bool "Enable an option to set max stack size that can be used" - default y if ARCH_VERSAL || ARCH_ZYNQMP || ARCH_ZYNQ - help - This will enable an option to set max stack size that can be - used by U-Boot. - -config STACK_SIZE - hex "Define max stack size that can be used by U-Boot" - depends on SET_STACK_SIZE - default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP - default 0x1000000 if ARCH_ZYNQ - help - Define Max stack size that can be used by U-Boot so that the - initrd_high will be calculated as base stack pointer minus this - stack size. - config ARM64_SUPPORT_AARCH32 bool "ARM64 system support AArch32 execution state" depends on ARM64 @@ -1957,6 +1940,7 @@ source "board/hisilicon/hikey/Kconfig" source "board/hisilicon/hikey960/Kconfig" source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" +source "board/myir/mys_6ulx/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index abf9a027cc..43a2ee1213 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -721,6 +721,7 @@ dtb-$(CONFIG_MX6UL) += \ dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ imx6ull-colibri.dtb \ + imx6ull-myir-mys-6ulx-eval.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-dart-6ul.dtb \ imx6ull-somlabs-visionsom.dtb \ diff --git a/arch/arm/dts/imx6ull-colibri-u-boot.dtsi b/arch/arm/dts/imx6ull-colibri-u-boot.dtsi index 531cdcc4da..afdb0f43cf 100644 --- a/arch/arm/dts/imx6ull-colibri-u-boot.dtsi +++ b/arch/arm/dts/imx6ull-colibri-u-boot.dtsi @@ -3,6 +3,15 @@ * Copyright 2019 Toradex AG */ +/ { + aliases { + u-boot,dm-pre-reloc; + mmc0 = &usdhc1; + usb0 = &usbotg1; /* required for ums */ + display0 = &lcdif; + }; +}; + &pinctrl_uart1 { u-boot,dm-pre-reloc; }; @@ -10,3 +19,39 @@ &pinctrl_uart1_ctrl1 { u-boot,dm-pre-reloc; }; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + status = "okay"; + display = <&display0>; + u-boot,dm-pre-reloc; + + display0: display0 { + bits-per-pixel = <18>; + bus-width = <24>; + status = "okay"; + + display-timings { + native-mode = <&timing_vga>; + timing_vga: 640x480 { + u-boot,dm-pre-reloc; + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <24>; + vback-porch = <32>; + vfront-porch = <11>; + hsync-len = <96>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx6ull-colibri.dtsi b/arch/arm/dts/imx6ull-colibri.dtsi index fca53119fe..b7bf79f28c 100644 --- a/arch/arm/dts/imx6ull-colibri.dtsi +++ b/arch/arm/dts/imx6ull-colibri.dtsi @@ -8,13 +8,6 @@ #include "imx6ull.dtsi" / { - aliases { - u-boot,dm-pre-reloc; - mmc0 = &usdhc1; - usb0 = &usbotg1; /* required for ums */ - display0 = &lcdif; - }; - chosen { stdout-path = &uart1; }; @@ -151,42 +144,6 @@ }; }; -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - status = "okay"; - display = <&display0>; - u-boot,dm-pre-reloc; - - display0: display0 { - bits-per-pixel = <18>; - bus-width = <24>; - status = "okay"; - - display-timings { - native-mode = <&timing_vga>; - timing_vga: 640x480 { - u-boot,dm-pre-reloc; - clock-frequency = <25175000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <33>; - vfront-porch = <10>; - hsync-len = <96>; - vsync-len = <2>; - - de-active = <1>; - hsync-active = <0>; - vsync-active = <0>; - pixelclk-active = <0>; - }; - }; - }; -}; - /* PWM */ &pwm4 { pinctrl-names = "default"; diff --git a/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts b/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts new file mode 100644 index 0000000000..2fd69da028 --- /dev/null +++ b/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-myir-mys-6ulx.dtsi" +#include "imx6ull-mys-6ulx-u-boot.dtsi" + +/ { + model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND"; + compatible = "myir,imx6ull-mys-6ulx-eval", "fsl,imx6ull"; +}; + +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi b/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi new file mode 100644 index 0000000000..d03694feaf --- /dev/null +++ b/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi + */ + +#include +#include +#include + +/ { + model = "MYiR MYS-6ULX Single Board Computer"; + compatible = "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + reg_vdd_5v: regulator-vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_vdd_3v3: regulator-vdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_vdd_5v>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <®_vdd_3v3>; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_vdd_3v3>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; + vmmc-supply = <®_vdd_3v3>; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; +}; diff --git a/arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi b/arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi new file mode 100644 index 0000000000..cd15d9ba86 --- /dev/null +++ b/arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi + */ + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&gpmi { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&usdhc1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&usdhc2 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx7-colibri-emmc.dts b/arch/arm/dts/imx7-colibri-emmc.dts index bc0d10c716..8545498275 100644 --- a/arch/arm/dts/imx7-colibri-emmc.dts +++ b/arch/arm/dts/imx7-colibri-emmc.dts @@ -5,13 +5,13 @@ /dts-v1/; #include "imx7-colibri.dtsi" +#include "imx7-colibri-u-boot.dtsi" / { model = "Toradex Colibri iMX7D 1GB (eMMC)"; compatible = "toradex,imx7d-colibri-emmc", "fsl,imx7d"; aliases { - u-boot,dm-pre-reloc; mmc0 = &usdhc3; mmc1 = &usdhc1; display1 = &lcdif; diff --git a/arch/arm/dts/imx7-colibri-rawnand.dts b/arch/arm/dts/imx7-colibri-rawnand.dts index 5f12a2ac2a..5211fb1f44 100644 --- a/arch/arm/dts/imx7-colibri-rawnand.dts +++ b/arch/arm/dts/imx7-colibri-rawnand.dts @@ -5,17 +5,19 @@ /dts-v1/; #include "imx7-colibri.dtsi" +#include "imx7-colibri-u-boot.dtsi" / { model = "Toradex Colibri iMX7S/D"; compatible = "toradex,imx7-colibri", "fsl,imx7"; - chosen { - stdout-path = &uart1; + aliases { + display1 = &lcdif; + usb0 = &usbotg1; /* required for ums */ }; - aliases { - usb0 = &usbotg1; /* required for ums */ + chosen { + stdout-path = &uart1; }; reg_5v0: regulator-5v0 { diff --git a/arch/arm/dts/imx7-colibri-u-boot.dtsi b/arch/arm/dts/imx7-colibri-u-boot.dtsi new file mode 100644 index 0000000000..91386476d5 --- /dev/null +++ b/arch/arm/dts/imx7-colibri-u-boot.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +&lcdif { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + u-boot,dm-pre-reloc; + + display0: display0 { + bits-per-pixel = <18>; + bus-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing_vga>; + timing_vga: 640x480 { + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <24>; + vback-porch = <32>; + vfront-porch = <11>; + hsync-len = <96>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx7-colibri.dtsi b/arch/arm/dts/imx7-colibri.dtsi index ec95f22a0c..b352036e30 100644 --- a/arch/arm/dts/imx7-colibri.dtsi +++ b/arch/arm/dts/imx7-colibri.dtsi @@ -172,6 +172,38 @@ >; }; + pinctrl_lcdif_dat: lcdif-dat-grp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdif-ctrl-grp { + fsl,pins = < + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + >; + }; + pinctrl_enet1: enet1grp { fsl,pins = < MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 @@ -227,36 +259,3 @@ >; }; }; - -&lcdif { - status = "okay"; - display = <&display0>; - u-boot,dm-pre-reloc; - - display0: display0 { - bits-per-pixel = <18>; - bus-width = <24>; - status = "okay"; - - display-timings { - native-mode = <&timing_vga>; - timing_vga: 640x480 { - u-boot,dm-pre-reloc; - clock-frequency = <25175000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <33>; - vfront-porch = <10>; - hsync-len = <96>; - vsync-len = <2>; - - de-active = <1>; - hsync-active = <0>; - vsync-active = <0>; - pixelclk-active = <0>; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts index b86f46e03e..1c67c08c88 100644 --- a/arch/arm/dts/imx8mm-verdin.dts +++ b/arch/arm/dts/imx8mm-verdin.dts @@ -16,6 +16,12 @@ stdout-path = &uart1; }; + aliases { + eeprom0 = &eeprom_module; + eeprom1 = &eeprom_carrier_board; + eeprom2 = &eeprom_display_adapter; + }; + /* fixed clock dedicated to SPI CAN controller */ clk20m: oscillator { compatible = "fixed-clock"; @@ -321,8 +327,8 @@ vcc-supply = <&ldo5_reg>; }; - eeprom@50 { - compatible = "st,24c02"; + eeprom_module: eeprom@50 { + compatible = "st,24c02", "atmel,24c02", "i2c-eeprom"; pagesize = <16>; reg = <0x50>; }; @@ -377,16 +383,16 @@ status = "okay"; }; - /* EEPROM on MIPI-DSI to HDMI adapter */ - eeprom_50: eeprom@50 { - compatible = "st,24c02"; + /* EEPROM on display adapter (MIPI DSI Display Adapter) */ + eeprom_display_adapter: eeprom@50 { + compatible = "st,24c02", "atmel,24c02", "i2c-eeprom"; pagesize = <16>; reg = <0x50>; }; - /* EEPROM on Verdin Development board */ - eeprom_57: eeprom@57 { - compatible = "st,24c02"; + /* EEPROM on carrier board */ + eeprom_carrier_board: eeprom@57 { + compatible = "st,24c02", "atmel,24c02", "i2c-eeprom"; pagesize = <16>; reg = <0x57>; }; diff --git a/arch/arm/include/asm/arch-mediatek/reset.h b/arch/arm/include/asm/arch-mediatek/reset.h index 9704666d24..4ba0bad94e 100644 --- a/arch/arm/include/asm/arch-mediatek/reset.h +++ b/arch/arm/include/asm/arch-mediatek/reset.h @@ -6,7 +6,7 @@ #ifndef __MEDIATEK_RESET_H #define __MEDIATEK_RESET_H -#include +struct udevice; int mediatek_reset_bind(struct udevice *pdev, u32 regofs, u32 num_regs); diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 694c26d35f..fe8d5947cc 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 8ee024ff1a..8dfc8645fc 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -933,7 +933,7 @@ static void acquire_buildinfo(void) /* Get ARM Trusted Firmware commit id */ arm_smccc_smc(IMX_SIP_BUILDINFO, IMX_SIP_BUILDINFO_GET_COMMITHASH, - 0, 0 , 0, 0, 0, 0, &res); + 0, 0, 0, 0, 0, 0, &res); atf_commit = res.a0; if (atf_commit == 0xffffffff) { debug("ATF does not support build info\n"); diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index fdee0d4f64..17173f9839 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -460,6 +460,18 @@ config TARGET_MX6ULL_14X14_EVK select MX6ULL imply CMD_DM +config TARGET_MYS_6ULX + bool "MYiR MYS-6ULX" + select MX6ULL + select DM + select DM_ETH + select DM_GPIO + select DM_I2C + select DM_MMC + select DM_SERIAL + select DM_THERMAL + select SUPPORT_SPL + config TARGET_NITROGEN6X bool "nitrogen6x" imply USB_ETHER_ASIX diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 798fe74a3d..9cb61f5c34 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -218,7 +218,7 @@ const struct rproc_att hostmap[] = { { 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */ { 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */ { 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */ - { 0x80000000, 0x80000000, 0xe0000000 }, /* DDRC */ + { 0x80000000, 0x80000000, 0x60000000 }, /* DDRC */ { /* sentinel */ } }; #endif diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 1a231c67f5..76a5f7aca6 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -293,8 +293,7 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) CSF_PAD_SIZE, offset)) { image_entry(); } else { - puts("spl: ERROR: image authentication fail\n"); - hang(); + panic("spl: ERROR: image authentication fail\n"); } } } @@ -320,8 +319,7 @@ void board_spl_fit_post_load(ulong load_addr, size_t length) if (imx_hab_authenticate_image(load_addr, offset + IVT_SIZE + CSF_PAD_SIZE, offset)) { - puts("spl: ERROR: image authentication unsuccessful\n"); - hang(); + panic("spl: ERROR: image authentication unsuccessful\n"); } } #endif diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index 513be09c68..96be069ee8 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c index 70940f01f3..8aad4be467 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 2bd260e5d7..ff6b3c7e3d 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -20,14 +20,6 @@ config TARGET_MICROBLAZE_GENERIC endchoice -config STACK_SIZE - hex "Define max stack size that can be used by u-boot" - default 0x200000 - help - Defines Max stack size that can be used by u-boot so that the - initrd_high will be calculated as base stack pointer minus this - stack size. - source "board/xilinx/microblaze-generic/Kconfig" endmenu diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 997e145450..e0f6b6c4b3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -112,9 +112,11 @@ config ARCH_OCTEON select DISPLAY_CPUINFO select DMA_ADDR_T_64BIT select DM - select DM_SERIAL - select DM_GPIO select DM_ETH + select DM_GPIO + select DM_I2C + select DM_SERIAL + select DM_SPI select MIPS_L2_CACHE select MIPS_MACH_EARLY_INIT select MIPS_TUNE_OCTEON3 diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi index a7bd55f8ad..f5ad4a6213 100644 --- a/arch/mips/dts/mrvl,cn73xx.dtsi +++ b/arch/mips/dts/mrvl,cn73xx.dtsi @@ -5,6 +5,8 @@ /dts-v1/; +#include + / { #address-cells = <2>; #size-cells = <2>; @@ -38,6 +40,38 @@ #size-cells = <1>; }; + clk: clock { + compatible = "mrvl,octeon-clk"; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + gpio: gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-7890-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + nr-gpios = <32>; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (1 - edge rising + * 2 - edge falling + * 4 - level active high + * 8 - level active low) + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pins connect to 16 consecutive CUI bits */ + interrupts = <0x03000 4>, <0x03001 4>, + <0x03002 4>, <0x03003 4>, + <0x03004 4>, <0x03005 4>, + <0x03006 4>, <0x03007 4>, + <0x03008 4>, <0x03009 4>, + <0x0300a 4>, <0x0300b 4>, + <0x0300c 4>, <0x0300d 4>, + <0x0300e 4>, <0x0300f 4>; + }; + reset: reset@1180006001600 { compatible = "mrvl,cn7xxx-rst"; reg = <0x11800 0x06001600 0x0 0x200>; @@ -60,5 +94,37 @@ reg-shift = <3>; interrupts = <0x08040 4>; }; + + i2c0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-7890-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + /* INT_ST, INT_TS, INT_CORE */ + interrupts = <0x0b000 1>, <0x0b001 1>, <0x0b002 1>; + clock-frequency = <100000>; + clocks = <&clk OCTEON_CLK_IO>; + }; + + i2c1: i2c@1180000001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-7890-twsi"; + reg = <0x11800 0x00001200 0x0 0x200>; + /* INT_ST, INT_TS, INT_CORE */ + interrupts = <0x0b100 1>, <0x0b101 1>, <0x0b102 1>; + clock-frequency = <100000>; + clocks = <&clk OCTEON_CLK_IO>; + }; + + spi: spi@1070000001000 { + compatible = "cavium,octeon-3010-spi"; + reg = <0x10700 0x00001000 0x0 0x100>; + interrupts = <0x05001 1>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <25000000>; + clocks = <&clk OCTEON_CLK_IO>; + }; }; }; diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts b/arch/mips/dts/mrvl,octeon-ebb7304.dts index 4e9c2de7d4..6b2e5e84bc 100644 --- a/arch/mips/dts/mrvl,octeon-ebb7304.dts +++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts @@ -5,7 +5,7 @@ /dts-v1/; -/include/ "mrvl,cn73xx.dtsi" +#include "mrvl,cn73xx.dtsi" / { model = "cavium,ebb7304"; @@ -13,6 +13,7 @@ aliases { serial0 = &uart0; + spi0 = &spi; }; chosen { @@ -94,3 +95,21 @@ &uart0 { clock-frequency = <1200000000>; }; + +&i2c0 { + u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ + clock-frequency = <100000>; +}; + +&i2c1 { + u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ + clock-frequency = <100000>; +}; + +&spi { + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <2000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/mach-mscc/include/mach/jr2/jr2.h b/arch/mips/mach-mscc/include/mach/jr2/jr2.h index 67244f63fa..3a779e7035 100644 --- a/arch/mips/mach-mscc/include/mach/jr2/jr2.h +++ b/arch/mips/mach-mscc/include/mach/jr2/jr2.h @@ -8,9 +8,6 @@ #ifndef _MSCC_JR2_H_ #define _MSCC_JR2_H_ -#include -#include - /* * Target offset base(s) */ diff --git a/arch/mips/mach-mscc/include/mach/luton/luton.h b/arch/mips/mach-mscc/include/mach/luton/luton.h index 19f02ede66..dda665fc15 100644 --- a/arch/mips/mach-mscc/include/mach/luton/luton.h +++ b/arch/mips/mach-mscc/include/mach/luton/luton.h @@ -8,9 +8,6 @@ #ifndef _MSCC_OCELOT_H_ #define _MSCC_OCELOT_H_ -#include -#include - /* * Target offset base(s) */ diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h index 2cb2135d37..72b07c33cd 100644 --- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h @@ -8,9 +8,6 @@ #ifndef _MSCC_OCELOT_H_ #define _MSCC_OCELOT_H_ -#include -#include - /* * Target offset base(s) */ diff --git a/arch/mips/mach-mscc/include/mach/serval/serval.h b/arch/mips/mach-mscc/include/mach/serval/serval.h index 763d18fe62..a78c6e59bb 100644 --- a/arch/mips/mach-mscc/include/mach/serval/serval.h +++ b/arch/mips/mach-mscc/include/mach/serval/serval.h @@ -8,9 +8,6 @@ #ifndef _MSCC_SERVAL_H_ #define _MSCC_SERVAL_H_ -#include -#include - /* * Target offset base(s) */ diff --git a/arch/mips/mach-mscc/include/mach/servalt/servalt.h b/arch/mips/mach-mscc/include/mach/servalt/servalt.h index 9015bc7dad..4d7d0886dd 100644 --- a/arch/mips/mach-mscc/include/mach/servalt/servalt.h +++ b/arch/mips/mach-mscc/include/mach/servalt/servalt.h @@ -8,9 +8,6 @@ #ifndef _MSCC_SERVALT_H_ #define _MSCC_SERVALT_H_ -#include -#include - /* * Target offset base(s) */ diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index afdb4f4402..5302677ee4 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -3,6 +3,8 @@ * (C) Copyright 2019 SiFive, Inc */ +#include + / { cpus { assigned-clocks = <&prci PRCI_CLK_COREPLL>; @@ -59,6 +61,16 @@ reg = <0x0 0x2000000 0x0 0xc0000>; u-boot,dm-spl; }; + prci: clock-controller@10000000 { + #reset-cells = <1>; + resets = <&prci PRCI_RST_DDR_CTRL_N>, + <&prci PRCI_RST_DDR_AXI_N>, + <&prci PRCI_RST_DDR_AHB_N>, + <&prci PRCI_RST_DDR_PHY_N>, + <&prci PRCI_RST_GEMGXL_N>; + reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb", + "ddr_phy", "gemgxl_reset"; + }; dmc: dmc@100b0000 { compatible = "sifive,fu540-c000-ddr"; reg = <0x0 0x100b0000 0x0 0x0800 diff --git a/arch/riscv/include/asm/arch-fu540/reset.h b/arch/riscv/include/asm/arch-fu540/reset.h new file mode 100644 index 0000000000..e42797a395 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/reset.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2020 SiFive, Inc. + * + * Author: Sagar Kadam + */ + +#ifndef __RESET_SIFIVE_H +#define __RESET_SIFIVE_H + +int sifive_reset_bind(struct udevice *dev, ulong count); + +#endif diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index cbca69ef6b..a34b108fff 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -811,7 +811,7 @@ config S3_VGA_ROM_RUN graphics console won't work without VGA options ROMs. Set it to N if your kernel is only on a serial console. -config STACK_SIZE +config STACK_SIZE_RESUME hex depends on HAVE_ACPI_RESUME default 0x1000 diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c b/arch/x86/cpu/apollolake/fsp_bindings.c index 9130af9ce0..bbf04b5009 100644 --- a/arch/x86/cpu/apollolake/fsp_bindings.c +++ b/arch/x86/cpu/apollolake/fsp_bindings.c @@ -89,6 +89,28 @@ static void read_u32_prop(ofnode node, char *name, size_t count, u32 *dst) ofnode_read_u32_array(node, name, dst, count); } +/** + * read_u64_prop() - Read an u64 property from devicetree (scalar or array) + * @node: Valid node reference to read property from + * @name: Name of the property to read from + * @count: If the property is expected to be an array, this is the + * number of expected elements + * set to 0 if the property is expected to be a scalar + * @dst: Pointer to destination of where to save the value(s) read + * from devicetree + */ +static int read_u64_prop(ofnode node, char *name, size_t count, u64 *dst) +{ + if (count == 0) { + ofnode_read_u64(node, name, dst); + } else { + debug("ERROR: %s u64 arrays not supported!\n", __func__); + return -EINVAL; + } + + return 0; +} + /** * read_string_prop() - Read a string property from devicetree * @node: Valid node reference to read property from @@ -206,6 +228,12 @@ static int fsp_update_config_from_dtb(ofnode node, u8 *cfg, read_u32_prop(node, fspb->propname, fspb->count, (u32 *)&cfg[fspb->offset]); break; + case FSP_UINT64: + ret = read_u64_prop(node, fspb->propname, fspb->count, + (u64 *)&cfg[fspb->offset]); + if (ret) + return ret; + break; case FSP_STRING: read_string_prop(node, fspb->propname, fspb->count, (char *)&cfg[fspb->offset]); @@ -605,6 +633,17 @@ const struct fsp_binding fsp_m_bindings[] = { .offset = offsetof(struct fsp_m_config, variable_nvs_buffer_ptr), .propname = "fspm,variable-nvs-buffer-ptr", }, { + .type = FSP_UINT64, + .offset = offsetof(struct fsp_m_config, start_timer_ticker_of_pfet_assert), + .propname = "fspm,start-timer-ticker-of-pfet-assert", + }, { + .type = FSP_UINT8, .offset = offsetof(struct fsp_m_config, rt_en), + .propname = "fspm,rt-en", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, skip_pcie_power_sequence), + .propname = "fspm,skip-pcie-power-sequence", + }, { .propname = NULL } }; @@ -1794,6 +1833,18 @@ const struct fsp_binding fsp_s_bindings[] = { .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, port_usb20_hs_npre_drv_sel), }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, os_selection), + .propname = "fsps,os-selection", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, dptf_enabled), + .propname = "fsps,dptf-enabled", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pwm_enabled), + .propname = "fsps,pwm-enabled", + }, { .propname = NULL } }; diff --git a/arch/x86/cpu/call32.S b/arch/x86/cpu/call32.S index e185b9a42b..e641e781c0 100644 --- a/arch/x86/cpu/call32.S +++ b/arch/x86/cpu/call32.S @@ -32,8 +32,7 @@ cpu_call32: push %rdi /* 32-bit code segment */ lea compat(%rip), %rax push %rax - .byte 0x48 /* REX prefix to force 64-bit far return */ - retf + retfq .code32 compat: /* @@ -60,4 +59,4 @@ compat: /* Jump to the required target */ pushl %edi /* 32-bit code segment */ pushl %esi /* 32-bit target address */ - retf + retfl diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 99bc48021e..dd6b8753de 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include diff --git a/arch/x86/cpu/sipi_vector.S b/arch/x86/cpu/sipi_vector.S index 40cc27f1e1..fa1e6cb19a 100644 --- a/arch/x86/cpu/sipi_vector.S +++ b/arch/x86/cpu/sipi_vector.S @@ -131,12 +131,12 @@ ap_start: jnz microcode_done /* Determine if parallel microcode loading is allowed */ - cmp $0xffffffff, microcode_lock + cmpl $0xffffffff, microcode_lock je load_microcode /* Protect microcode loading */ lock_microcode: - lock bts $0, microcode_lock + lock btsl $0, microcode_lock jc lock_microcode load_microcode: @@ -154,7 +154,7 @@ load_microcode: popa /* Unconditionally unlock microcode loading */ - cmp $0xffffffff, microcode_lock + cmpl $0xffffffff, microcode_lock je microcode_done xor %eax, %eax diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h index 5275b75f3b..78c338e9ff 100644 --- a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h @@ -122,7 +122,10 @@ struct __packed fsp_m_config { /* 0x150 */ void *variable_nvs_buffer_ptr; - u8 reserved_fspm_upd[12]; + u64 start_timer_ticker_of_pfet_assert; + u8 rt_en; + u8 skip_pcie_power_sequence; + u8 reserved_fspm_upd[2]; }; /** FSP-M UPD Configuration */ diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h index 451a7a254a..be80f5db09 100644 --- a/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h @@ -351,7 +351,10 @@ struct __packed fsp_s_config { u8 port_usb20_hs_npre_drv_sel[8]; /* 0x370 */ - u8 reserved_fsps_upd[16]; + u8 os_selection; + u8 dptf_enabled; + u8 pwm_enabled; + u8 reserved_fsps_upd[13]; }; /** struct fsps_upd - FSP-S Configuration */ @@ -563,4 +566,8 @@ struct __packed fsps_upd { #define PCIE_RP_SELECTABLE_DEEMPHASIS_6_DB 0 #define PCIE_RP_SELECTABLE_DEEMPHASIS_3_5_DB 1 +#define OS_SELECTION_WINDOWS 0 +#define OS_SELECTION_ANDROID 1 +#define OS_SELECTION_LINUX 3 + #endif diff --git a/arch/x86/include/asm/arch-apollolake/fsp_bindings.h b/arch/x86/include/asm/arch-apollolake/fsp_bindings.h index b4939519ce..a80e66bbfa 100644 --- a/arch/x86/include/asm/arch-apollolake/fsp_bindings.h +++ b/arch/x86/include/asm/arch-apollolake/fsp_bindings.h @@ -17,6 +17,7 @@ enum conf_type { FSP_UINT8, FSP_UINT16, FSP_UINT32, + FSP_UINT64, FSP_STRING, FSP_LPDDR4_SWIZZLE, }; diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index e5c916070c..bee0760c2d 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -12,8 +12,8 @@ * Intel interrupt router configuration mechanism * * There are two known ways of Intel interrupt router configuration mechanism - * so far. On most cases, the IRQ routing configuraiton is controlled by PCI - * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0). + * so far. On most cases, the IRQ routing configuration is controlled by PCI + * configuration registers on the legacy bridge, normally PCI BDF(0, 31, 0). * On some newer platforms like BayTrail and Braswell, the IRQ routing is now * in the IBASE register block where IBASE is memory-mapped. */ @@ -36,7 +36,7 @@ struct pirq_regmap { * @link_base: link value base number * @link_num: number of PIRQ links supported * @has_regmap: has mapping table between PIRQ link and routing register offset - * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means + * @irq_mask: IRQ mask representing the 16 IRQs in 8259, bit N is 1 means * IRQ N is available to be routed * @lb_bdf: irq router's PCI bus/device/function number encoding * @ibase: IBASE register block base address diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 01d498c21e..faa819fab4 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -121,7 +121,7 @@ unsigned int install_e820_map(unsigned int max_entries, ulong stack_size; stack_size = CONFIG_IS_ENABLED(HAVE_ACPI_RESUME, - (CONFIG_STACK_SIZE), (0)); + (CONFIG_STACK_SIZE_RESUME), (0)); /* * Everything between U-Boot's stack and ram top needs to be * reserved in order for ACPI S3 resume to work. diff --git a/board/atmel/common/board.c b/board/atmel/common/board.c index c41706c400..eee5c357bd 100644 --- a/board/atmel/common/board.c +++ b/board/atmel/common/board.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c index ada7cf5eb7..5f44714301 100644 --- a/board/liebherr/display5/display5.c +++ b/board/liebherr/display5/display5.c @@ -27,7 +27,6 @@ #include #include -#include #include #include diff --git a/board/mscc/servalt/servalt.c b/board/mscc/servalt/servalt.c index d0e6016b9a..879f5de506 100644 --- a/board/mscc/servalt/servalt.c +++ b/board/mscc/servalt/servalt.c @@ -9,6 +9,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + enum { BOARD_TYPE_PCB116 = 0xAABBCE00, }; diff --git a/board/myir/mys_6ulx/Kconfig b/board/myir/mys_6ulx/Kconfig new file mode 100644 index 0000000000..cbf72c6eca --- /dev/null +++ b/board/myir/mys_6ulx/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MYS_6ULX + +config SYS_BOARD + default "mys_6ulx" + +config SYS_VENDOR + default "myir" + +config SYS_CONFIG_NAME + default "mys_6ulx" + +endif diff --git a/board/myir/mys_6ulx/MAINTAINERS b/board/myir/mys_6ulx/MAINTAINERS new file mode 100644 index 0000000000..d4ee661182 --- /dev/null +++ b/board/myir/mys_6ulx/MAINTAINERS @@ -0,0 +1,9 @@ +MYS_6ULX BOARD +M: Parthiban Nallathambi +S: Maintained +F: arch/arm/dts/imx6ull-myir-mys-6ulx-nand.dts +F: arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi +F: arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi +F: board/myir/mys_6ulx/ +F: configs/myir_mys_6ulx_defconfig +F: include/configs/mys_6ulx.h diff --git a/board/myir/mys_6ulx/Makefile b/board/myir/mys_6ulx/Makefile new file mode 100644 index 0000000000..3c63e439ab --- /dev/null +++ b/board/myir/mys_6ulx/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := mys_6ulx.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/myir/mys_6ulx/README b/board/myir/mys_6ulx/README new file mode 100644 index 0000000000..a0996659c9 --- /dev/null +++ b/board/myir/mys_6ulx/README @@ -0,0 +1,52 @@ +How to use U-Boot on MYiR MYS-6ULX Single Board Computer +-------------------------------------------------------- + +- Configure and build U-Boot for MYS-6ULX iMX6ULL: + + $ make mrproper + $ make myir_mys_6ulx_defconfig + $ make + + This will generate SPL and u-boot-dtb.img images. + +Boot from MMC/SD: +- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card: + + $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Boot mode settings: + + Boot switch position: SW1 -> 0 + SW2 -> 1 + SW3 -> 0 + SW4 -> 1 + +Boot from NAND: +- Boot the board using SD/MMC or Serial download and load the SPL into memory +either from SD/MMC or TFTP. + +Default MTD layout is 512k(spl),1m(uboot),1m(uboot-dup),-(ubi) + +Flash SPL to NAND from SD/MMC, + + $ ext4load mmc 0:2 $loadaddr SPL + $ nand erase.part spl + $ nandbcb init $loadaddr 0x0 $filesize + +Flash u-boot proper to NAND from SD/MMC, + + $ ext4load mmc 0:2 $loadaddr u-boot-dtb.img + $ nand erase.part uboot + $ nand write $loadaddr uboot $filesize + +- Boot mode settings: + + Boot switch position: SW1 -> 1 + SW2 -> 0 + SW3 -> 0 + SW4 -> 1 + +- Connect the Serial cable to UART0 and the PC for the console. + +- Reset the board using and U-Boot should boot from NAND. diff --git a/board/myir/mys_6ulx/mys_6ulx.c b/board/myir/mys_6ulx/mys_6ulx.c new file mode 100644 index 0000000000..d886af05be --- /dev/null +++ b/board/myir/mys_6ulx/mys_6ulx.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart5_pads[] = { + MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); +} + +#ifdef CONFIG_FEC_MXC + +static int setup_fec(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(0, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + /* + * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select + * 50 MHz RMII clock mode. + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif /* CONFIG_FEC_MXC */ + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + return 0; +} + +int checkboard(void) +{ + u32 cpurev = get_cpu_rev(); + + printf("Board: MYiR MYS-6ULX %s Single Board Computer\n", + get_imx_type((cpurev & 0xFF000) >> 12)); + + return 0; +} diff --git a/board/myir/mys_6ulx/spl.c b/board/myir/mys_6ulx/spl.c new file mode 100644 index 0000000000..5cd4d05283 --- /dev/null +++ b/board/myir/mys_6ulx/spl.c @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Configuration for Micron MT41K128M16JT-125, 32M x 16 x 8 -> 256MiB */ + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x41480148, + .p0_mprddlctl = 0x40403E42, + .p0_mpwrdlctl = 0x40405852, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, /* Bus size = 16bit */ + .cs_density = 32, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1, + .rtt_nom = 1, + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .pd_fast_exit = 1, + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ +}; + +/* MT41K128M16JT-125 (2Gb density) */ +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); +} + +static void spl_dram_init(void) +{ + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +#ifdef CONFIG_FSL_ESDHC_IMX + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifndef CONFIG_NAND_MXS +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { + .esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4, + }, +#ifndef CONFIG_NAND_MXS + { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 8, + }, +#endif +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; +#ifndef CONFIG_NAND_MXS + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; +#endif + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +#endif /* CONFIG_FSL_ESDHC_IMX */ + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* Setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* Setup iomux and fec */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); +} diff --git a/board/phytec/pcm058/README b/board/phytec/pcm058/README index 02be0994fc..687366bffb 100644 --- a/board/phytec/pcm058/README +++ b/board/phytec/pcm058/README @@ -61,17 +61,21 @@ Then, clear the SPI flash: => sf probe => sf erase 0x0 0x1000000 -Load the SPL from raw MMC into memory and copy to the SPI. The SPL is maximum -392*512-byte blocks in size therefore 0x188 blocks, totaling 0x31000 bytes: +Load the equivalent of u-boot-with-spl.imx from the raw MMC into memory and +copy to the SPI. The SPL is expected at an offset of 0x400, and its size is +maximum 392*512-byte blocks in size, therefore 0x188 blocks, totaling 0x31000 +bytes. Assume U-boot should fit into 640KiB, therefore 0x500 512-byte blocks, +totalling 0xA0000 bytes. Adding these together: -=> mmc read ${loadaddr} 0x2 0x188 -=> sf write ${loadaddr} 0x400 0x31000 +=> mmc read ${loadaddr} 0x2 0x688 +=> sf write ${loadaddr} 0x400 0xD1000 -Load the U-boot binary into memory and copy to the SPI. U-boot should fit into -640KiB, so 0x500 512-byte blocks, totalling 0xA0000 bytes: +The SPL is located at offset 0x400, and U-boot at 0x31400 in SPI flash, as to +match the SD Card layout. This would allow, instead of reading from the SD Card +above, with networking and TFTP correctly configured, the equivalent of: -=> mmc read ${loadaddr} 0x18a 0x500 -=> sf write ${loadaddr} 0x40000 0xA0000 +=> tftp u-boot-with-spl.imx +=> sf write ${fileaddr} 0x400 ${filesize} The default NAND bootscripts expect a single MTD partition named "rootfs", which in turn contains the UBI volumes "fit" (which contains the kernel fit- diff --git a/board/st/common/stm32mp_dfu.c b/board/st/common/stm32mp_dfu.c index 0cda9196f9..38eb0f27c9 100644 --- a/board/st/common/stm32mp_dfu.c +++ b/board/st/common/stm32mp_dfu.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c index 55e2b5f05d..89b99a0b74 100644 --- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c +++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c @@ -57,32 +57,7 @@ static void setup_gpmi_nand(void) } #endif /* CONFIG_NAND_MXS */ -#ifdef CONFIG_VIDEO_MXS -static iomux_v3_cfg_t const lcd_pads[] = { - MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), -}; - +#ifdef CONFIG_DM_VIDEO static iomux_v3_cfg_t const backlight_pads[] = { /* Backlight On */ MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -95,8 +70,6 @@ static iomux_v3_cfg_t const backlight_pads[] = { static int setup_lcd(void) { - imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); - imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); /* Set BL_ON */ @@ -153,11 +126,6 @@ int board_init(void) #ifdef CONFIG_NAND_MXS setup_gpmi_nand(); #endif - -#ifdef CONFIG_VIDEO_MXS - setup_lcd(); -#endif - return 0; } @@ -203,6 +171,12 @@ int board_late_init(void) } #endif /* CONFIG_CMD_USB_SDP */ +#if defined(CONFIG_DM_VIDEO) + setup_lcd(); + + show_boot_logo(); +#endif + return 0; } diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS index 82246be160..61a504487a 100644 --- a/board/toradex/colibri_imx7/MAINTAINERS +++ b/board/toradex/colibri_imx7/MAINTAINERS @@ -9,5 +9,6 @@ F: include/configs/colibri_imx7.h F: configs/colibri_imx7_defconfig F: configs/colibri_imx7_emmc_defconfig F: arch/arm/dts/imx7-colibri.dtsi +F: arch/arm/dts/imx7-colibri-u-boot.dtsi F: arch/arm/dts/imx7-colibri-emmc.dts F: arch/arm/dts/imx7-colibri-rawnand.dts diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 26c285d88c..14df3fc42c 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -100,32 +100,7 @@ static void setup_gpmi_nand(void) } #endif -#ifdef CONFIG_VIDEO_MXS -static iomux_v3_cfg_t const lcd_pads[] = { - MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), -}; - +#ifdef CONFIG_DM_VIDEO static iomux_v3_cfg_t const backlight_pads[] = { /* Backlight On */ MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -139,8 +114,6 @@ static iomux_v3_cfg_t const backlight_pads[] = { static int setup_lcd(void) { - imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); - imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); /* Set BL_ON */ @@ -215,10 +188,6 @@ int board_init(void) setup_gpmi_nand(); #endif -#ifdef CONFIG_VIDEO_MXS - setup_lcd(); -#endif - #ifdef CONFIG_USB_EHCI_MX7 imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads)); gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); @@ -382,4 +351,15 @@ int board_usb_phy_mode(int port) return USB_INIT_HOST; } } + +int board_late_init(void) +{ +#if defined(CONFIG_DM_VIDEO) + setup_lcd(); + + show_boot_logo(); +#endif + return 0; +} + #endif diff --git a/board/toradex/common/Kconfig b/board/toradex/common/Kconfig index 11f4aab359..36068d2e3b 100644 --- a/board/toradex/common/Kconfig +++ b/board/toradex/common/Kconfig @@ -20,6 +20,12 @@ config TDX_HAVE_NAND config TDX_HAVE_NOR bool +config TDX_HAVE_EEPROM + bool + +config TDX_HAVE_EEPROM_EXTRA + bool + if TDX_CFG_BLOCK config TDX_CFG_BLOCK_IS_IN_MMC @@ -37,6 +43,11 @@ config TDX_CFG_BLOCK_IS_IN_NOR depends on TDX_HAVE_NOR default y +config TDX_CFG_BLOCK_IS_IN_EEPROM + bool + depends on TDX_HAVE_EEPROM + default y + config TDX_CFG_BLOCK_DEV int "Toradex config block eMMC device ID" depends on TDX_CFG_BLOCK_IS_IN_MMC @@ -66,4 +77,11 @@ config TDX_CFG_BLOCK_2ND_ETHADDR Ethernet carrier boards. This options enables the code to set the second Ethernet address as environment variable (eth1addr). +config TDX_CFG_BLOCK_EXTRA + bool "Support for additional EEPROMs (carrier board, display adapter)" + depends on TDX_HAVE_EEPROM_EXTRA + help + Enables fetching auxilary config blocks from carrier board/display + adapter EEPROMs. + endif diff --git a/board/toradex/common/Makefile b/board/toradex/common/Makefile index 6b9fccb6b9..7b19b6e4c8 100644 --- a/board/toradex/common/Makefile +++ b/board/toradex/common/Makefile @@ -8,4 +8,5 @@ obj- := __dummy__.o else obj-$(CONFIG_TDX_CFG_BLOCK) += tdx-cfg-block.o obj-y += tdx-common.o +obj-y += tdx-eeprom.o endif diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 75216ecf6d..bf27b2fa66 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -5,6 +5,8 @@ #include #include "tdx-cfg-block.h" +#include "tdx-eeprom.h" + #include #include @@ -37,21 +39,31 @@ DECLARE_GLOBAL_DATA_PTR; #define TAG_VALID 0xcf01 #define TAG_MAC 0x0000 +#define TAG_CAR_SERIAL 0x0021 #define TAG_HW 0x0008 #define TAG_INVALID 0xffff #define TAG_FLAG_VALID 0x1 +#define TDX_EEPROM_ID_MODULE 0 +#define TDX_EEPROM_ID_CARRIER 1 + #if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC) #define TDX_CFG_BLOCK_MAX_SIZE 512 #elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND) #define TDX_CFG_BLOCK_MAX_SIZE 64 #elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR) #define TDX_CFG_BLOCK_MAX_SIZE 64 +#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_EEPROM) +#define TDX_CFG_BLOCK_MAX_SIZE 64 #else #error Toradex config block location not set #endif +#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA +#define TDX_CFG_BLOCK_EXTRA_MAX_SIZE 64 +#endif + struct toradex_tag { u32 len:14; u32 flags:2; @@ -62,6 +74,11 @@ bool valid_cfgblock; struct toradex_hw tdx_hw_tag; struct toradex_eth_addr tdx_eth_addr; u32 tdx_serial; +#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA +u32 tdx_car_serial; +bool valid_cfgblock_carrier; +struct toradex_hw tdx_car_hw_tag; +#endif const char * const toradex_modules[] = { [0] = "UNKNOWN MODULE", @@ -124,6 +141,18 @@ const char * const toradex_modules[] = { [57] = "Verdin iMX8M Mini DualLite 1GB", }; +const char * const toradex_carrier_boards[] = { + [0] = "UNKNOWN CARRIER BOARD", + [155] = "Dahlia", + [156] = "Verdin Development Board", +}; + +const char * const toradex_display_adapters[] = { + [0] = "UNKNOWN DISPLAY ADAPTER", + [157] = "Verdin DSI to HDMI Adapter", + [159] = "Verdin DSI to LVDS Adapter", +}; + #ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC static int tdx_cfg_block_mmc_storage(u8 *config_block, int write) { @@ -224,6 +253,20 @@ static int write_tdx_cfg_block_to_nor(unsigned char *config_block) } #endif +#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_EEPROM +static int read_tdx_cfg_block_from_eeprom(unsigned char *config_block) +{ + return read_tdx_eeprom_data(TDX_EEPROM_ID_MODULE, 0x0, config_block, + TDX_CFG_BLOCK_MAX_SIZE); +} + +static int write_tdx_cfg_block_to_eeprom(unsigned char *config_block) +{ + return write_tdx_eeprom_data(TDX_EEPROM_ID_MODULE, 0x0, config_block, + TDX_CFG_BLOCK_MAX_SIZE); +} +#endif + int read_tdx_cfg_block(void) { int ret = 0; @@ -247,6 +290,8 @@ int read_tdx_cfg_block(void) ret = read_tdx_cfg_block_from_nand(config_block); #elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR) ret = read_tdx_cfg_block_from_nor(config_block); +#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_EEPROM) + ret = read_tdx_cfg_block_from_eeprom(config_block); #else ret = -EINVAL; #endif @@ -263,7 +308,12 @@ int read_tdx_cfg_block(void) valid_cfgblock = true; offset = 4; - while (offset < TDX_CFG_BLOCK_MAX_SIZE) { + /* + * check if there is enough space for storing tag and value of the + * biggest element + */ + while (offset + sizeof(struct toradex_tag) + + sizeof(struct toradex_hw) < TDX_CFG_BLOCK_MAX_SIZE) { tag = (struct toradex_tag *)(config_block + offset); offset += 4; if (tag->id == TAG_INVALID) @@ -322,7 +372,6 @@ static int get_cfgblock_interactive(void) it = 'y'; #endif - #if defined(CONFIG_TARGET_APALIS_IMX8) || \ defined(CONFIG_TARGET_APALIS_IMX8X) || \ defined(CONFIG_TARGET_COLIBRI_IMX6ULL) || \ @@ -493,7 +542,8 @@ static int get_cfgblock_interactive(void) return 0; } -static int get_cfgblock_barcode(char *barcode) +static int get_cfgblock_barcode(char *barcode, struct toradex_hw *tag, + u32 *serial) { if (strlen(barcode) < 16) { printf("Argument too short, barcode is 16 chars long\n"); @@ -501,30 +551,137 @@ static int get_cfgblock_barcode(char *barcode) } /* Get hardware information from the first 8 digits */ - tdx_hw_tag.ver_major = barcode[4] - '0'; - tdx_hw_tag.ver_minor = barcode[5] - '0'; - tdx_hw_tag.ver_assembly = barcode[7] - '0'; + tag->ver_major = barcode[4] - '0'; + tag->ver_minor = barcode[5] - '0'; + tag->ver_assembly = barcode[7] - '0'; barcode[4] = '\0'; - tdx_hw_tag.prodid = simple_strtoul(barcode, NULL, 10); + tag->prodid = simple_strtoul(barcode, NULL, 10); /* Parse second part of the barcode (serial number */ barcode += 8; - tdx_serial = simple_strtoul(barcode, NULL, 10); + *serial = simple_strtoul(barcode, NULL, 10); return 0; } -static int do_cfgblock_create(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) +static int write_tag(u8 *config_block, int *offset, int tag_id, + u8 *tag_data, size_t tag_data_size) { - u8 *config_block; struct toradex_tag *tag; - size_t size = TDX_CFG_BLOCK_MAX_SIZE; + + if (!offset || !config_block) + return -EINVAL; + + tag = (struct toradex_tag *)(config_block + *offset); + tag->id = tag_id; + tag->flags = TAG_FLAG_VALID; + /* len is provided as number of 32bit values after the tag */ + tag->len = (tag_data_size + sizeof(u32) - 1) / sizeof(u32); + *offset += sizeof(struct toradex_tag); + if (tag_data && tag_data_size) { + memcpy(config_block + *offset, tag_data, + tag_data_size); + *offset += tag_data_size; + } + + return 0; +} + +#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA +int read_tdx_cfg_block_carrier(void) +{ + int ret = 0; + u8 *config_block = NULL; + struct toradex_tag *tag; + size_t size = TDX_CFG_BLOCK_EXTRA_MAX_SIZE; + int offset; + + /* Allocate RAM area for carrier config block */ + config_block = memalign(ARCH_DMA_MINALIGN, size); + if (!config_block) { + printf("Not enough malloc space available!\n"); + return -ENOMEM; + } + + memset(config_block, 0, size); + + ret = read_tdx_eeprom_data(TDX_EEPROM_ID_CARRIER, 0x0, config_block, + size); + if (ret) + return ret; + + /* Expect a valid tag first */ + tag = (struct toradex_tag *)config_block; + if (tag->flags != TAG_FLAG_VALID || tag->id != TAG_VALID) { + valid_cfgblock_carrier = false; + ret = -EINVAL; + goto out; + } + valid_cfgblock_carrier = true; + offset = 4; + + while (offset + sizeof(struct toradex_tag) + + sizeof(struct toradex_hw) < TDX_CFG_BLOCK_MAX_SIZE) { + tag = (struct toradex_tag *)(config_block + offset); + offset += 4; + if (tag->id == TAG_INVALID) + break; + + if (tag->flags == TAG_FLAG_VALID) { + switch (tag->id) { + case TAG_CAR_SERIAL: + memcpy(&tdx_car_serial, config_block + offset, + sizeof(tdx_car_serial)); + break; + case TAG_HW: + memcpy(&tdx_car_hw_tag, config_block + + offset, 8); + break; + } + } + + /* Get to next tag according to current tags length */ + offset += tag->len * 4; + } +out: + free(config_block); + return ret; +} + +int check_pid8_sanity(char *pid8) +{ + char s_carrierid_verdin_dev[5]; + char s_carrierid_dahlia[5]; + + sprintf(s_carrierid_verdin_dev, "0%d", VERDIN_DEVELOPMENT_BOARD); + sprintf(s_carrierid_dahlia, "0%d", DAHLIA); + + /* sane value check, first 4 chars which represent carrier id */ + if (!strncmp(pid8, s_carrierid_verdin_dev, 4)) + return 0; + + if (!strncmp(pid8, s_carrierid_dahlia, 4)) + return 0; + + return -EINVAL; +} + +int try_migrate_tdx_cfg_block_carrier(void) +{ + char pid8[8]; int offset = 0; int ret = CMD_RET_SUCCESS; - int err; - int force_overwrite = 0; + size_t size = TDX_CFG_BLOCK_EXTRA_MAX_SIZE; + u8 *config_block; + + memset(pid8, 0x0, 8); + ret = read_tdx_eeprom_data(TDX_EEPROM_ID_CARRIER, 0x0, (u8 *)pid8, 8); + if (ret) + return ret; + + if (check_pid8_sanity(pid8)) + return -EINVAL; /* Allocate RAM area for config block */ config_block = memalign(ARCH_DMA_MINALIGN, size); @@ -534,12 +691,189 @@ static int do_cfgblock_create(struct cmd_tbl *cmdtp, int flag, int argc, } memset(config_block, 0xff, size); + /* we try parse PID8 concatenating zeroed serial number */ + tdx_car_hw_tag.ver_major = pid8[4] - '0'; + tdx_car_hw_tag.ver_minor = pid8[5] - '0'; + tdx_car_hw_tag.ver_assembly = pid8[7] - '0'; + + pid8[4] = '\0'; + tdx_car_hw_tag.prodid = simple_strtoul(pid8, NULL, 10); + + /* Valid Tag */ + write_tag(config_block, &offset, TAG_VALID, NULL, 0); + + /* Product Tag */ + write_tag(config_block, &offset, TAG_HW, (u8 *)&tdx_car_hw_tag, + sizeof(tdx_car_hw_tag)); + + /* Serial Tag */ + write_tag(config_block, &offset, TAG_CAR_SERIAL, (u8 *)&tdx_car_serial, + sizeof(tdx_car_serial)); + + memset(config_block + offset, 0, 32 - offset); + ret = write_tdx_eeprom_data(TDX_EEPROM_ID_CARRIER, 0x0, config_block, + size); + if (ret) { + printf("Failed to write Toradex Extra config block: %d\n", + ret); + ret = CMD_RET_FAILURE; + goto out; + } + + printf("Successfully migrated to Toradex Config Block from PID8\n"); + +out: + free(config_block); + return ret; +} + +static int get_cfgblock_carrier_interactive(void) +{ + char message[CONFIG_SYS_CBSIZE]; + int len; + + printf("Supported carrier boards:\n"); + printf("CARRIER BOARD NAME\t\t [ID]\n"); + for (int i = 0; i < sizeof(toradex_carrier_boards) / + sizeof(toradex_carrier_boards[0]); i++) + if (toradex_carrier_boards[i]) + printf("%s \t\t [%d]\n", toradex_carrier_boards[i], i); + + sprintf(message, "Choose your carrier board (provide ID): "); + len = cli_readline(message); + tdx_car_hw_tag.prodid = simple_strtoul(console_buffer, NULL, 10); + + do { + sprintf(message, "Enter carrier board version (e.g. V1.1B): V"); + len = cli_readline(message); + } while (len < 4); + + tdx_car_hw_tag.ver_major = console_buffer[0] - '0'; + tdx_car_hw_tag.ver_minor = console_buffer[2] - '0'; + tdx_car_hw_tag.ver_assembly = console_buffer[3] - 'A'; + + while (len < 8) { + sprintf(message, "Enter carrier board serial number: "); + len = cli_readline(message); + } + + tdx_car_serial = simple_strtoul(console_buffer, NULL, 10); + + return 0; +} + +static int do_cfgblock_carrier_create(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + u8 *config_block; + size_t size = TDX_CFG_BLOCK_EXTRA_MAX_SIZE; + int offset = 0; + int ret = CMD_RET_SUCCESS; + int err; + int force_overwrite = 0; if (argc >= 3) { if (argv[2][0] == '-' && argv[2][1] == 'y') force_overwrite = 1; } + /* Allocate RAM area for config block */ + config_block = memalign(ARCH_DMA_MINALIGN, size); + if (!config_block) { + printf("Not enough malloc space available!\n"); + return CMD_RET_FAILURE; + } + + memset(config_block, 0xff, size); + read_tdx_cfg_block_carrier(); + if (valid_cfgblock_carrier && !force_overwrite) { + char message[CONFIG_SYS_CBSIZE]; + + sprintf(message, "A valid Toradex Carrier config block is present, still recreate? [y/N] "); + + if (!cli_readline(message)) + goto out; + + if (console_buffer[0] != 'y' && + console_buffer[0] != 'Y') + goto out; + } + + if (argc < 3 || (force_overwrite && argc < 4)) { + err = get_cfgblock_carrier_interactive(); + } else { + if (force_overwrite) + err = get_cfgblock_barcode(argv[3], &tdx_car_hw_tag, + &tdx_car_serial); + else + err = get_cfgblock_barcode(argv[2], &tdx_car_hw_tag, + &tdx_car_serial); + } + + if (err) { + ret = CMD_RET_FAILURE; + goto out; + } + + /* Valid Tag */ + write_tag(config_block, &offset, TAG_VALID, NULL, 0); + + /* Product Tag */ + write_tag(config_block, &offset, TAG_HW, (u8 *)&tdx_car_hw_tag, + sizeof(tdx_car_hw_tag)); + + /* Serial Tag */ + write_tag(config_block, &offset, TAG_CAR_SERIAL, (u8 *)&tdx_car_serial, + sizeof(tdx_car_serial)); + + memset(config_block + offset, 0, 32 - offset); + err = write_tdx_eeprom_data(TDX_EEPROM_ID_CARRIER, 0x0, config_block, + size); + if (err) { + printf("Failed to write Toradex Extra config block: %d\n", + ret); + ret = CMD_RET_FAILURE; + goto out; + } + + printf("Toradex Extra config block successfully written\n"); + +out: + free(config_block); + return ret; +} + +#endif /* CONFIG_TDX_CFG_BLOCK_EXTRA */ + +static int do_cfgblock_create(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + u8 *config_block; + size_t size = TDX_CFG_BLOCK_MAX_SIZE; + int offset = 0; + int ret = CMD_RET_SUCCESS; + int err; + int force_overwrite = 0; + + if (argc >= 3) { +#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA + if (!strcmp(argv[2], "carrier")) + return do_cfgblock_carrier_create(cmdtp, flag, + --argc, ++argv); +#endif /* CONFIG_TDX_CFG_BLOCK_EXTRA */ + if (argv[2][0] == '-' && argv[2][1] == 'y') + force_overwrite = 1; + } + + /* Allocate RAM area for config block */ + config_block = memalign(ARCH_DMA_MINALIGN, size); + if (!config_block) { + printf("Not enough malloc space available!\n"); + return CMD_RET_FAILURE; + } + + memset(config_block, 0xff, size); + read_tdx_cfg_block(); if (valid_cfgblock) { #if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND) @@ -581,9 +915,11 @@ static int do_cfgblock_create(struct cmd_tbl *cmdtp, int flag, int argc, err = get_cfgblock_interactive(); } else { if (force_overwrite) - err = get_cfgblock_barcode(argv[3]); + err = get_cfgblock_barcode(argv[3], &tdx_hw_tag, + &tdx_serial); else - err = get_cfgblock_barcode(argv[2]); + err = get_cfgblock_barcode(argv[2], &tdx_hw_tag, + &tdx_serial); } if (err) { ret = CMD_RET_FAILURE; @@ -595,39 +931,25 @@ static int do_cfgblock_create(struct cmd_tbl *cmdtp, int flag, int argc, tdx_eth_addr.nic = htonl(tdx_serial << 8); /* Valid Tag */ - tag = (struct toradex_tag *)config_block; - tag->id = TAG_VALID; - tag->flags = TAG_FLAG_VALID; - tag->len = 0; - offset += 4; + write_tag(config_block, &offset, TAG_VALID, NULL, 0); /* Product Tag */ - tag = (struct toradex_tag *)(config_block + offset); - tag->id = TAG_HW; - tag->flags = TAG_FLAG_VALID; - tag->len = 2; - offset += 4; - - memcpy(config_block + offset, &tdx_hw_tag, 8); - offset += 8; + write_tag(config_block, &offset, TAG_HW, (u8 *)&tdx_hw_tag, + sizeof(tdx_hw_tag)); /* MAC Tag */ - tag = (struct toradex_tag *)(config_block + offset); - tag->id = TAG_MAC; - tag->flags = TAG_FLAG_VALID; - tag->len = 2; - offset += 4; + write_tag(config_block, &offset, TAG_MAC, (u8 *)&tdx_eth_addr, + sizeof(tdx_eth_addr)); - memcpy(config_block + offset, &tdx_eth_addr, 6); - offset += 6; memset(config_block + offset, 0, 32 - offset); - #if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC) err = tdx_cfg_block_mmc_storage(config_block, 1); #elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND) err = write_tdx_cfg_block_to_nand(config_block); #elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR) err = write_tdx_cfg_block_to_nor(config_block); +#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_EEPROM) + err = write_tdx_cfg_block_to_eeprom(config_block); #else err = -EINVAL; #endif @@ -667,8 +989,10 @@ static int do_cfgblock(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_USAGE; } -U_BOOT_CMD(cfgblock, 4, 0, do_cfgblock, - "Toradex config block handling commands", - "create [-y] [barcode] - (Re-)create Toradex config block\n" - "cfgblock reload - Reload Toradex config block from flash" +U_BOOT_CMD( + cfgblock, 5, 0, do_cfgblock, + "Toradex config block handling commands", + "create [-y] [barcode] - (Re-)create Toradex config block\n" + "create carrier [-y] [barcode] - (Re-)create Toradex Carrier config block\n" + "cfgblock reload - Reload Toradex config block from flash" ); diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index d8f3941f26..8f91d9aec6 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -80,12 +80,28 @@ enum { VERDIN_IMX8MMDL, }; +enum { + DAHLIA = 155, + VERDIN_DEVELOPMENT_BOARD = 156, +}; + +enum { + VERDIN_DSI_TO_HDMI_ADAPTER = 157, + VERDIN_DSI_TO_LVDS_ADAPTER = 159, +}; + extern const char * const toradex_modules[]; +extern const char * const toradex_carrier_boards[]; extern bool valid_cfgblock; extern struct toradex_hw tdx_hw_tag; +extern struct toradex_hw tdx_car_hw_tag; extern struct toradex_eth_addr tdx_eth_addr; extern u32 tdx_serial; +extern u32 tdx_car_serial; int read_tdx_cfg_block(void); +int read_tdx_cfg_block_carrier(void); + +int try_migrate_tdx_cfg_block_carrier(void); #endif /* _TDX_CFG_BLOCK_H */ diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index 3a3cfc8821..fe5295f94b 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -9,6 +9,13 @@ #include #include +#ifdef CONFIG_DM_VIDEO +#include +#include +#include +#include +#endif + #include "tdx-cfg-block.h" #include #include "tdx-common.h" @@ -19,6 +26,12 @@ static char tdx_serial_str[9]; static char tdx_board_rev_str[6]; +#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA +static char tdx_car_serial_str[9]; +static char tdx_car_rev_str[6]; +static char *tdx_carrier_board_name; +#endif + #ifdef CONFIG_REVISION_TAG u32 get_board_rev(void) { @@ -88,6 +101,28 @@ int show_board_info(void) toradex_modules[tdx_hw_tag.prodid], tdx_board_rev_str, tdx_serial_str); +#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA + if (read_tdx_cfg_block_carrier()) { + printf("MISSING TORADEX CARRIER CONFIG BLOCKS\n"); + try_migrate_tdx_cfg_block_carrier(); + } else { + tdx_carrier_board_name = (char *) + toradex_carrier_boards[tdx_car_hw_tag.prodid]; + + sprintf(tdx_car_serial_str, "%08u", tdx_car_serial); + sprintf(tdx_car_rev_str, "V%1d.%1d%c", + tdx_car_hw_tag.ver_major, + tdx_car_hw_tag.ver_minor, + (char)tdx_car_hw_tag.ver_assembly + + 'A'); + + env_set("carrier_serial#", tdx_car_serial_str); + printf("Carrier: Toradex %s %s, Serial# %s\n", + tdx_carrier_board_name, + tdx_car_rev_str, + tdx_car_serial_str); + } +#endif } /* @@ -168,3 +203,22 @@ int ft_common_board_setup(void *blob, struct bd_info *bd) } #endif /* CONFIG_TDX_CFG_BLOCK */ + +#if defined(CONFIG_DM_VIDEO) +int show_boot_logo(void) +{ + struct udevice *dev; + int ret; + int xpos, ypos; + + splash_get_pos(&xpos, &ypos); + + ret = uclass_get_device(UCLASS_VIDEO, 0, &dev); + if (ret) + return ret; + + ret = video_bmp_display(dev, (ulong)bmp_logo_bitmap, xpos, ypos, true); + + return ret; +} +#endif /* CONFIG_DM_VIDEO */ diff --git a/board/toradex/common/tdx-common.h b/board/toradex/common/tdx-common.h index 81375de598..8020df5b44 100644 --- a/board/toradex/common/tdx-common.h +++ b/board/toradex/common/tdx-common.h @@ -11,4 +11,8 @@ int ft_common_board_setup(void *blob, struct bd_info *bd); +#if defined(CONFIG_DM_VIDEO) +int show_boot_logo(void); +#endif + #endif /* _TDX_COMMON_H */ diff --git a/board/toradex/common/tdx-eeprom.c b/board/toradex/common/tdx-eeprom.c new file mode 100644 index 0000000000..fbc267dab6 --- /dev/null +++ b/board/toradex/common/tdx-eeprom.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Toradex + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int get_tdx_eeprom(u32 eeprom_id, struct udevice **devp) +{ + int ret = 0; + int node; + ofnode eeprom; + char eeprom_str[16]; + const char *path; + + if (!gd->fdt_blob) { + printf("%s: don't have a valid gd->fdt_blob!\n", __func__); + return -EFAULT; + } + + node = fdt_path_offset(gd->fdt_blob, "/aliases"); + if (node < 0) + return -ENODEV; + + sprintf(eeprom_str, "eeprom%d", eeprom_id); + + path = fdt_getprop(gd->fdt_blob, node, eeprom_str, NULL); + if (!path) { + printf("%s: no alias for %s\n", __func__, eeprom_str); + return -ENODEV; + } + + eeprom = ofnode_path(path); + if (!ofnode_valid(eeprom)) { + printf("%s: invalid hardware path to EEPROM\n", __func__); + return -ENODEV; + } + + ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, devp); + if (ret) { + printf("%s: cannot find EEPROM by node\n", __func__); + return ret; + } + + return ret; +} + +int read_tdx_eeprom_data(u32 eeprom_id, int offset, u8 *buf, + int size) +{ + struct udevice *dev; + int ret; + + ret = get_tdx_eeprom(eeprom_id, &dev); + if (ret) + return ret; + + ret = i2c_eeprom_read(dev, 0x0, buf, size); + if (ret) { + printf("%s: error reading data from EEPROM id: %d!, ret = %d\n", + __func__, eeprom_id, ret); + return ret; + } + + return ret; +} + +int write_tdx_eeprom_data(u32 eeprom_id, int offset, u8 *buf, + int size) +{ + struct udevice *dev; + int ret; + + ret = get_tdx_eeprom(eeprom_id, &dev); + if (ret) + return ret; + + ret = i2c_eeprom_write(dev, 0x0, buf, size); + if (ret) { + printf("%s: error writing data to EEPROM id: %d, ret = %d\n", + __func__, eeprom_id, ret); + return ret; + } + + return ret; +} diff --git a/board/toradex/common/tdx-eeprom.h b/board/toradex/common/tdx-eeprom.h new file mode 100644 index 0000000000..a6772d2f3f --- /dev/null +++ b/board/toradex/common/tdx-eeprom.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2020 Toradex + */ + +#ifndef _TDX_EEPROM_H +#define _TDX_EEPROM_H + +#include + +int read_tdx_eeprom_data(u32 eeprom_id, int offset, uint8_t *buf, int size); +int write_tdx_eeprom_data(u32 eeprom_id, int offset, uint8_t *buf, int size); + +#endif /* _TDX_EEPROM_H */ diff --git a/board/toradex/verdin-imx8mm/Kconfig b/board/toradex/verdin-imx8mm/Kconfig index 8a2fe98682..149aed6da7 100644 --- a/board/toradex/verdin-imx8mm/Kconfig +++ b/board/toradex/verdin-imx8mm/Kconfig @@ -12,9 +12,15 @@ config SYS_CONFIG_NAME config TDX_CFG_BLOCK default y +config TDX_CFG_BLOCK_EXTRA + default y + config TDX_HAVE_MMC default y +config TDX_HAVE_EEPROM_EXTRA + default y + config TDX_CFG_BLOCK_DEV default "0" diff --git a/cmd/demo.c b/cmd/demo.c index 9da06f5e4d..f923533f79 100644 --- a/cmd/demo.c +++ b/cmd/demo.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include diff --git a/cmd/mdio.c b/cmd/mdio.c index c48bb51237..cfa45ad12a 100644 --- a/cmd/mdio.c +++ b/cmd/mdio.c @@ -10,6 +10,7 @@ #include #include +#include #include #include diff --git a/cmd/mii.c b/cmd/mii.c index b52a55dc33..fe8602eb7c 100644 --- a/cmd/mii.c +++ b/cmd/mii.c @@ -10,6 +10,7 @@ #include #include +#include #include typedef struct _MII_field_desc_t { diff --git a/cmd/w1.c b/cmd/w1.c index 92be1f2531..459094bf80 100644 --- a/cmd/w1.c +++ b/cmd/w1.c @@ -6,6 +6,7 @@ */ #include #include +#include #include #include #include diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 72c7165dc2..10605f1bab 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1529,6 +1529,16 @@ config TPL_SPI_FLASH_SUPPORT Enable support for using SPI flash in TPL. See SPL_SPI_FLASH_SUPPORT for details. +config TPL_SPI_FLASH_TINY + bool "Enable low footprint TPL SPI Flash support" + depends on TPL_SPI_FLASH_SUPPORT && !SPI_FLASH_BAR + default y if SPI_FLASH + help + Enable lightweight TPL SPI Flash support that supports just reading + data/images from flash. No support to write/erase flash. Enable + this if you have TPL size limitations and don't need full-fledged + SPI flash support. + config TPL_SPI_LOAD bool "Support loading from SPI flash" depends on TPL_SPI_FLASH_SUPPORT diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index d1716a3096..23108bd3b1 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -92,3 +92,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_FDT_FIXUP_PARTITIONS=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index b2cce8aa27..e409e09050 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -91,3 +91,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_FDT_FIXUP_PARTITIONS=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index b4334371eb..8355fef419 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -85,3 +85,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 0e1e64134b..02f7279b03 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -43,6 +43,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="imx6dl-hummingboard2-emmc-som-v15 imx6q-hummingboard2-emmc-som-v15" CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y +CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig new file mode 100644 index 0000000000..84463a3c4c --- /dev/null +++ b/configs/myir_mys_6ulx_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x4000 +CONFIG_TARGET_MYS_6ULX=y +CONFIG_SPL_TEXT_BASE=0x908000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_NR_DRAM_BANKS=8 +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-myir-mys-6ulx-eval" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_DMA=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_DEFAULT="gpmi-nand:512k(spl),1m(uboot),1m(uboot-dup),-(ubi)" +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_MXC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x180000 +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_SMBIOS_MANUFACTURER="MYiR" diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig index d810b1e45f..f8d27b01dc 100644 --- a/configs/octeon_ebb7304_defconfig +++ b/configs/octeon_ebb7304_defconfig @@ -1,9 +1,9 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0xffffffff80000000 CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEBUG_UART_BASE=0x8001180000000800 CONFIG_DEBUG_UART_CLOCK=1200000000 CONFIG_ARCH_OCTEON=y @@ -12,6 +12,8 @@ CONFIG_ARCH_OCTEON=y CONFIG_DEBUG_UART=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y CONFIG_CMD_DHCP=y @@ -29,10 +31,18 @@ CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_NETDEVICES is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y CONFIG_DEBUG_UART_SHIFT=3 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_OCTEON_SPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_OCTEON=y CONFIG_HEXDUMP=y diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig index e8a263bee5..045ef16ec7 100644 --- a/configs/pcm058_defconfig +++ b/configs/pcm058_defconfig @@ -7,7 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x31400 CONFIG_MX6_OCRAM_256KB=y CONFIG_TARGET_PCM058=y CONFIG_DM_GPIO=y @@ -35,6 +35,7 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x18a CONFIG_SPL_DMA=y CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig index 0a38941f61..0a602da837 100644 --- a/configs/pico-imx6_defconfig +++ b/configs/pico-imx6_defconfig @@ -66,6 +66,9 @@ CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_RGMII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig index 59804062d9..070ef66446 100644 --- a/configs/sifive_fu540_defconfig +++ b/configs/sifive_fu540_defconfig @@ -25,3 +25,5 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_CLK=y CONFIG_DM_MTD=y +CONFIG_SPL_DM_RESET=y +CONFIG_DM_RESET=y diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig index 96651f0268..459bf0d530 100644 --- a/configs/sipeed_maix_bitm_defconfig +++ b/configs/sipeed_maix_bitm_defconfig @@ -1,6 +1,7 @@ CONFIG_RISCV=y CONFIG_TARGET_SIPEED_MAIX=y CONFIG_ARCH_RV64I=y +CONFIG_STACK_SIZE=0x100000 # CONFIG_NET is not set # CONFIG_INPUT is not set # CONFIG_DM_ETH is not set diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index eb290554d6..f50a9952f4 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -101,6 +101,7 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_ANSI is not set CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set +CONFIG_VIDCONSOLE_AS_LCD=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y # CONFIG_GZIP is not set diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index ca8a1e3efb..937094ca9e 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -75,6 +75,7 @@ CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC_IMX=y diff --git a/doc/board/emulation/qemu-mips.rst b/doc/board/emulation/qemu-mips.rst index f206039f54..d35925126a 100644 --- a/doc/board/emulation/qemu-mips.rst +++ b/doc/board/emulation/qemu-mips.rst @@ -29,28 +29,28 @@ Using u-boot.bin as ROM (replaces Qemu monitor): .. code-block:: bash - make qemu_mips + make qemu_mips_defconfig qemu-system-mips -M mips -bios u-boot.bin -nographic 32 bit, little endian .. code-block:: bash - make qemu_mipsel + make qemu_mipsel_defconfig qemu-system-mipsel -M mips -bios u-boot.bin -nographic 64 bit, big endian .. code-block:: bash - make qemu_mips64 + make qemu_mips64_defconfig qemu-system-mips64 -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic 64 bit, little endian .. code-block:: bash - make qemu_mips64el + make qemu_mips64el_defconfig qemu-system-mips64el -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic or using u-boot.bin from emulated flash: diff --git a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt index 5311938f43..666400e085 100644 --- a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt +++ b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt @@ -240,6 +240,9 @@ Optional properties: - fspm,enable-reset-system: Enable Reset System - fspm,enable-s3-heci2: Enable HECI2 in S3 resume path - fspm,variable-nvs-buffer-ptr: +- fspm,start-timer-ticker-of-pfet-assert: PCIE SLOT Power Enable Assert Time - PFET +- fspm,rt-en: Real Time Enabling +- fspm,skip-pcie-power-sequence: Skip Pcie Power Sequence Example: diff --git a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt index 973d253ada..731a310cf8 100644 --- a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt +++ b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt @@ -463,6 +463,12 @@ Optional properties: - fsps,port-usb20-i-usb-tx-emphasis-en: PerPort HS Transmitter Emphasis - fsps,port-usb20-per-port-rxi-set: PerPort HS Receiver Bias - fsps,port-usb20-hs-npre-drv-sel: Delay/skew's strength control for HS driver +- fsps,os-selection: OS Selection + 0: Windows + 1: Android + 3: Linux +- fsps,dptf-enabled: DPTF +- fsps,pwm-enabled: PWM Enabled Example: diff --git a/drivers/adc/stm32-adc-core.c b/drivers/adc/stm32-adc-core.c index 31bbb6f9d6..f20c46fb36 100644 --- a/drivers/adc/stm32-adc-core.c +++ b/drivers/adc/stm32-adc-core.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/adc/stm32-adc-core.h b/drivers/adc/stm32-adc-core.h index ba0e10e6cc..05968dbcc8 100644 --- a/drivers/adc/stm32-adc-core.h +++ b/drivers/adc/stm32-adc-core.h @@ -26,9 +26,9 @@ #define STM32_ADC_MAX_ADCS 3 #define STM32_ADCX_COMN_OFFSET 0x300 -#include #include -#include + +struct udevice; /** * struct stm32_adc_common - stm32 ADC driver common data (for all instances) diff --git a/drivers/adc/stm32-adc.c b/drivers/adc/stm32-adc.c index b12f894a9b..3f0ed48846 100644 --- a/drivers/adc/stm32-adc.c +++ b/drivers/adc/stm32-adc.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 82cb1874e1..6003e140b5 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -83,6 +83,13 @@ config CLK_INTEL set up by U-Boot itself but only statically. Thus the driver does not support changing clock rates, only querying them. +config CLK_OCTEON + bool "Clock controller driver for Marvell MIPS Octeon" + depends on CLK && ARCH_OCTEON + default y + help + Enable this to support the clocks on Octeon MIPS platforms. + config CLK_STM32F bool "Enable clock driver support for STM32F family" depends on CLK && (STM32F7 || STM32F4) diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index d911954581..cda4b4b605 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o obj-$(CONFIG_CLK_K210) += kendryte/ obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o +obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_CLK_SIFIVE) += sifive/ diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 15656f5973..934cd5787a 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -25,6 +25,11 @@ static inline const struct clk_ops *clk_dev_ops(struct udevice *dev) return (const struct clk_ops *)dev->driver->ops; } +struct clk *dev_get_clk_ptr(struct udevice *dev) +{ + return (struct clk *)dev_get_uclass_priv(dev); +} + #if CONFIG_IS_ENABLED(OF_CONTROL) # if CONFIG_IS_ENABLED(OF_PLATDATA) int clk_get_by_driver_info(struct udevice *dev, struct phandle_1_arg *cells, diff --git a/drivers/clk/clk_octeon.c b/drivers/clk/clk_octeon.c new file mode 100644 index 0000000000..fd559e05fc --- /dev/null +++ b/drivers/clk/clk_octeon.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Stefan Roese + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct octeon_clk_priv { + u64 core_clk; + u64 io_clk; +}; + +static int octeon_clk_enable(struct clk *clk) +{ + /* Nothing to do on Octeon */ + return 0; +} + +static ulong octeon_clk_get_rate(struct clk *clk) +{ + struct octeon_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case OCTEON_CLK_CORE: + return priv->core_clk; + + case OCTEON_CLK_IO: + return priv->io_clk; + + default: + return 0; + } + + return 0; +} + +static struct clk_ops octeon_clk_ops = { + .enable = octeon_clk_enable, + .get_rate = octeon_clk_get_rate, +}; + +static const struct udevice_id octeon_clk_ids[] = { + { .compatible = "mrvl,octeon-clk" }, + { /* sentinel */ } +}; + +static int octeon_clk_probe(struct udevice *dev) +{ + struct octeon_clk_priv *priv = dev_get_priv(dev); + + /* + * The clock values are already read into GD, lets just store them + * in priv data + */ + priv->core_clk = gd->cpu_clk; + priv->io_clk = gd->bus_clk; + + return 0; +} + +U_BOOT_DRIVER(clk_octeon) = { + .name = "clk_octeon", + .id = UCLASS_CLK, + .of_match = octeon_clk_ids, + .ops = &octeon_clk_ops, + .probe = octeon_clk_probe, + .priv_auto_alloc_size = sizeof(struct octeon_clk_priv), +}; diff --git a/drivers/clk/kendryte/bypass.c b/drivers/clk/kendryte/bypass.c index d1fd28175b..5f1986f2cb 100644 --- a/drivers/clk/kendryte/bypass.c +++ b/drivers/clk/kendryte/bypass.c @@ -4,12 +4,15 @@ */ #define LOG_CATEGORY UCLASS_CLK -#include +#include +#include #include +#include +#include +#include #include #include -#include #define CLK_K210_BYPASS "k210_clk_bypass" diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c index 19e358856a..ab6d75d585 100644 --- a/drivers/clk/kendryte/pll.c +++ b/drivers/clk/kendryte/pll.c @@ -3,18 +3,20 @@ * Copyright (C) 2019-20 Sean Anderson */ #define LOG_CATEGORY UCLASS_CLK -#include -#include +#include +#include /* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */ #include +#include +#include +#include #include +#include #include #include #include #include -#include -#include #define CLK_K210_PLL "k210_clk_pll" diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index fe6e0d4073..c5148e9a37 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -30,17 +30,22 @@ #include #include +#include #include #include #include #include #include +#include +#include +#include #include #include #include #include #include +#include /* * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects: @@ -131,21 +136,18 @@ /* DEVICESRESETREG */ #define PRCI_DEVICESRESETREG_OFFSET 0x28 -#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0 +#define PRCI_DEVICERESETCNT 5 + #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT) -#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1 + (0x1 << PRCI_RST_DDR_CTRL_N) #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT) -#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2 + (0x1 << PRCI_RST_DDR_AXI_N) #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT) -#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3 + (0x1 << PRCI_RST_DDR_AHB_N) #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT) -#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5 + (0x1 << PRCI_RST_DDR_PHY_N) #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT) + (0x1 << PRCI_RST_GEMGXL_N) /* CLKMUXSTATUSREG */ #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c @@ -528,6 +530,41 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { .recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate, }; +static int __prci_consumer_reset(const char *rst_name, bool trigger) +{ + struct udevice *dev; + struct reset_ctl rst_sig; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_RESET, + DM_GET_DRIVER(sifive_reset), + &dev); + if (ret) { + dev_err(dev, "Reset driver not found: %d\n", ret); + return ret; + } + + ret = reset_get_by_name(dev, rst_name, &rst_sig); + if (ret) { + dev_err(dev, "failed to get %s reset\n", rst_name); + return ret; + } + + if (reset_valid(&rst_sig)) { + if (trigger) + ret = reset_deassert(&rst_sig); + else + ret = reset_assert(&rst_sig); + if (ret) { + dev_err(dev, "failed to trigger reset id = %ld\n", + rst_sig.id); + return ret; + } + } + + return ret; +} + /** * __prci_ddr_release_reset() - Release DDR reset * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg @@ -535,19 +572,20 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { */ static void __prci_ddr_release_reset(struct __prci_data *pd) { - u32 v; - - v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET); - v |= PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK; - __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd); + /* Release DDR ctrl reset */ + __prci_consumer_reset("ddr_ctrl", true); /* HACK to get the '1 full controller clock cycle'. */ asm volatile ("fence"); - v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET); - v |= (PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK | - PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK | - PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK); - __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd); + + /* Release DDR AXI reset */ + __prci_consumer_reset("ddr_axi", true); + + /* Release DDR AHB reset */ + __prci_consumer_reset("ddr_ahb", true); + + /* Release DDR PHY reset */ + __prci_consumer_reset("ddr_phy", true); /* HACK to get the '1 full controller clock cycle'. */ asm volatile ("fence"); @@ -567,12 +605,8 @@ static void __prci_ddr_release_reset(struct __prci_data *pd) */ static void __prci_ethernet_release_reset(struct __prci_data *pd) { - u32 v; - /* Release GEMGXL reset */ - v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET); - v |= PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK; - __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd); + __prci_consumer_reset("gemgxl_reset", true); /* Procmon => core clock */ __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET, @@ -757,6 +791,11 @@ static struct clk_ops sifive_fu540_prci_ops = { .disable = sifive_fu540_prci_disable, }; +static int sifive_fu540_clk_bind(struct udevice *dev) +{ + return sifive_reset_bind(dev, PRCI_DEVICERESETCNT); +} + static const struct udevice_id sifive_fu540_prci_ids[] = { { .compatible = "sifive,fu540-c000-prci" }, { } @@ -769,4 +808,5 @@ U_BOOT_DRIVER(sifive_fu540_prci) = { .probe = sifive_fu540_prci_probe, .ops = &sifive_fu540_prci_ops, .priv_auto_alloc_size = sizeof(struct __prci_data), + .bind = sifive_fu540_clk_bind, }; diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c index 20ae47bfb5..0f8baefb1f 100644 --- a/drivers/ddr/imx/imx8m/ddrphy_utils.c +++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* -* Copyright 2018 NXP -*/ + * Copyright 2018 NXP + */ #include #include @@ -201,7 +201,7 @@ unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) } unsigned int look_for_max(unsigned int data[], - unsigned int addr_start, unsigned int addr_end) + unsigned int addr_start, unsigned int addr_end) { unsigned int i, imax = 0; @@ -233,9 +233,9 @@ void get_trained_CDD(u32 fsp) if (i == 0) { cdd_cha[0] = (tmp >> 8) & 0xff; } else if (i == 6) { - cdd_cha[11]=tmp & 0xff; + cdd_cha[11] = tmp & 0xff; } else { - cdd_chb[ i * 2 - 1] = tmp & 0xff; + cdd_chb[i * 2 - 1] = tmp & 0xff; cdd_chb[i * 2] = (tmp >> 8) & 0xff; } } @@ -254,7 +254,8 @@ void get_trained_CDD(u32 fsp) g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max; } else { unsigned int ddr4_cdd[64]; - for( i = 0; i < 29; i++) { + + for (i = 0; i < 29; i++) { tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54012 + i) * 4); ddr4_cdd[i * 2] = tmp & 0xff; ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff; @@ -269,18 +270,18 @@ void get_trained_CDD(u32 fsp) void update_umctl2_rank_space_setting(unsigned int pstat_num) { - unsigned int i,ddr_type; + unsigned int i, ddr_type; unsigned int addr_slot, rdata, tmp, tmp_t; - unsigned int ddrc_w2r,ddrc_r2w,ddrc_wr_gap,ddrc_rd_gap; + unsigned int ddrc_w2r, ddrc_r2w, ddrc_wr_gap, ddrc_rd_gap; ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f; for (i = 0; i < pstat_num; i++) { addr_slot = i ? (i + 1) * 0x1000 : 0; if (ddr_type == 0x20) { /* update r2w:[13:8], w2r:[5:0] */ - rdata=reg32_read(DDRC_DRAMTMG2(0) + addr_slot); + rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot); ddrc_w2r = rdata & 0x3f; - if(is_imx8mp()) + if (is_imx8mp()) tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1); else tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1; @@ -297,7 +298,7 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num) reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t); } else { /* update w2r:[5:0] */ - rdata=reg32_read(DDRC_DRAMTMG9(0) + addr_slot); + rdata = reg32_read(DDRC_DRAMTMG9(0) + addr_slot); ddrc_w2r = rdata & 0x3f; if (is_imx8mp()) tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1); @@ -310,7 +311,7 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num) /* update r2w:[13:8] */ rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot); ddrc_r2w = (rdata >> 8) & 0x3f; - if(is_imx8mp()) + if (is_imx8mp()) tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1); else tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1; @@ -324,7 +325,7 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num) /* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */ rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot); ddrc_wr_gap = (rdata >> 8) & 0xf; - if(is_imx8mp()) + if (is_imx8mp()) tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1); else tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1; @@ -342,7 +343,7 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num) } } - if(is_imx8mq()) { + if (is_imx8mq()) { /* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */ rdata = reg32_read(DDRC_RANKCTL(0)); ddrc_wr_gap = (rdata >> 8) & 0xf; diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index dfd3cbb461..44e1ac54c3 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index ff5cd7efce..11e9a17f97 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -346,6 +346,16 @@ config PIC32_GPIO help Say yes here to support Microchip PIC32 GPIOs. +config OCTEON_GPIO + bool "Octeon II/III/TX/TX2 GPIO driver" + depends on DM_GPIO && DM_PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) + default y + help + Add support for the Marvell Octeon GPIO driver. This is used with + various Octeon parts such as Octeon II/III and OcteonTX/TX2. + Octeon II/III has 32 GPIOs (count defined via DT) and OcteonTX/TX2 + has 64 GPIOs (count defined via internal register). + config STM32_GPIO bool "ST STM32 GPIO driver" depends on DM_GPIO && (ARCH_STM32 || ARCH_STM32MP) diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index e769509c69..d3d0d3cacf 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o obj-$(CONFIG_HSDK_CREG_GPIO) += hsdk-creg-gpio.o obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o +obj-$(CONFIG_OCTEON_GPIO) += octeon_gpio.o obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o obj-$(CONFIG_MSM_GPIO) += msm_gpio.o obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index a16f5719ed..88b920a074 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include enum mxc_gpio_direction { MXC_GPIO_DIRECTION_IN, @@ -22,6 +24,10 @@ enum mxc_gpio_direction { #define GPIO_PER_BANK 32 struct mxc_gpio_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + /* Put this first since driver model will copy the data here */ + struct dtd_gpio_mxc dtplat; +#endif int bank_index; struct gpio_regs *regs; }; @@ -280,6 +286,12 @@ static int mxc_gpio_probe(struct udevice *dev) int banknum; char name[18], *str; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_gpio_mxc *dtplat = &plat->dtplat; + + plat->regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]); +#endif + banknum = plat->bank_index; if (IS_ENABLED(CONFIG_ARCH_IMX8)) sprintf(name, "GPIO%d_", banknum); @@ -297,14 +309,15 @@ static int mxc_gpio_probe(struct udevice *dev) static int mxc_gpio_ofdata_to_platdata(struct udevice *dev) { - fdt_addr_t addr; struct mxc_gpio_plat *plat = dev_get_platdata(dev); + if (!CONFIG_IS_ENABLED(OF_PLATDATA)) { + fdt_addr_t addr; + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; - addr = dev_read_addr(dev); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - - plat->regs = (struct gpio_regs *)addr; + plat->regs = (struct gpio_regs *)addr; + } plat->bank_index = dev->req_seq; return 0; @@ -332,6 +345,8 @@ U_BOOT_DRIVER(gpio_mxc) = { .bind = mxc_gpio_bind, }; +U_BOOT_DRIVER_ALIAS(gpio_mxc, fsl_imx6q_gpio) + #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct mxc_gpio_plat mxc_plat[] = { { 0, (struct gpio_regs *)GPIO1_BASE_ADDR }, diff --git a/drivers/gpio/octeon_gpio.c b/drivers/gpio/octeon_gpio.c new file mode 100644 index 0000000000..45acaadcdb --- /dev/null +++ b/drivers/gpio/octeon_gpio.c @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * (C) Copyright 2011 + * eInfochips Ltd. + * Written-by: Ajay Bhargav + * + * (C) Copyright 2010 + * Marvell Semiconductor + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Returns the bit value to write or read based on the offset */ +#define GPIO_BIT(x) BIT_ULL((x) & 0x3f) + +#define GPIO_RX_DAT 0x00 +#define GPIO_TX_SET 0x08 +#define GPIO_TX_CLR 0x10 +#define GPIO_CONST 0x90 /* OcteonTX only */ + +/* Offset to register-set for 2nd GPIOs (> 63), OcteonTX only */ +#define GPIO1_OFFSET 0x1400 + +/* GPIO_CONST register bits */ +#define GPIO_CONST_GPIOS_MASK GENMASK_ULL(7, 0) + +/* GPIO_BIT_CFG register bits */ +#define GPIO_BIT_CFG_TX_OE BIT_ULL(0) +#define GPIO_BIT_CFG_PIN_XOR BIT_ULL(1) +#define GPIO_BIT_CFG_INT_EN BIT_ULL(2) +#define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK_ULL(26, 16) + +enum { + PROBE_PCI = 0, /* PCI based probing */ + PROBE_DT, /* DT based probing */ +}; + +struct octeon_gpio_data { + int probe; + u32 reg_offs; + u32 gpio_bit_cfg_offs; +}; + +struct octeon_gpio { + void __iomem *base; + const struct octeon_gpio_data *data; +}; + +/* Returns the offset to the output register based on the offset and value */ +static u32 gpio_tx_reg(int offset, int value) +{ + u32 ret; + + ret = value ? GPIO_TX_SET : GPIO_TX_CLR; + if (offset > 63) + ret += GPIO1_OFFSET; + + return ret; +} + +/* Returns the offset to the input data register based on the offset */ +static u32 gpio_rx_dat_reg(int offset) +{ + u32 ret; + + ret = GPIO_RX_DAT; + if (offset > 63) + ret += GPIO1_OFFSET; + + return ret; +} + +static int octeon_gpio_dir_input(struct udevice *dev, unsigned int offset) +{ + struct octeon_gpio *gpio = dev_get_priv(dev); + + debug("%s(%s, %u)\n", __func__, dev->name, offset); + clrbits_64(gpio->base + gpio->data->gpio_bit_cfg_offs + 8 * offset, + GPIO_BIT_CFG_TX_OE | GPIO_BIT_CFG_PIN_XOR | + GPIO_BIT_CFG_INT_EN | GPIO_BIT_CFG_PIN_SEL_MASK); + + return 0; +} + +static int octeon_gpio_dir_output(struct udevice *dev, unsigned int offset, + int value) +{ + struct octeon_gpio *gpio = dev_get_priv(dev); + + debug("%s(%s, %u, %d)\n", __func__, dev->name, offset, value); + writeq(GPIO_BIT(offset), gpio->base + gpio->data->reg_offs + + gpio_tx_reg(offset, value)); + + clrsetbits_64(gpio->base + gpio->data->gpio_bit_cfg_offs + 8 * offset, + GPIO_BIT_CFG_PIN_SEL_MASK | GPIO_BIT_CFG_INT_EN, + GPIO_BIT_CFG_TX_OE); + + return 0; +} + +static int octeon_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct octeon_gpio *gpio = dev_get_priv(dev); + u64 reg = readq(gpio->base + gpio->data->reg_offs + + gpio_rx_dat_reg(offset)); + + debug("%s(%s, %u): value: %d\n", __func__, dev->name, offset, + !!(reg & GPIO_BIT(offset))); + + return !!(reg & GPIO_BIT(offset)); +} + +static int octeon_gpio_set_value(struct udevice *dev, + unsigned int offset, int value) +{ + struct octeon_gpio *gpio = dev_get_priv(dev); + + debug("%s(%s, %u, %d)\n", __func__, dev->name, offset, value); + writeq(GPIO_BIT(offset), gpio->base + gpio->data->reg_offs + + gpio_tx_reg(offset, value)); + + return 0; +} + +static int octeon_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct octeon_gpio *gpio = dev_get_priv(dev); + u64 val = readq(gpio->base + gpio->data->gpio_bit_cfg_offs + + 8 * offset); + int pin_sel; + + debug("%s(%s, %u): GPIO_BIT_CFG: 0x%llx\n", __func__, dev->name, + offset, val); + pin_sel = FIELD_GET(GPIO_BIT_CFG_PIN_SEL_MASK, val); + if (pin_sel) + return GPIOF_FUNC; + else if (val & GPIO_BIT_CFG_TX_OE) + return GPIOF_OUTPUT; + else + return GPIOF_INPUT; +} + +static int octeon_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct ofnode_phandle_args *args) +{ + if (args->args_count < 1) + return -EINVAL; + + desc->offset = args->args[0]; + desc->flags = 0; + if (args->args_count > 1) { + if (args->args[1] & GPIO_ACTIVE_LOW) + desc->flags |= GPIOD_ACTIVE_LOW; + /* In the future add tri-state flag support */ + } + return 0; +} + +static const struct dm_gpio_ops octeon_gpio_ops = { + .direction_input = octeon_gpio_dir_input, + .direction_output = octeon_gpio_dir_output, + .get_value = octeon_gpio_get_value, + .set_value = octeon_gpio_set_value, + .get_function = octeon_gpio_get_function, + .xlate = octeon_gpio_xlate, +}; + +static int octeon_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct octeon_gpio *priv = dev_get_priv(dev); + char *end; + + priv->data = (const struct octeon_gpio_data *)dev_get_driver_data(dev); + + if (priv->data->probe == PROBE_PCI) { + priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); + uc_priv->gpio_count = readq(priv->base + + priv->data->reg_offs + GPIO_CONST) & + GPIO_CONST_GPIOS_MASK; + } else { + priv->base = dev_remap_addr(dev); + uc_priv->gpio_count = ofnode_read_u32_default(dev->node, + "nr-gpios", 32); + } + + if (!priv->base) { + debug("%s(%s): Could not get base address\n", + __func__, dev->name); + return -ENODEV; + } + + uc_priv->bank_name = strdup(dev->name); + end = strchr(uc_priv->bank_name, '@'); + end[0] = 'A' + dev->seq; + end[1] = '\0'; + + debug("%s(%s): base address: %p, pin count: %d\n", + __func__, dev->name, priv->base, uc_priv->gpio_count); + + return 0; +} + +static const struct octeon_gpio_data gpio_octeon_data = { + .probe = PROBE_DT, + .reg_offs = 0x80, + .gpio_bit_cfg_offs = 0x100, +}; + +static const struct octeon_gpio_data gpio_octeontx_data = { + .probe = PROBE_PCI, + .reg_offs = 0x00, + .gpio_bit_cfg_offs = 0x400, +}; + +static const struct udevice_id octeon_gpio_ids[] = { + { .compatible = "cavium,thunder-8890-gpio", + .data = (ulong)&gpio_octeontx_data }, + { .compatible = "cavium,octeon-7890-gpio", + .data = (ulong)&gpio_octeon_data }, + { } +}; + +U_BOOT_DRIVER(octeon_gpio) = { + .name = "octeon_gpio", + .id = UCLASS_GPIO, + .of_match = of_match_ptr(octeon_gpio_ids), + .probe = octeon_gpio_probe, + .priv_auto_alloc_size = sizeof(struct octeon_gpio), + .ops = &octeon_gpio_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 644f4651fb..788677984b 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -33,6 +33,9 @@ #include #include #include +#include +#include +#include #if !CONFIG_IS_ENABLED(BLK) #include "mmc_private.h" @@ -102,6 +105,11 @@ struct fsl_esdhc { }; struct fsl_esdhc_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + /* Put this first since driver model will copy the data here */ + struct dtd_fsl_esdhc dtplat; +#endif + struct mmc_config cfg; struct mmc mmc; }; @@ -1378,25 +1386,19 @@ __weak void init_clk_usdhc(u32 index) { } -static int fsl_esdhc_probe(struct udevice *dev) +static int fsl_esdhc_ofdata_to_platdata(struct udevice *dev) { - struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); - struct fsl_esdhc_plat *plat = dev_get_platdata(dev); +#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct fsl_esdhc_priv *priv = dev_get_priv(dev); - const void *fdt = gd->fdt_blob; - int node = dev_of_offset(dev); - struct esdhc_soc_data *data = - (struct esdhc_soc_data *)dev_get_driver_data(dev); #if CONFIG_IS_ENABLED(DM_REGULATOR) struct udevice *vqmmc_dev; + int ret; #endif + const void *fdt = gd->fdt_blob; + int node = dev_of_offset(dev); + fdt_addr_t addr; unsigned int val; - struct mmc *mmc; -#if !CONFIG_IS_ENABLED(BLK) - struct blk_desc *bdesc; -#endif - int ret; addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) @@ -1404,8 +1406,6 @@ static int fsl_esdhc_probe(struct udevice *dev) priv->esdhc_regs = (struct fsl_esdhc *)addr; priv->dev = dev; priv->mode = -1; - if (data) - priv->flags = data->flags; val = dev_read_u32_default(dev, "bus-width", -1); if (val == 8) @@ -1469,6 +1469,63 @@ static int fsl_esdhc_probe(struct udevice *dev) priv->vs18_enable = 1; } #endif +#endif + return 0; +} + +static int fsl_esdhc_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct fsl_esdhc_plat *plat = dev_get_platdata(dev); + struct fsl_esdhc_priv *priv = dev_get_priv(dev); + struct esdhc_soc_data *data = + (struct esdhc_soc_data *)dev_get_driver_data(dev); + struct mmc *mmc; +#if !CONFIG_IS_ENABLED(BLK) + struct blk_desc *bdesc; +#endif + int ret; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_fsl_esdhc *dtplat = &plat->dtplat; + unsigned int val; + + priv->esdhc_regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]); + val = plat->dtplat.bus_width; + if (val == 8) + priv->bus_width = 8; + else if (val == 4) + priv->bus_width = 4; + else + priv->bus_width = 1; + + if (dtplat->non_removable) + priv->non_removable = 1; + else + priv->non_removable = 0; + + if (CONFIG_IS_ENABLED(DM_GPIO) && !priv->non_removable) { + struct udevice *gpiodev; + struct driver_info *info; + + info = (struct driver_info *)dtplat->cd_gpios->node; + + ret = device_get_by_driver_info(info, &gpiodev); + + if (ret) + return ret; + + ret = gpio_dev_request_index(gpiodev, gpiodev->name, "cd-gpios", + dtplat->cd_gpios->arg[0], GPIOD_IS_IN, + dtplat->cd_gpios->arg[1], &priv->cd_gpio); + + if (ret) + return ret; + } +#endif + + if (data) + priv->flags = data->flags; /* * TODO: @@ -1520,9 +1577,11 @@ static int fsl_esdhc_probe(struct udevice *dev) return ret; } +#if !CONFIG_IS_ENABLED(OF_PLATDATA) ret = mmc_of_parse(dev, &plat->cfg); if (ret) return ret; +#endif mmc = &plat->mmc; mmc->cfg = &plat->cfg; @@ -1644,9 +1703,10 @@ static int fsl_esdhc_bind(struct udevice *dev) #endif U_BOOT_DRIVER(fsl_esdhc) = { - .name = "fsl-esdhc-mmc", + .name = "fsl_esdhc", .id = UCLASS_MMC, .of_match = fsl_esdhc_ids, + .ofdata_to_platdata = fsl_esdhc_ofdata_to_platdata, .ops = &fsl_esdhc_ops, #if CONFIG_IS_ENABLED(BLK) .bind = fsl_esdhc_bind, @@ -1655,4 +1715,6 @@ U_BOOT_DRIVER(fsl_esdhc) = { .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat), .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), }; + +U_BOOT_DRIVER_ALIAS(fsl_esdhc, fsl_imx6q_usdhc) #endif diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index f4eb655f6e..ff871f8252 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c b/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c index c58679834e..a6acf556bc 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ #include +#include #include #include #include "brcmnand_compat.h" diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.h b/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.h index 6f9bec7085..52711d4978 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.h +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.h @@ -3,8 +3,8 @@ #ifndef __BRCMNAND_COMPAT_H #define __BRCMNAND_COMPAT_H -#include -#include +struct clk; +struct udevice; char *devm_kasprintf(struct udevice *dev, gfp_t gfp, const char *fmt, ...); diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 952fd1e45a..99cc418552 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -8,7 +8,7 @@ spi-nor-y := sf_probe.o spi-nor-ids.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o -ifeq ($(CONFIG_SPL_SPI_FLASH_TINY),y) +ifeq ($(CONFIG_$(SPL_TPL_)SPI_FLASH_TINY),y) spi-nor-y += spi-nor-tiny.o else spi-nor-y += spi-nor-core.o diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 475f6c31db..b959e3453a 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -119,7 +119,7 @@ static int spi_flash_std_erase(struct udevice *dev, u32 offset, size_t len) struct erase_info instr; if (offset % mtd->erasesize || len % mtd->erasesize) { - printf("SF: Erase offset/length not multiple of erase size\n"); + debug("SF: Erase offset/length not multiple of erase size\n"); return -EINVAL; } diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index fdcd830ce4..0113e70037 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2470,7 +2470,7 @@ static int spi_nor_init(struct spi_nor *nor) * designer) that this is bad. */ if (nor->flags & SNOR_F_BROKEN_RESET) - printf("enabling reset hack; may not recover from unexpected reboots\n"); + debug("enabling reset hack; may not recover from unexpected reboots\n"); set_4byte(nor, nor->info, 1); } diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c index 9f676c649d..fa26ea33c8 100644 --- a/drivers/mtd/spi/spi-nor-tiny.c +++ b/drivers/mtd/spi/spi-nor-tiny.c @@ -377,7 +377,7 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) } dev_dbg(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", id[0], id[1], id[2]); - return ERR_PTR(-ENODEV); + return ERR_PTR(-EMEDIUMTYPE); } static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, @@ -733,7 +733,7 @@ int spi_nor_scan(struct spi_nor *nor) info = spi_nor_read_id(nor); if (IS_ERR_OR_NULL(info)) - return -ENOENT; + return PTR_ERR(info); /* Parse the Serial Flash Discoverable Parameters table. */ ret = spi_nor_init_params(nor, info, ¶ms); if (ret) diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 559560860b..ad5ac6618f 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 593798e3e3..0124e8e051 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -8,7 +8,7 @@ #ifndef _PCIE_LAYERSCAPE_H_ #define _PCIE_LAYERSCAPE_H_ #include -#include + #include #ifndef CONFIG_SYS_PCI_MEMORY_BUS diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index 94de4edaf4..8315b0b590 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/pci/pcie_layerscape_gen4.h b/drivers/pci/pcie_layerscape_gen4.h index d298a2b810..483eb538b5 100644 --- a/drivers/pci/pcie_layerscape_gen4.h +++ b/drivers/pci/pcie_layerscape_gen4.h @@ -9,7 +9,6 @@ #ifndef _PCIE_LAYERSCAPE_GEN4_H_ #define _PCIE_LAYERSCAPE_GEN4_H_ #include -#include #include #ifndef CONFIG_SYS_PCI_MEMORY_SIZE diff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c b/drivers/pci/pcie_layerscape_gen4_fixup.c index 375ce45839..148b5d17ed 100644 --- a/drivers/pci/pcie_layerscape_gen4_fixup.c +++ b/drivers/pci/pcie_layerscape_gen4_fixup.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c index aafa3057ad..84004e5921 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx6.c +++ b/drivers/pinctrl/nxp/pinctrl-imx6.c @@ -41,8 +41,8 @@ static const struct udevice_id imx6_pinctrl_match[] = { { /* sentinel */ } }; -U_BOOT_DRIVER(imx6_pinctrl) = { - .name = "imx6-pinctrl", +U_BOOT_DRIVER(fsl_imx6q_iomuxc) = { + .name = "fsl_imx6q_iomuxc", .id = UCLASS_PINCTRL, .of_match = of_match_ptr(imx6_pinctrl_match), .probe = imx6_pinctrl_probe, @@ -51,3 +51,5 @@ U_BOOT_DRIVER(imx6_pinctrl) = { .ops = &imx_pinctrl_ops, .flags = DM_FLAG_PRE_RELOC, }; + +U_BOOT_DRIVER_ALIAS(fsl_imx6q_iomuxc, fsl_imx6dl_iomuxc) diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c index b5f7aec353..2fa6c7e6b2 100644 --- a/drivers/power/regulator/fixed.c +++ b/drivers/power/regulator/fixed.c @@ -5,7 +5,6 @@ * Przemyslaw Marczak */ -#include "regulator_common.h" #include #include #include @@ -13,6 +12,8 @@ #include #include +#include "regulator_common.h" + static int fixed_regulator_ofdata_to_platdata(struct udevice *dev) { struct dm_regulator_uclass_platdata *uc_pdata; diff --git a/drivers/power/regulator/gpio-regulator.c b/drivers/power/regulator/gpio-regulator.c index cf3fbae79d..947f812d09 100644 --- a/drivers/power/regulator/gpio-regulator.c +++ b/drivers/power/regulator/gpio-regulator.c @@ -4,7 +4,6 @@ * Keerthy */ -#include "regulator_common.h" #include #include #include @@ -15,6 +14,8 @@ #include #include +#include "regulator_common.h" + #define GPIO_REGULATOR_MAX_STATES 2 DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/power/regulator/regulator_common.c b/drivers/power/regulator/regulator_common.c index 4cfcc31298..13906b9c6e 100644 --- a/drivers/power/regulator/regulator_common.c +++ b/drivers/power/regulator/regulator_common.c @@ -4,12 +4,14 @@ * Sven Schwermer */ -#include "regulator_common.h" #include +#include #include #include #include +#include "regulator_common.h" + int regulator_common_ofdata_to_platdata(struct udevice *dev, struct regulator_common_platdata *dev_pdata, const char *enable_gpio_name) { diff --git a/drivers/power/regulator/regulator_common.h b/drivers/power/regulator/regulator_common.h index 18a525880a..bf80439c78 100644 --- a/drivers/power/regulator/regulator_common.h +++ b/drivers/power/regulator/regulator_common.h @@ -7,9 +7,7 @@ #ifndef _REGULATOR_COMMON_H #define _REGULATOR_COMMON_H -#include #include -#include struct regulator_common_platdata { struct gpio_desc gpio; /* GPIO for regulator enable control */ diff --git a/drivers/ram/k3-am654-ddrss.c b/drivers/ram/k3-am654-ddrss.c index 8bbd8cfa83..21e5a65529 100644 --- a/drivers/ram/k3-am654-ddrss.c +++ b/drivers/ram/k3-am654-ddrss.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 6d53561223..253902ff57 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -148,6 +148,15 @@ config RESET_IMX7 help Support for reset controller on i.MX7/8 SoCs. +config RESET_SIFIVE + bool "Reset Driver for SiFive SoC's" + depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_FU540 + default y + help + PRCI module within SiFive SoC's provides mechanism to reset + different hw blocks like DDR, gemgxl. With this driver we leverage + U-Boot's reset framework to reset these hardware blocks. + config RESET_SYSCON bool "Enable generic syscon reset driver support" depends on DM_RESET diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 8e0124b8de..3c7f066ae3 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -23,5 +23,6 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o +obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o diff --git a/drivers/reset/reset-sifive.c b/drivers/reset/reset-sifive.c new file mode 100644 index 0000000000..527757f853 --- /dev/null +++ b/drivers/reset/reset-sifive.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Sifive, Inc. + * Author: Sagar Kadam + */ + +#include +#include +#include +#include +#include +#include +#include + +#define PRCI_RESETREG_OFFSET 0x28 + +struct sifive_reset_priv { + void *base; + /* number of reset signals */ + int nr_reset; +}; + +static int sifive_rst_trigger(struct reset_ctl *rst, bool level) +{ + struct sifive_reset_priv *priv = dev_get_priv(rst->dev); + int id = rst->id; + int regval = readl(priv->base + PRCI_RESETREG_OFFSET); + + /* Derive bitposition from rst id */ + if (level) + /* Reset deassert */ + regval |= BIT(id); + else + /* Reset assert */ + regval &= ~BIT(id); + + writel(regval, priv->base + PRCI_RESETREG_OFFSET); + + return 0; +} + +static int sifive_reset_assert(struct reset_ctl *rst) +{ + return sifive_rst_trigger(rst, false); +} + +static int sifive_reset_deassert(struct reset_ctl *rst) +{ + return sifive_rst_trigger(rst, true); +} + +static int sifive_reset_request(struct reset_ctl *rst) +{ + struct sifive_reset_priv *priv = dev_get_priv(rst->dev); + + debug("%s(rst=%p) (dev=%p, id=%lu) (nr_reset=%d)\n", __func__, + rst, rst->dev, rst->id, priv->nr_reset); + + if (rst->id > priv->nr_reset) + return -EINVAL; + + return 0; +} + +static int sifive_reset_free(struct reset_ctl *rst) +{ + struct sifive_reset_priv *priv = dev_get_priv(rst->dev); + + debug("%s(rst=%p) (dev=%p, id=%lu) (nr_reset=%d)\n", __func__, + rst, rst->dev, rst->id, priv->nr_reset); + + return 0; +} + +static int sifive_reset_probe(struct udevice *dev) +{ + struct sifive_reset_priv *priv = dev_get_priv(dev); + + priv->base = dev_remap_addr(dev); + if (!priv->base) + return -ENOMEM; + + return 0; +} + +int sifive_reset_bind(struct udevice *dev, ulong count) +{ + struct udevice *rst_dev; + struct sifive_reset_priv *priv; + int ret; + + ret = device_bind_driver_to_node(dev, "sifive-reset", "reset", + dev_ofnode(dev), &rst_dev); + if (ret) { + dev_err(dev, "failed to bind sifive_reset driver (ret=%d)\n", ret); + return ret; + } + priv = malloc(sizeof(struct sifive_reset_priv)); + priv->nr_reset = count; + rst_dev->priv = priv; + + return 0; +} + +const struct reset_ops sifive_reset_ops = { + .request = sifive_reset_request, + .rfree = sifive_reset_free, + .rst_assert = sifive_reset_assert, + .rst_deassert = sifive_reset_deassert, +}; + +U_BOOT_DRIVER(sifive_reset) = { + .name = "sifive-reset", + .id = UCLASS_RESET, + .ops = &sifive_reset_ops, + .probe = sifive_reset_probe, + .priv_auto_alloc_size = sizeof(struct sifive_reset_priv), +}; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 30d808d7bb..3fc2d0674a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -240,6 +240,14 @@ config NXP_FSPI Enable the NXP FlexSPI (FSPI) driver. This driver can be used to access the SPI NOR flash on platforms embedding this NXP IP core. +config OCTEON_SPI + bool "Octeon SPI driver" + depends on DM_PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) + help + Enable the Octeon SPI driver. This driver can be used to + access the SPI NOR flash on Octeon II/III and OcteonTX/TX2 + SoC platforms. + config OMAP3_SPI bool "McSPI driver for OMAP" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 4e7461771f..b5c9ff1af8 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o +obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o obj-$(CONFIG_PIC32_SPI) += pic32_spi.o obj-$(CONFIG_PL022_SPI) += pl022_spi.o diff --git a/drivers/spi/mscc_bb_spi.c b/drivers/spi/mscc_bb_spi.c index 0454410ee9..e77447b655 100644 --- a/drivers/spi/mscc_bb_spi.c +++ b/drivers/spi/mscc_bb_spi.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/spi/octeon_spi.c b/drivers/spi/octeon_spi.c new file mode 100644 index 0000000000..83fe6330a1 --- /dev/null +++ b/drivers/spi/octeon_spi.c @@ -0,0 +1,613 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define OCTEON_SPI_MAX_BYTES 9 +#define OCTEON_SPI_MAX_CLOCK_HZ 50000000 + +#define OCTEON_SPI_NUM_CS 4 + +#define OCTEON_SPI_CS_VALID(cs) ((cs) < OCTEON_SPI_NUM_CS) + +#define MPI_CFG 0x0000 +#define MPI_STS 0x0008 +#define MPI_TX 0x0010 +#define MPI_XMIT 0x0018 +#define MPI_WIDE_DAT 0x0040 +#define MPI_IO_CTL 0x0048 +#define MPI_DAT(X) (0x0080 + ((X) << 3)) +#define MPI_WIDE_BUF(X) (0x0800 + ((X) << 3)) +#define MPI_CYA_CFG 0x1000 +#define MPI_CLKEN 0x1080 + +#define MPI_CFG_ENABLE BIT_ULL(0) +#define MPI_CFG_IDLELO BIT_ULL(1) +#define MPI_CFG_CLK_CONT BIT_ULL(2) +#define MPI_CFG_WIREOR BIT_ULL(3) +#define MPI_CFG_LSBFIRST BIT_ULL(4) +#define MPI_CFG_CS_STICKY BIT_ULL(5) +#define MPI_CFG_CSHI BIT_ULL(7) +#define MPI_CFG_IDLECLKS GENMASK_ULL(9, 8) +#define MPI_CFG_TRITX BIT_ULL(10) +#define MPI_CFG_CSLATE BIT_ULL(11) +#define MPI_CFG_CSENA0 BIT_ULL(12) +#define MPI_CFG_CSENA1 BIT_ULL(13) +#define MPI_CFG_CSENA2 BIT_ULL(14) +#define MPI_CFG_CSENA3 BIT_ULL(15) +#define MPI_CFG_CLKDIV GENMASK_ULL(28, 16) +#define MPI_CFG_LEGACY_DIS BIT_ULL(31) +#define MPI_CFG_IOMODE GENMASK_ULL(35, 34) +#define MPI_CFG_TB100_EN BIT_ULL(49) + +#define MPI_DAT_DATA GENMASK_ULL(7, 0) + +#define MPI_STS_BUSY BIT_ULL(0) +#define MPI_STS_MPI_INTR BIT_ULL(1) +#define MPI_STS_RXNUM GENMASK_ULL(12, 8) + +#define MPI_TX_TOTNUM GENMASK_ULL(4, 0) +#define MPI_TX_TXNUM GENMASK_ULL(12, 8) +#define MPI_TX_LEAVECS BIT_ULL(16) +#define MPI_TX_CSID GENMASK_ULL(21, 20) + +#define MPI_XMIT_TOTNUM GENMASK_ULL(10, 0) +#define MPI_XMIT_TXNUM GENMASK_ULL(30, 20) +#define MPI_XMIT_BUF_SEL BIT_ULL(59) +#define MPI_XMIT_LEAVECS BIT_ULL(60) +#define MPI_XMIT_CSID GENMASK_ULL(62, 61) + +/* Used on Octeon TX2 */ +void board_acquire_flash_arb(bool acquire); + +/* Local driver data structure */ +struct octeon_spi { + void __iomem *base; /* Register base address */ + struct clk clk; + u32 clkdiv; /* Clock divisor for device speed */ +}; + +static u64 octeon_spi_set_mpicfg(struct udevice *dev) +{ + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + struct udevice *bus = dev_get_parent(dev); + struct octeon_spi *priv = dev_get_priv(bus); + u64 mpi_cfg; + uint max_speed = slave->max_hz; + bool cpha, cpol; + + if (!max_speed) + max_speed = 12500000; + if (max_speed > OCTEON_SPI_MAX_CLOCK_HZ) + max_speed = OCTEON_SPI_MAX_CLOCK_HZ; + + debug("\n slave params %d %d %d\n", slave->cs, + slave->max_hz, slave->mode); + cpha = !!(slave->mode & SPI_CPHA); + cpol = !!(slave->mode & SPI_CPOL); + + mpi_cfg = FIELD_PREP(MPI_CFG_CLKDIV, priv->clkdiv & 0x1fff) | + FIELD_PREP(MPI_CFG_CSHI, !!(slave->mode & SPI_CS_HIGH)) | + FIELD_PREP(MPI_CFG_LSBFIRST, !!(slave->mode & SPI_LSB_FIRST)) | + FIELD_PREP(MPI_CFG_WIREOR, !!(slave->mode & SPI_3WIRE)) | + FIELD_PREP(MPI_CFG_IDLELO, cpha != cpol) | + FIELD_PREP(MPI_CFG_CSLATE, cpha) | + MPI_CFG_CSENA0 | MPI_CFG_CSENA1 | + MPI_CFG_CSENA2 | MPI_CFG_CSENA1 | + MPI_CFG_ENABLE; + + debug("\n mpi_cfg %llx\n", mpi_cfg); + return mpi_cfg; +} + +/** + * Wait until the SPI bus is ready + * + * @param dev SPI device to wait for + */ +static void octeon_spi_wait_ready(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct octeon_spi *priv = dev_get_priv(bus); + void *base = priv->base; + u64 mpi_sts; + + do { + mpi_sts = readq(base + MPI_STS); + WATCHDOG_RESET(); + } while (mpi_sts & MPI_STS_BUSY); + + debug("%s(%s)\n", __func__, dev->name); +} + +/** + * Claim the bus for a slave device + * + * @param dev SPI bus + * + * @return 0 for success, -EINVAL if chip select is invalid + */ +static int octeon_spi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct octeon_spi *priv = dev_get_priv(bus); + void *base = priv->base; + u64 mpi_cfg; + + debug("\n\n%s(%s)\n", __func__, dev->name); + if (!OCTEON_SPI_CS_VALID(spi_chip_select(dev))) + return -EINVAL; + + if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) + board_acquire_flash_arb(true); + + mpi_cfg = readq(base + MPI_CFG); + mpi_cfg &= ~MPI_CFG_TRITX; + mpi_cfg |= MPI_CFG_ENABLE; + writeq(mpi_cfg, base + MPI_CFG); + mpi_cfg = readq(base + MPI_CFG); + udelay(5); /** Wait for bus to settle */ + + return 0; +} + +/** + * Release the bus to a slave device + * + * @param dev SPI bus + * + * @return 0 for success, -EINVAL if chip select is invalid + */ +static int octeon_spi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct octeon_spi *priv = dev_get_priv(bus); + void *base = priv->base; + u64 mpi_cfg; + + debug("%s(%s)\n\n", __func__, dev->name); + if (!OCTEON_SPI_CS_VALID(spi_chip_select(dev))) + return -EINVAL; + + if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) + board_acquire_flash_arb(false); + + mpi_cfg = readq(base + MPI_CFG); + mpi_cfg &= ~MPI_CFG_ENABLE; + writeq(mpi_cfg, base + MPI_CFG); + mpi_cfg = readq(base + MPI_CFG); + udelay(1); + + return 0; +} + +static int octeon_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev_get_parent(dev); + struct octeon_spi *priv = dev_get_priv(bus); + void *base = priv->base; + u64 mpi_tx; + u64 mpi_cfg; + u64 wide_dat = 0; + int len = bitlen / 8; + int i; + const u8 *tx_data = dout; + u8 *rx_data = din; + int cs = spi_chip_select(dev); + + if (!OCTEON_SPI_CS_VALID(cs)) + return -EINVAL; + + debug("\n %s(%s, %u, %p, %p, 0x%lx), cs: %d\n", + __func__, dev->name, bitlen, dout, din, flags, cs); + + mpi_cfg = octeon_spi_set_mpicfg(dev); + if (mpi_cfg != readq(base + MPI_CFG)) { + writeq(mpi_cfg, base + MPI_CFG); + mpi_cfg = readq(base + MPI_CFG); + udelay(10); + } + + debug("\n mpi_cfg upd %llx\n", mpi_cfg); + + /* + * Start by writing and reading 8 bytes at a time. While we can support + * up to 10, it's easier to just use 8 with the MPI_WIDE_DAT register. + */ + while (len > 8) { + if (tx_data) { + wide_dat = get_unaligned((u64 *)tx_data); + debug(" tx: %016llx \t", (unsigned long long)wide_dat); + tx_data += 8; + writeq(wide_dat, base + MPI_WIDE_DAT); + } + + mpi_tx = FIELD_PREP(MPI_TX_CSID, cs) | + FIELD_PREP(MPI_TX_LEAVECS, 1) | + FIELD_PREP(MPI_TX_TXNUM, tx_data ? 8 : 0) | + FIELD_PREP(MPI_TX_TOTNUM, 8); + writeq(mpi_tx, base + MPI_TX); + + octeon_spi_wait_ready(dev); + + debug("\n "); + + if (rx_data) { + wide_dat = readq(base + MPI_WIDE_DAT); + debug(" rx: %016llx\t", (unsigned long long)wide_dat); + *(u64 *)rx_data = wide_dat; + rx_data += 8; + } + len -= 8; + } + + debug("\n "); + + /* Write and read the rest of the data */ + if (tx_data) { + for (i = 0; i < len; i++) { + debug(" tx: %02x\n", *tx_data); + writeq(*tx_data++, base + MPI_DAT(i)); + } + } + + mpi_tx = FIELD_PREP(MPI_TX_CSID, cs) | + FIELD_PREP(MPI_TX_LEAVECS, !(flags & SPI_XFER_END)) | + FIELD_PREP(MPI_TX_TXNUM, tx_data ? len : 0) | + FIELD_PREP(MPI_TX_TOTNUM, len); + writeq(mpi_tx, base + MPI_TX); + + octeon_spi_wait_ready(dev); + + debug("\n "); + + if (rx_data) { + for (i = 0; i < len; i++) { + *rx_data = readq(base + MPI_DAT(i)) & 0xff; + debug(" rx: %02x\n", *rx_data); + rx_data++; + } + } + + return 0; +} + +static int octeontx2_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev_get_parent(dev); + struct octeon_spi *priv = dev_get_priv(bus); + void *base = priv->base; + u64 mpi_xmit; + u64 mpi_cfg; + u64 wide_dat = 0; + int len = bitlen / 8; + int rem; + int i; + const u8 *tx_data = dout; + u8 *rx_data = din; + int cs = spi_chip_select(dev); + + if (!OCTEON_SPI_CS_VALID(cs)) + return -EINVAL; + + debug("\n %s(%s, %u, %p, %p, 0x%lx), cs: %d\n", + __func__, dev->name, bitlen, dout, din, flags, cs); + + mpi_cfg = octeon_spi_set_mpicfg(dev); + + mpi_cfg |= MPI_CFG_TRITX | MPI_CFG_LEGACY_DIS | MPI_CFG_CS_STICKY | + MPI_CFG_TB100_EN; + + mpi_cfg &= ~MPI_CFG_IOMODE; + if (flags & (SPI_TX_DUAL | SPI_RX_DUAL)) + mpi_cfg |= FIELD_PREP(MPI_CFG_IOMODE, 2); + if (flags & (SPI_TX_QUAD | SPI_RX_QUAD)) + mpi_cfg |= FIELD_PREP(MPI_CFG_IOMODE, 3); + + if (mpi_cfg != readq(base + MPI_CFG)) { + writeq(mpi_cfg, base + MPI_CFG); + mpi_cfg = readq(base + MPI_CFG); + udelay(10); + } + + debug("\n mpi_cfg upd %llx\n\n", mpi_cfg); + + /* Start by writing or reading 1024 bytes at a time. */ + while (len > 1024) { + if (tx_data) { + /* 8 bytes per iteration */ + for (i = 0; i < 128; i++) { + wide_dat = get_unaligned((u64 *)tx_data); + debug(" tx: %016llx \t", + (unsigned long long)wide_dat); + if ((i % 4) == 3) + debug("\n"); + tx_data += 8; + writeq(wide_dat, base + MPI_WIDE_BUF(i)); + } + } + + mpi_xmit = FIELD_PREP(MPI_XMIT_CSID, cs) | MPI_XMIT_LEAVECS | + FIELD_PREP(MPI_XMIT_TXNUM, tx_data ? 1024 : 0) | + FIELD_PREP(MPI_XMIT_TOTNUM, 1024); + writeq(mpi_xmit, base + MPI_XMIT); + + octeon_spi_wait_ready(dev); + + debug("\n "); + + if (rx_data) { + /* 8 bytes per iteration */ + for (i = 0; i < 128; i++) { + wide_dat = readq(base + MPI_WIDE_BUF(i)); + debug(" rx: %016llx\t", + (unsigned long long)wide_dat); + if ((i % 4) == 3) + debug("\n"); + *(u64 *)rx_data = wide_dat; + rx_data += 8; + } + } + len -= 1024; + } + + if (tx_data) { + rem = len % 8; + /* 8 bytes per iteration */ + for (i = 0; i < len / 8; i++) { + wide_dat = get_unaligned((u64 *)tx_data); + debug(" tx: %016llx \t", + (unsigned long long)wide_dat); + if ((i % 4) == 3) + debug("\n"); + tx_data += 8; + writeq(wide_dat, base + MPI_WIDE_BUF(i)); + } + if (rem) { + memcpy(&wide_dat, tx_data, rem); + debug(" rtx: %016llx\t", wide_dat); + writeq(wide_dat, base + MPI_WIDE_BUF(i)); + } + } + + mpi_xmit = FIELD_PREP(MPI_XMIT_CSID, cs) | + FIELD_PREP(MPI_XMIT_LEAVECS, !(flags & SPI_XFER_END)) | + FIELD_PREP(MPI_XMIT_TXNUM, tx_data ? len : 0) | + FIELD_PREP(MPI_XMIT_TOTNUM, len); + writeq(mpi_xmit, base + MPI_XMIT); + + octeon_spi_wait_ready(dev); + + debug("\n "); + + if (rx_data) { + rem = len % 8; + /* 8 bytes per iteration */ + for (i = 0; i < len / 8; i++) { + wide_dat = readq(base + MPI_WIDE_BUF(i)); + debug(" rx: %016llx\t", + (unsigned long long)wide_dat); + if ((i % 4) == 3) + debug("\n"); + *(u64 *)rx_data = wide_dat; + rx_data += 8; + } + if (rem) { + wide_dat = readq(base + MPI_WIDE_BUF(i)); + debug(" rrx: %016llx\t", + (unsigned long long)wide_dat); + memcpy(rx_data, &wide_dat, rem); + rx_data += rem; + } + } + + return 0; +} + +static bool octeon_spi_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + /* For now, support only below combinations + * 1-1-1 + * 1-1-2 1-2-2 + * 1-1-4 1-4-4 + */ + if (op->cmd.buswidth != 1) + return false; + return true; +} + +static int octeon_spi_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + unsigned long flags = SPI_XFER_BEGIN; + const void *tx; + void *rx; + u8 opcode, *buf; + u8 *addr; + int i, temp, ret; + + if (op->cmd.buswidth != 1) + return -ENOTSUPP; + + /* Send CMD */ + i = 0; + opcode = op->cmd.opcode; + + if (!op->data.nbytes && !op->addr.nbytes && !op->dummy.nbytes) + flags |= SPI_XFER_END; + + ret = octeontx2_spi_xfer(slave->dev, 8, (void *)&opcode, NULL, flags); + if (ret < 0) + return ret; + + /* Send Address and dummy */ + if (op->addr.nbytes) { + /* Alloc buffer for address+dummy */ + buf = (u8 *)calloc(1, op->addr.nbytes + op->dummy.nbytes); + if (!buf) { + printf("%s Out of memory\n", __func__); + return -ENOMEM; + } + addr = (u8 *)&op->addr.val; + for (temp = 0; temp < op->addr.nbytes; temp++) + buf[i++] = *(u8 *)(addr + op->addr.nbytes - 1 - temp); + for (temp = 0; temp < op->dummy.nbytes; temp++) + buf[i++] = 0xff; + if (op->addr.buswidth == 2) + flags |= SPI_RX_DUAL; + if (op->addr.buswidth == 4) + flags |= SPI_RX_QUAD; + + if (!op->data.nbytes) + flags |= SPI_XFER_END; + ret = octeontx2_spi_xfer(slave->dev, i * 8, (void *)buf, NULL, + flags); + free(buf); + if (ret < 0) + return ret; + } + if (!op->data.nbytes) + return 0; + + /* Send/Receive Data */ + flags |= SPI_XFER_END; + if (op->data.buswidth == 2) + flags |= SPI_RX_DUAL; + if (op->data.buswidth == 4) + flags |= SPI_RX_QUAD; + + rx = (op->data.dir == SPI_MEM_DATA_IN) ? op->data.buf.in : NULL; + tx = (op->data.dir == SPI_MEM_DATA_OUT) ? op->data.buf.out : NULL; + + ret = octeontx2_spi_xfer(slave->dev, (op->data.nbytes * 8), tx, rx, + flags); + return ret; +} + +static const struct spi_controller_mem_ops octeontx2_spi_mem_ops = { + .supports_op = octeon_spi_supports_op, + .exec_op = octeon_spi_exec_op, +}; + +/** + * Set the speed of the SPI bus + * + * @param bus bus to set + * @param max_hz maximum speed supported + */ +static int octeon_spi_set_speed(struct udevice *bus, uint max_hz) +{ + struct octeon_spi *priv = dev_get_priv(bus); + ulong clk_rate; + u32 calc_hz; + + if (max_hz > OCTEON_SPI_MAX_CLOCK_HZ) + max_hz = OCTEON_SPI_MAX_CLOCK_HZ; + + clk_rate = clk_get_rate(&priv->clk); + if (IS_ERR_VALUE(clk_rate)) + return -EINVAL; + + debug("%s(%s, %u, %lu)\n", __func__, bus->name, max_hz, clk_rate); + + priv->clkdiv = clk_rate / (2 * max_hz); + while (1) { + calc_hz = clk_rate / (2 * priv->clkdiv); + if (calc_hz <= max_hz) + break; + priv->clkdiv += 1; + } + + if (priv->clkdiv > 8191) + return -EINVAL; + + debug("%s: clkdiv=%d\n", __func__, priv->clkdiv); + + return 0; +} + +static int octeon_spi_set_mode(struct udevice *bus, uint mode) +{ + /* We don't set it here */ + return 0; +} + +static struct dm_spi_ops octeon_spi_ops = { + .claim_bus = octeon_spi_claim_bus, + .release_bus = octeon_spi_release_bus, + .set_speed = octeon_spi_set_speed, + .set_mode = octeon_spi_set_mode, + .xfer = octeon_spi_xfer, +}; + +static int octeon_spi_probe(struct udevice *dev) +{ + struct octeon_spi *priv = dev_get_priv(dev); + int ret; + + /* Octeon TX & TX2 use PCI based probing */ + if (device_is_compatible(dev, "cavium,thunder-8190-spi")) { + pci_dev_t bdf = dm_pci_get_bdf(dev); + + debug("SPI PCI device: %x\n", bdf); + priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); + /* Add base offset */ + priv->base += 0x1000; + + /* + * Octeon TX2 needs a different xfer function and supports + * mem_ops + */ + if (device_is_compatible(dev, "cavium,thunderx-spi")) { + octeon_spi_ops.xfer = octeontx2_spi_xfer; + octeon_spi_ops.mem_ops = &octeontx2_spi_mem_ops; + } + } else { + priv->base = dev_remap_addr(dev); + } + + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret < 0) + return ret; + + ret = clk_enable(&priv->clk); + if (ret) + return ret; + + debug("SPI bus %s %d at %p\n", dev->name, dev->seq, priv->base); + + return 0; +} + +static const struct udevice_id octeon_spi_ids[] = { + /* MIPS Octeon */ + { .compatible = "cavium,octeon-3010-spi" }, + /* ARM Octeon TX / TX2 */ + { .compatible = "cavium,thunder-8190-spi" }, + { } +}; + +U_BOOT_DRIVER(octeon_spi) = { + .name = "spi_octeon", + .id = UCLASS_SPI, + .of_match = octeon_spi_ids, + .probe = octeon_spi_probe, + .priv_auto_alloc_size = sizeof(struct octeon_spi), + .ops = &octeon_spi_ops, +}; diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index d344701aeb..c095ae9505 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -13,9 +13,14 @@ #include #include "internals.h" #else -#include +#include +#include +#include +#include +#include #include #include +#include #endif #ifndef __UBOOT__ diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c index 0e0ce25abb..c7345d9042 100644 --- a/drivers/spi/spi-sifive.c +++ b/drivers/spi/spi-sifive.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index 001f0703e3..a53b941410 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -9,8 +9,10 @@ #include #include +#include #include #include +#include #include #include #include diff --git a/drivers/sysreset/sysreset-uclass.c b/drivers/sysreset/sysreset-uclass.c index 995240f0cb..3f5414ed1f 100644 --- a/drivers/sysreset/sysreset-uclass.c +++ b/drivers/sysreset/sysreset-uclass.c @@ -117,6 +117,7 @@ void reset_cpu(ulong addr) int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { printf("resetting ...\n"); + mdelay(100); sysreset_walk_halt(SYSRESET_COLD); diff --git a/drivers/ufs/cdns-platform.c b/drivers/ufs/cdns-platform.c index 1a7bb7bed8..bad1bf7de5 100644 --- a/drivers/ufs/cdns-platform.c +++ b/drivers/ufs/cdns-platform.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c index 87b4e5fc56..92b7e9fd7c 100644 --- a/drivers/ufs/ufs.c +++ b/drivers/ufs/ufs.c @@ -19,9 +19,10 @@ #include #include #include +#include +#include #include #include - #include #include "ufs.h" diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h index e0bde93776..069888fdd9 100644 --- a/drivers/ufs/ufs.h +++ b/drivers/ufs/ufs.h @@ -2,11 +2,10 @@ #ifndef __UFS_H #define __UFS_H -#include -#include - #include "unipro.h" +struct udevice; + #define UFS_CDB_SIZE 16 #define UPIU_TRANSACTION_UIC_CMD 0x1F #define UIC_CMD_SIZE (sizeof(u32) * 4) diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c index 988071a61d..8ac2f0a78a 100644 --- a/drivers/usb/musb-new/musb_uboot.c +++ b/drivers/usb/musb-new/musb_uboot.c @@ -1,5 +1,6 @@ #include #include +#include #include #include #include @@ -452,3 +453,39 @@ struct musb *musb_register(struct musb_hdrc_platform_data *plat, void *bdata, return *musbp; } + +#if CONFIG_IS_ENABLED(DM_USB) +struct usb_device *usb_dev_get_parent(struct usb_device *udev) +{ + struct udevice *parent = udev->dev->parent; + + /* + * When called from usb-uclass.c: usb_scan_device() udev->dev points + * to the parent udevice, not the actual udevice belonging to the + * udev as the device is not instantiated yet. + * + * If dev is an usb-bus, then we are called from usb_scan_device() for + * an usb-device plugged directly into the root port, return NULL. + */ + if (device_get_uclass_id(udev->dev) == UCLASS_USB) + return NULL; + + /* + * If these 2 are not the same we are being called from + * usb_scan_device() and udev itself is the parent. + */ + if (dev_get_parent_priv(udev->dev) != udev) + return udev; + + /* We are being called normally, use the parent pointer */ + if (device_get_uclass_id(parent) == UCLASS_USB_HUB) + return dev_get_parent_priv(parent); + + return NULL; +} +#else +struct usb_device *usb_dev_get_parent(struct usb_device *udev) +{ + return udev->parent; +} +#endif diff --git a/drivers/usb/musb-new/pic32.c b/drivers/usb/musb-new/pic32.c index 74a841af46..2fbe9bebf1 100644 --- a/drivers/usb/musb-new/pic32.c +++ b/drivers/usb/musb-new/pic32.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include diff --git a/drivers/usb/musb-new/usb-compat.h b/drivers/usb/musb-new/usb-compat.h index f2c18ad3a2..1c66c4fe36 100644 --- a/drivers/usb/musb-new/usb-compat.h +++ b/drivers/usb/musb-new/usb-compat.h @@ -1,9 +1,10 @@ #ifndef __USB_COMPAT_H__ #define __USB_COMPAT_H__ -#include #include "usb.h" +struct udevice; + struct usb_hcd { void *hcd_priv; }; @@ -67,40 +68,12 @@ static inline int usb_hcd_unmap_urb_for_dma(struct usb_hcd *hcd, return 0; } -#if CONFIG_IS_ENABLED(DM_USB) -static inline struct usb_device *usb_dev_get_parent(struct usb_device *udev) -{ - struct udevice *parent = udev->dev->parent; - - /* - * When called from usb-uclass.c: usb_scan_device() udev->dev points - * to the parent udevice, not the actual udevice belonging to the - * udev as the device is not instantiated yet. - * - * If dev is an usb-bus, then we are called from usb_scan_device() for - * an usb-device plugged directly into the root port, return NULL. - */ - if (device_get_uclass_id(udev->dev) == UCLASS_USB) - return NULL; - - /* - * If these 2 are not the same we are being called from - * usb_scan_device() and udev itself is the parent. - */ - if (dev_get_parent_priv(udev->dev) != udev) - return udev; - - /* We are being called normally, use the parent pointer */ - if (device_get_uclass_id(parent) == UCLASS_USB_HUB) - return dev_get_parent_priv(parent); - - return NULL; -} -#else -static inline struct usb_device *usb_dev_get_parent(struct usb_device *dev) -{ - return dev->parent; -} -#endif +/** + * usb_dev_get_parent() - Get the parent of a USB device + * + * @udev: USB struct containing information about the device + * @return associated device for which udev == dev_get_parent_priv(dev) + */ +struct usb_device *usb_dev_get_parent(struct usb_device *udev); #endif /* __USB_COMPAT_H__ */ diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c index 587d62f2d8..eb93a4f1fa 100644 --- a/drivers/video/imx/mxc_ipuv3_fb.c +++ b/drivers/video/imx/mxc_ipuv3_fb.c @@ -66,6 +66,7 @@ static void fb_videomode_to_var(struct fb_var_screeninfo *var, * Structure containing the MXC specific framebuffer information. */ struct mxcfb_info { + struct udevice *udev; int blank; ipu_channel_t ipu_ch; int ipu_di; @@ -381,13 +382,16 @@ static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) static int mxcfb_map_video_memory(struct fb_info *fbi) { + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + struct video_uc_platdata *plat = dev_get_uclass_platdata(mxc_fbi->udev); + if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length) { fbi->fix.smem_len = fbi->var.yres_virtual * fbi->fix.line_length; } fbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN); - fbi->screen_base = (char *)gd->video_bottom; + fbi->screen_base = (char *)plat->base; fbi->fix.smem_start = (unsigned long)fbi->screen_base; if (fbi->screen_base == 0) { @@ -477,8 +481,8 @@ extern struct clk *g_ipu_clk; * * @return Appropriate error code to the kernel common code */ -static int mxcfb_probe(u32 interface_pix_fmt, uint8_t disp, - struct fb_videomode const *mode) +static int mxcfb_probe(struct udevice *dev, u32 interface_pix_fmt, + uint8_t disp, struct fb_videomode const *mode) { struct fb_info *fbi; struct mxcfb_info *mxcfbi; @@ -501,6 +505,7 @@ static int mxcfb_probe(u32 interface_pix_fmt, uint8_t disp, } mxcfbi->ipu_di = disp; + mxcfbi->udev = dev; if (!ipu_clk_enabled()) clk_enable(g_ipu_clk); @@ -600,7 +605,7 @@ static int ipuv3_video_probe(struct udevice *dev) if (ret < 0) return ret; - ret = mxcfb_probe(gpixfmt, gdisp, gmode); + ret = mxcfb_probe(dev, gpixfmt, gdisp, gmode); if (ret < 0) return ret; @@ -660,8 +665,8 @@ static const struct udevice_id ipuv3_video_ids[] = { { } }; -U_BOOT_DRIVER(ipuv3_video) = { - .name = "ipuv3_video", +U_BOOT_DRIVER(fsl_imx6q_ipu) = { + .name = "fsl_imx6q_ipu", .id = UCLASS_VIDEO, .of_match = ipuv3_video_ids, .bind = ipuv3_video_bind, diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 6e8a1db26c..21eb134e7b 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -10,6 +10,8 @@ #include #include +#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) + #define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 82bd61f919..009bcdcc83 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -10,6 +10,8 @@ #include #include +#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) + #define CONFIG_SPL_MAX_SIZE (152 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index bb5dbe3c0d..1a50559b48 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -10,6 +10,8 @@ #include #include +#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) + #define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h new file mode 100644 index 0000000000..208779958f --- /dev/null +++ b/include/configs/mys_6ulx.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi + */ + +#ifndef __MYS_6ULX_H +#define __MYS_6ULX_H + +#include +#include "mx6_common.h" + +/* SPL options */ +#include "imx6_spl.h" + +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +/* Console configs */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_256M + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* NAND */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_IMX_THERMAL + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200n8\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "fdt_addr_r=0x82000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ + "ramdisk_addr_r=0x82100000\0" \ + "scriptaddr=0x87000000\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(UBIFS, ubifs, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#endif /* __MYS_6ULX_H */ diff --git a/include/dm-demo.h b/include/dm-demo.h index c9a82c7e52..7b6d0d80ff 100644 --- a/include/dm-demo.h +++ b/include/dm-demo.h @@ -6,8 +6,6 @@ #ifndef __DM_DEMO_H #define __DM_DEMO_H -#include - /** * struct dm_demo_pdata - configuration data for demo instance * diff --git a/include/dm.h b/include/dm.h index 2e1afda440..a1b84169e6 100644 --- a/include/dm.h +++ b/include/dm.h @@ -3,6 +3,10 @@ * Copyright (c) 2013 Google, Inc */ +#ifdef _DM_H_ +#warning "Suspect dm.h is included from a header file - please fix" +#endif + #ifndef _DM_H_ #define _DM_H_ diff --git a/include/dm/read.h b/include/dm/read.h index b1a6108544..487ec9e9c9 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -11,6 +11,7 @@ #include +#include #include #include #include diff --git a/include/dm/test.h b/include/dm/test.h index d39686cde2..2c92d41278 100644 --- a/include/dm/test.h +++ b/include/dm/test.h @@ -6,9 +6,6 @@ #ifndef __DM_TEST_H #define __DM_TEST_H -#include -#include - /** * struct dm_test_cdata - configuration data for test instance * diff --git a/include/dt-bindings/clock/octeon-clock.h b/include/dt-bindings/clock/octeon-clock.h new file mode 100644 index 0000000000..34e6a3bf41 --- /dev/null +++ b/include/dt-bindings/clock/octeon-clock.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Stefan Roese + */ + +#ifndef __DT_BINDINGS_CLOCK_OCTEON_CLOCK_H +#define __DT_BINDINGS_CLOCK_OCTEON_CLOCK_H + +#define OCTEON_CLK_CORE 0 +#define OCTEON_CLK_IO 1 + +#endif /* __DT_BINDINGS_CLOCK_OCTEON_CLOCK_H */ diff --git a/include/dt-bindings/reset/sifive-fu540-prci.h b/include/dt-bindings/reset/sifive-fu540-prci.h new file mode 100644 index 0000000000..89aa5b6679 --- /dev/null +++ b/include/dt-bindings/reset/sifive-fu540-prci.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Sifive, Inc. + * Author: Sagar Kadam + */ + +#ifndef __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H +#define __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H + +/* Reset indexes for use by device tree data and the PRCI driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 + +#endif diff --git a/include/efi_driver.h b/include/efi_driver.h index 840483a416..2b62219c5b 100644 --- a/include/efi_driver.h +++ b/include/efi_driver.h @@ -8,8 +8,6 @@ #ifndef _EFI_DRIVER_H #define _EFI_DRIVER_H 1 -#include -#include #include /* diff --git a/include/efi_variable.h b/include/efi_variable.h index 2c629e4dca..60491cb640 100644 --- a/include/efi_variable.h +++ b/include/efi_variable.h @@ -142,6 +142,22 @@ struct efi_var_file { */ efi_status_t efi_var_to_file(void); +/** + * efi_var_collect() - collect variables in buffer + * + * A buffer is allocated and filled with variables in a format ready to be + * written to disk. + * + * @bufp: pointer to pointer of buffer with collected variables + * @lenp: pointer to length of buffer + * @check_attr_mask: bitmask with required attributes of variables to be collected. + * variables are only collected if all of the required + * attributes are set. + * Return: status code + */ +efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t *lenp, + u32 check_attr_mask); + /** * efi_var_restore() - restore EFI variables from buffer * @@ -233,4 +249,62 @@ efi_status_t efi_init_secure_state(void); */ enum efi_auth_var_type efi_auth_var_get_type(u16 *name, const efi_guid_t *guid); +/** + * efi_get_next_variable_name_mem() - Runtime common code across efi variable + * implementations for GetNextVariable() + * from the cached memory copy + * @variable_name_size: size of variable_name buffer in byte + * @variable_name: name of uefi variable's name in u16 + * @vendor: vendor's guid + * + * Return: status code + */ +efi_status_t __efi_runtime +efi_get_next_variable_name_mem(efi_uintn_t *variable_name_size, u16 *variable_name, + efi_guid_t *vendor); +/** + * efi_get_variable_mem() - Runtime common code across efi variable + * implementations for GetVariable() from + * the cached memory copy + * + * @variable_name: name of the variable + * @vendor: vendor GUID + * @attributes: attributes of the variable + * @data_size: size of the buffer to which the variable value is copied + * @data: buffer to which the variable value is copied + * @timep: authentication time (seconds since start of epoch) + * Return: status code + + */ +efi_status_t __efi_runtime +efi_get_variable_mem(u16 *variable_name, const efi_guid_t *vendor, u32 *attributes, + efi_uintn_t *data_size, void *data, u64 *timep); + +/** + * efi_get_variable_runtime() - runtime implementation of GetVariable() + * + * @variable_name: name of the variable + * @guid: vendor GUID + * @attributes: attributes of the variable + * @data_size: size of the buffer to which the variable value is copied + * @data: buffer to which the variable value is copied + * Return: status code + */ +efi_status_t __efi_runtime EFIAPI +efi_get_variable_runtime(u16 *variable_name, const efi_guid_t *guid, + u32 *attributes, efi_uintn_t *data_size, void *data); + +/** + * efi_get_next_variable_name_runtime() - runtime implementation of + * GetNextVariable() + * + * @variable_name_size: size of variable_name buffer in byte + * @variable_name: name of uefi variable's name in u16 + * @guid: vendor's guid + * Return: status code + */ +efi_status_t __efi_runtime EFIAPI +efi_get_next_variable_name_runtime(efi_uintn_t *variable_name_size, + u16 *variable_name, efi_guid_t *guid); + #endif diff --git a/include/eth_phy.h b/include/eth_phy.h index 19c496551b..be6c881527 100644 --- a/include/eth_phy.h +++ b/include/eth_phy.h @@ -6,9 +6,10 @@ #ifndef _eth_phy_h_ #define _eth_phy_h_ -#include #include +struct udevice; + int eth_phy_binds_nodes(struct udevice *eth_dev); int eth_phy_set_mdio_bus(struct udevice *eth_dev, struct mii_dev *mdio_bus); struct mii_dev *eth_phy_get_mdio_bus(struct udevice *eth_dev); diff --git a/include/fs_loader.h b/include/fs_loader.h index b728c06fcf..1b3c58086f 100644 --- a/include/fs_loader.h +++ b/include/fs_loader.h @@ -6,7 +6,7 @@ #ifndef _FS_LOADER_H_ #define _FS_LOADER_H_ -#include +struct udevice; /** * struct phandle_part - A place for storing phandle of node and its partition diff --git a/include/kendryte/bypass.h b/include/kendryte/bypass.h index a081cbd12f..ab85bbcbfc 100644 --- a/include/kendryte/bypass.h +++ b/include/kendryte/bypass.h @@ -5,7 +5,7 @@ #ifndef K210_BYPASS_H #define K210_BYPASS_H -#include +struct clk; struct k210_bypass { struct clk clk; diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 8a20743ad8..79dce8f0ad 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -9,12 +9,13 @@ #ifndef __LINUX_CLK_PROVIDER_H #define __LINUX_CLK_PROVIDER_H -#include #include #include #include #include +struct udevice; + static inline void clk_dm(ulong id, struct clk *clk) { if (!IS_ERR(clk)) @@ -188,8 +189,5 @@ struct clk *clk_register_mux(struct device *dev, const char *name, const char *clk_hw_get_name(const struct clk *hw); ulong clk_generic_get_rate(struct clk *clk); -static inline struct clk *dev_get_clk_ptr(struct udevice *dev) -{ - return (struct clk *)dev_get_uclass_priv(dev); -} +struct clk *dev_get_clk_ptr(struct udevice *dev); #endif /* __LINUX_CLK_PROVIDER_H */ diff --git a/include/phy.h b/include/phy.h index fedd146091..1dbbf65111 100644 --- a/include/phy.h +++ b/include/phy.h @@ -9,14 +9,17 @@ #ifndef _PHY_H #define _PHY_H -#include +#include +#include +#include +#include #include #include #include #include #include -#include -#include + +struct udevice; #define PHY_FIXED_ID 0xa5a55a5a #define PHY_NCSI_ID 0xbeefcafe diff --git a/include/phy_interface.h b/include/phy_interface.h index 882e4af8ff..841ade311e 100644 --- a/include/phy_interface.h +++ b/include/phy_interface.h @@ -10,6 +10,8 @@ #ifndef _PHY_INTERFACE_H #define _PHY_INTERFACE_H +#include + typedef enum { PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_GMII, diff --git a/include/spi-mem.h b/include/spi-mem.h index 893f7bd733..ca0f55c8fd 100644 --- a/include/spi-mem.h +++ b/include/spi-mem.h @@ -11,10 +11,7 @@ #ifndef __UBOOT_SPI_MEM_H #define __UBOOT_SPI_MEM_H -#include -#include -#include -#include +struct udevice; #define SPI_MEM_OP_CMD(__opcode, __buswidth) \ { \ diff --git a/include/spi.h b/include/spi.h index 98ba9e796d..ef8c1f6692 100644 --- a/include/spi.h +++ b/include/spi.h @@ -146,8 +146,6 @@ struct spi_slave { #define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */ #define SPI_XFER_END BIT(1) /* Deassert CS after transfer */ #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) -#define SPI_XFER_MMAP BIT(2) /* Memory Mapped start */ -#define SPI_XFER_MMAP_END BIT(3) /* Memory Mapped End */ }; /** diff --git a/include/spi_flash.h b/include/spi_flash.h index b336619487..85cae32cc7 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -9,10 +9,11 @@ #ifndef _SPI_FLASH_H_ #define _SPI_FLASH_H_ -#include /* Because we dereference struct udevice here */ #include #include +struct udevice; + /* by default ENV use the same parameters than SF command */ #ifndef CONFIG_ENV_SPI_BUS # define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS diff --git a/include/test/ut.h b/include/test/ut.h index 99bbb1230c..6ab2f8830d 100644 --- a/include/test/ut.h +++ b/include/test/ut.h @@ -11,6 +11,7 @@ #include #include #include +#include struct unit_test_state; diff --git a/include/thermal.h b/include/thermal.h index 11d75256e0..52a3317fd5 100644 --- a/include/thermal.h +++ b/include/thermal.h @@ -7,7 +7,7 @@ #ifndef _THERMAL_H_ #define _THERMAL_H_ -#include +struct udevice; int thermal_get_temp(struct udevice *dev, int *temp); diff --git a/include/w1.h b/include/w1.h index b958b1c92c..77f439e587 100644 --- a/include/w1.h +++ b/include/w1.h @@ -8,7 +8,7 @@ #ifndef __W1_H #define __W1_H -#include +struct udevice; #define W1_FAMILY_DS24B33 0x23 #define W1_FAMILY_DS2431 0x2d diff --git a/include/wdt.h b/include/wdt.h index d2ccfbc62e..bc242c2eb2 100644 --- a/include/wdt.h +++ b/include/wdt.h @@ -6,9 +6,7 @@ #ifndef _WDT_H_ #define _WDT_H_ -#include -#include -#include +struct udevice; /* * Implement a simple watchdog uclass. Watchdog is basically a timer that diff --git a/lib/efi_driver/efi_block_device.c b/lib/efi_driver/efi_block_device.c index e7d8745ad8..0e72a68bce 100644 --- a/lib/efi_driver/efi_block_device.c +++ b/lib/efi_driver/efi_block_device.c @@ -30,6 +30,7 @@ #include #include +#include #include #include #include diff --git a/lib/efi_driver/efi_uclass.c b/lib/efi_driver/efi_uclass.c index 04e4e45734..0cf74b0361 100644 --- a/lib/efi_driver/efi_uclass.c +++ b/lib/efi_driver/efi_uclass.c @@ -17,6 +17,8 @@ * controllers. */ +#include +#include #include #include #include diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 441ac9432e..9bad1d159b 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -37,11 +37,11 @@ obj-y += efi_setup.o obj-$(CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2) += efi_unicode_collation.o obj-y += efi_var_common.o obj-y += efi_var_mem.o +obj-y += efi_var_file.o ifeq ($(CONFIG_EFI_MM_COMM_TEE),y) obj-y += efi_variable_tee.o else obj-y += efi_variable.o -obj-y += efi_var_file.o obj-$(CONFIG_EFI_VARIABLES_PRESEED) += efi_var_seed.o endif obj-y += efi_watchdog.o diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 44b8a2e09f..7be756e370 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -762,7 +762,7 @@ static void add_u_boot_and_runtime(void) unsigned long runtime_start, runtime_end, runtime_pages; unsigned long runtime_mask = EFI_PAGE_MASK; unsigned long uboot_start, uboot_pages; - unsigned long uboot_stack_size = 16 * 1024 * 1024; + unsigned long uboot_stack_size = CONFIG_STACK_SIZE; /* Add U-Boot */ uboot_start = ((uintptr_t)map_sysmem(gd->start_addr_sp, 0) - diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c index ee2e67bc8c..453cbce5c8 100644 --- a/lib/efi_loader/efi_var_common.c +++ b/lib/efi_loader/efi_var_common.c @@ -166,6 +166,28 @@ efi_status_t EFIAPI efi_query_variable_info( return EFI_EXIT(ret); } +efi_status_t __efi_runtime EFIAPI +efi_get_variable_runtime(u16 *variable_name, const efi_guid_t *guid, + u32 *attributes, efi_uintn_t *data_size, void *data) +{ + efi_status_t ret; + + ret = efi_get_variable_mem(variable_name, guid, attributes, data_size, data, NULL); + + /* Remove EFI_VARIABLE_READ_ONLY flag */ + if (attributes) + *attributes &= EFI_VARIABLE_MASK; + + return ret; +} + +efi_status_t __efi_runtime EFIAPI +efi_get_next_variable_name_runtime(efi_uintn_t *variable_name_size, + u16 *variable_name, efi_guid_t *guid) +{ + return efi_get_next_variable_name_mem(variable_name_size, variable_name, guid); +} + /** * efi_set_secure_state - modify secure boot state variables * @secure_boot: value of SecureBoot diff --git a/lib/efi_loader/efi_var_file.c b/lib/efi_loader/efi_var_file.c index 6f9d76f2a2..b171d2d1a8 100644 --- a/lib/efi_loader/efi_var_file.c +++ b/lib/efi_loader/efi_var_file.c @@ -46,18 +46,8 @@ static efi_status_t __maybe_unused efi_set_blk_dev_to_system_partition(void) return EFI_SUCCESS; } -/** - * efi_var_collect() - collect non-volatile variables in buffer - * - * A buffer is allocated and filled with all non-volatile variables in a - * format ready to be written to disk. - * - * @bufp: pointer to pointer of buffer with collected variables - * @lenp: pointer to length of buffer - * Return: status code - */ -static efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, - loff_t *lenp) +efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t *lenp, + u32 check_attr_mask) { size_t len = EFI_VAR_BUF_SIZE; struct efi_var_file *buf; @@ -102,11 +92,10 @@ static efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, free(buf); return ret; } - if (!(var->attr & EFI_VARIABLE_NON_VOLATILE)) - continue; - var->length = data_length; - var = (struct efi_var_entry *) - ALIGN((uintptr_t)data + data_length, 8); + if ((var->attr & check_attr_mask) == check_attr_mask) { + var->length = data_length; + var = (struct efi_var_entry *)ALIGN((uintptr_t)data + data_length, 8); + } } buf->reserved = 0; @@ -137,7 +126,7 @@ efi_status_t efi_var_to_file(void) loff_t actlen; int r; - ret = efi_var_collect(&buf, &len); + ret = efi_var_collect(&buf, &len, EFI_VARIABLE_NON_VOLATILE); if (ret != EFI_SUCCESS) goto error; diff --git a/lib/efi_loader/efi_var_mem.c b/lib/efi_loader/efi_var_mem.c index bfa8a56a8f..8f4a5a5e47 100644 --- a/lib/efi_loader/efi_var_mem.c +++ b/lib/efi_loader/efi_var_mem.c @@ -10,7 +10,7 @@ #include #include -static struct efi_var_file __efi_runtime_data *efi_var_buf; +struct efi_var_file __efi_runtime_data *efi_var_buf; static struct efi_var_entry __efi_runtime_data *efi_current_var; /** @@ -266,3 +266,71 @@ efi_status_t efi_var_mem_init(void) return ret; return ret; } + +efi_status_t __efi_runtime +efi_get_variable_mem(u16 *variable_name, const efi_guid_t *vendor, u32 *attributes, + efi_uintn_t *data_size, void *data, u64 *timep) +{ + efi_uintn_t old_size; + struct efi_var_entry *var; + u16 *pdata; + + if (!variable_name || !vendor || !data_size) + return EFI_INVALID_PARAMETER; + var = efi_var_mem_find(vendor, variable_name, NULL); + if (!var) + return EFI_NOT_FOUND; + + if (attributes) + *attributes = var->attr; + if (timep) + *timep = var->time; + + old_size = *data_size; + *data_size = var->length; + if (old_size < var->length) + return EFI_BUFFER_TOO_SMALL; + + if (!data) + return EFI_INVALID_PARAMETER; + + for (pdata = var->name; *pdata; ++pdata) + ; + ++pdata; + + efi_memcpy_runtime(data, pdata, var->length); + + return EFI_SUCCESS; +} + +efi_status_t __efi_runtime +efi_get_next_variable_name_mem(efi_uintn_t *variable_name_size, u16 *variable_name, + efi_guid_t *vendor) +{ + struct efi_var_entry *var; + efi_uintn_t old_size; + u16 *pdata; + + if (!variable_name_size || !variable_name || !vendor) + return EFI_INVALID_PARAMETER; + + efi_var_mem_find(vendor, variable_name, &var); + + if (!var) + return EFI_NOT_FOUND; + + for (pdata = var->name; *pdata; ++pdata) + ; + ++pdata; + + old_size = *variable_name_size; + *variable_name_size = (uintptr_t)pdata - (uintptr_t)var->name; + + if (old_size < *variable_name_size) + return EFI_BUFFER_TOO_SMALL; + + efi_memcpy_runtime(variable_name, var->name, *variable_name_size); + efi_memcpy_runtime(vendor, &var->guid, sizeof(efi_guid_t)); + + return EFI_SUCCESS; +} diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index 39a8482903..e509d6dbf0 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -282,68 +282,14 @@ efi_get_variable_int(u16 *variable_name, const efi_guid_t *vendor, u32 *attributes, efi_uintn_t *data_size, void *data, u64 *timep) { - efi_uintn_t old_size; - struct efi_var_entry *var; - u16 *pdata; - - if (!variable_name || !vendor || !data_size) - return EFI_INVALID_PARAMETER; - var = efi_var_mem_find(vendor, variable_name, NULL); - if (!var) - return EFI_NOT_FOUND; - - if (attributes) - *attributes = var->attr; - if (timep) - *timep = var->time; - - old_size = *data_size; - *data_size = var->length; - if (old_size < var->length) - return EFI_BUFFER_TOO_SMALL; - - if (!data) - return EFI_INVALID_PARAMETER; - - for (pdata = var->name; *pdata; ++pdata) - ; - ++pdata; - - efi_memcpy_runtime(data, pdata, var->length); - - return EFI_SUCCESS; + return efi_get_variable_mem(variable_name, vendor, attributes, data_size, data, timep); } efi_status_t __efi_runtime efi_get_next_variable_name_int(efi_uintn_t *variable_name_size, u16 *variable_name, efi_guid_t *vendor) { - struct efi_var_entry *var; - efi_uintn_t old_size; - u16 *pdata; - - if (!variable_name_size || !variable_name || !vendor) - return EFI_INVALID_PARAMETER; - - efi_var_mem_find(vendor, variable_name, &var); - - if (!var) - return EFI_NOT_FOUND; - - for (pdata = var->name; *pdata; ++pdata) - ; - ++pdata; - - old_size = *variable_name_size; - *variable_name_size = (uintptr_t)pdata - (uintptr_t)var->name; - - if (old_size < *variable_name_size) - return EFI_BUFFER_TOO_SMALL; - - efi_memcpy_runtime(variable_name, var->name, *variable_name_size); - efi_memcpy_runtime(vendor, &var->guid, sizeof(efi_guid_t)); - - return EFI_SUCCESS; + return efi_get_next_variable_name_mem(variable_name_size, variable_name, vendor); } efi_status_t efi_set_variable_int(u16 *variable_name, const efi_guid_t *vendor, @@ -504,49 +450,6 @@ efi_status_t __efi_runtime EFIAPI efi_query_variable_info_runtime( return EFI_UNSUPPORTED; } -/** - * efi_get_variable_runtime() - runtime implementation of GetVariable() - * - * @variable_name: name of the variable - * @vendor: vendor GUID - * @attributes: attributes of the variable - * @data_size: size of the buffer to which the variable value is copied - * @data: buffer to which the variable value is copied - * Return: status code - */ -static efi_status_t __efi_runtime EFIAPI -efi_get_variable_runtime(u16 *variable_name, const efi_guid_t *vendor, - u32 *attributes, efi_uintn_t *data_size, void *data) -{ - efi_status_t ret; - - ret = efi_get_variable_int(variable_name, vendor, attributes, - data_size, data, NULL); - - /* Remove EFI_VARIABLE_READ_ONLY flag */ - if (attributes) - *attributes &= EFI_VARIABLE_MASK; - - return ret; -} - -/** - * efi_get_next_variable_name_runtime() - runtime implementation of - * GetNextVariable() - * - * @variable_name_size: size of variable_name buffer in byte - * @variable_name: name of uefi variable's name in u16 - * @vendor: vendor's guid - * Return: status code - */ -static efi_status_t __efi_runtime EFIAPI -efi_get_next_variable_name_runtime(efi_uintn_t *variable_name_size, - u16 *variable_name, efi_guid_t *vendor) -{ - return efi_get_next_variable_name_int(variable_name_size, variable_name, - vendor); -} - /** * efi_set_variable_runtime() - runtime implementation of SetVariable() * diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c index 94c4de8703..be6f3dfad4 100644 --- a/lib/efi_loader/efi_variable_tee.c +++ b/lib/efi_loader/efi_variable_tee.c @@ -15,6 +15,8 @@ #include #include +#define OPTEE_PAGE_SIZE BIT(12) +extern struct efi_var_file __efi_runtime_data *efi_var_buf; static efi_uintn_t max_buffer_size; /* comm + var + func + data */ static efi_uintn_t max_payload_size; /* func + data */ @@ -237,8 +239,32 @@ efi_status_t EFIAPI get_max_payload(efi_uintn_t *size) if (ret != EFI_SUCCESS) goto out; + /* Make sure the buffer is big enough for storing variables */ + if (var_payload->size < MM_VARIABLE_ACCESS_HEADER_SIZE + 0x20) { + ret = EFI_DEVICE_ERROR; + goto out; + } *size = var_payload->size; - + /* + * Although the max payload is configurable on StMM, we only share a + * single page from OP-TEE for the non-secure buffer used to communicate + * with StMM. Since OP-TEE will reject to map anything bigger than that, + * make sure we are in bounds. + */ + if (*size > OPTEE_PAGE_SIZE) + *size = OPTEE_PAGE_SIZE - MM_COMMUNICATE_HEADER_SIZE - + MM_VARIABLE_COMMUNICATE_SIZE; + /* + * There seems to be a bug in EDK2 miscalculating the boundaries and + * size checks, so deduct 2 more bytes to fulfill this requirement. Fix + * it up here to ensure backwards compatibility with older versions + * (cf. StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c. + * sizeof (EFI_MM_COMMUNICATE_HEADER) instead the size minus the + * flexible array member). + * + * size is guaranteed to be > 2 due to checks on the beginning. + */ + *size -= 2; out: free(comm_buf); return ret; @@ -410,7 +436,6 @@ efi_status_t efi_get_next_variable_name_int(efi_uintn_t *variable_name_size, efi_uintn_t payload_size; efi_uintn_t out_name_size; efi_uintn_t in_name_size; - efi_uintn_t tmp_dsize; u8 *comm_buf = NULL; efi_status_t ret; @@ -433,13 +458,8 @@ efi_status_t efi_get_next_variable_name_int(efi_uintn_t *variable_name_size, } /* Trim output buffer size */ - tmp_dsize = *variable_name_size; - if (in_name_size + tmp_dsize > - max_payload_size - MM_VARIABLE_GET_NEXT_HEADER_SIZE) { - tmp_dsize = max_payload_size - - MM_VARIABLE_GET_NEXT_HEADER_SIZE - - in_name_size; - } + if (out_name_size > max_payload_size - MM_VARIABLE_GET_NEXT_HEADER_SIZE) + out_name_size = max_payload_size - MM_VARIABLE_GET_NEXT_HEADER_SIZE; payload_size = MM_VARIABLE_GET_NEXT_HEADER_SIZE + out_name_size; comm_buf = setup_mm_hdr((void **)&var_getnext, payload_size, @@ -465,8 +485,7 @@ efi_status_t efi_get_next_variable_name_int(efi_uintn_t *variable_name_size, goto out; guidcpy(guid, &var_getnext->guid); - memcpy(variable_name, (u8 *)var_getnext->name, - var_getnext->name_size); + memcpy(variable_name, var_getnext->name, var_getnext->name_size); out: free(comm_buf); @@ -599,39 +618,6 @@ out: return ret; } -/** - * efi_get_variable_runtime() - runtime implementation of GetVariable() - * - * @variable_name: name of the variable - * @guid: vendor GUID - * @attributes: attributes of the variable - * @data_size: size of the buffer to which the variable value is copied - * @data: buffer to which the variable value is copied - * Return: status code - */ -static efi_status_t __efi_runtime EFIAPI -efi_get_variable_runtime(u16 *variable_name, const efi_guid_t *guid, - u32 *attributes, efi_uintn_t *data_size, void *data) -{ - return EFI_UNSUPPORTED; -} - -/** - * efi_get_next_variable_name_runtime() - runtime implementation of - * GetNextVariable() - * - * @variable_name_size: size of variable_name buffer in byte - * @variable_name: name of uefi variable's name in u16 - * @guid: vendor's guid - * Return: status code - */ -static efi_status_t __efi_runtime EFIAPI -efi_get_next_variable_name_runtime(efi_uintn_t *variable_name_size, - u16 *variable_name, efi_guid_t *guid) -{ - return EFI_UNSUPPORTED; -} - /** * efi_query_variable_info() - get information about EFI variables * @@ -681,8 +667,10 @@ efi_set_variable_runtime(u16 *variable_name, const efi_guid_t *guid, */ void efi_variables_boot_exit_notify(void) { - u8 *comm_buf; efi_status_t ret; + u8 *comm_buf; + loff_t len; + struct efi_var_file *var_buf; comm_buf = setup_mm_hdr(NULL, 0, SMM_VARIABLE_FUNCTION_EXIT_BOOT_SERVICE, &ret); @@ -695,6 +683,18 @@ void efi_variables_boot_exit_notify(void) log_err("Unable to notify StMM for ExitBootServices\n"); free(comm_buf); + /* + * Populate the list for runtime variables. + * asking EFI_VARIABLE_RUNTIME_ACCESS is redundant, since + * efi_var_mem_notify_exit_boot_services will clean those, but that's fine + */ + ret = efi_var_collect(&var_buf, &len, EFI_VARIABLE_RUNTIME_ACCESS); + if (ret != EFI_SUCCESS) + log_err("Can't populate EFI variables. No runtime variables will be available\n"); + else + memcpy(efi_var_buf, var_buf, len); + free(var_buf); + /* Update runtime service table */ efi_runtime_services.query_variable_info = efi_query_variable_info_runtime; @@ -714,6 +714,11 @@ efi_status_t efi_init_variables(void) { efi_status_t ret; + /* Create a cached copy of the variables that will be enabled on ExitBootServices() */ + ret = efi_var_mem_init(); + if (ret != EFI_SUCCESS) + return ret; + ret = get_max_payload(&max_payload_size); if (ret != EFI_SUCCESS) return ret; diff --git a/lib/efi_selftest/Kconfig b/lib/efi_selftest/Kconfig index 478140330b..ca62436108 100644 --- a/lib/efi_selftest/Kconfig +++ b/lib/efi_selftest/Kconfig @@ -1,6 +1,8 @@ config CMD_BOOTEFI_SELFTEST bool "UEFI unit tests" depends on CMD_BOOTEFI + imply PARTITIONS + imply DOS_PARTITION imply FAT imply FAT_WRITE imply CMD_POWEROFF if PSCI_RESET || SYSRESET_PSCI diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile index e9baa64135..45ce6859b8 100644 --- a/lib/efi_selftest/Makefile +++ b/lib/efi_selftest/Makefile @@ -32,7 +32,6 @@ efi_selftest_memory.o \ efi_selftest_open_protocol.o \ efi_selftest_register_notify.o \ efi_selftest_set_virtual_address_map.o \ -efi_selftest_snp.o \ efi_selftest_textinput.o \ efi_selftest_textinputex.o \ efi_selftest_textoutput.o \ @@ -42,6 +41,8 @@ efi_selftest_variables.o \ efi_selftest_variables_runtime.o \ efi_selftest_watchdog.o +obj-$(CONFIG_NET) += efi_selftest_snp.o + obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_selftest_devicepath.o obj-$(CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2) += \ efi_selftest_unicode_collation.o @@ -56,7 +57,7 @@ ifeq ($(CONFIG_GENERATE_ACPI_TABLE),) obj-y += efi_selftest_fdt.o endif -ifeq ($(CONFIG_BLK)$(CONFIG_PARTITIONS),yy) +ifeq ($(CONFIG_BLK)$(CONFIG_DOS_PARTITION),yy) obj-y += efi_selftest_block_device.o endif diff --git a/net/eth_legacy.c b/net/eth_legacy.c index 340469ba3a..992d1880bf 100644 --- a/net/eth_legacy.c +++ b/net/eth_legacy.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 238f12cb46..3932362dba 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -2322,7 +2322,7 @@ sub get_raw_comment { # Checks specific to U-Boot sub u_boot_line { - my ($realfile, $line, $herecurr) = @_; + my ($realfile, $line, $rawline, $herecurr) = @_; # ask for a test if a new uclass ID is added if ($realfile =~ /uclass-id.h/ && $line =~ /^\+/) { @@ -2353,6 +2353,12 @@ sub u_boot_line { ERROR("DEFINE_CONFIG_CMD", "All commands are managed by Kconfig\n" . $herecurr); } + + # Don't put common.h and dm.h in header files + if ($realfile =~ /\.h$/ && $rawline =~ /^\+#include\s*<(common|dm)\.h>*/) { + ERROR("BARRED_INCLUDE_IN_HDR", + "Avoid including common.h and dm.h in header files\n" . $herecurr); + } } sub process { @@ -3296,7 +3302,7 @@ sub process { } if ($u_boot) { - u_boot_line($realfile, $line, $herecurr); + u_boot_line($realfile, $line, $rawline, $herecurr); } # check we are in a valid source file C or perl if not then ignore this hunk diff --git a/test/dm/adc.c b/test/dm/adc.c index da7bd4bf1f..7fa1d48dd9 100644 --- a/test/dm/adc.c +++ b/test/dm/adc.c @@ -17,6 +17,7 @@ #include #include #include +#include #include static int dm_test_adc_bind(struct unit_test_state *uts) diff --git a/test/dm/audio.c b/test/dm/audio.c index 77c3a3625b..4bb86e3214 100644 --- a/test/dm/audio.c +++ b/test/dm/audio.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include diff --git a/test/dm/axi.c b/test/dm/axi.c index e1155a51dd..5b1bbab0b8 100644 --- a/test/dm/axi.c +++ b/test/dm/axi.c @@ -8,9 +8,10 @@ #include #include #include -#include -#include #include +#include +#include +#include /* Test that sandbox AXI works correctly */ static int dm_test_axi_base(struct unit_test_state *uts) diff --git a/test/dm/blk.c b/test/dm/blk.c index 94b2855b8e..80d671e561 100644 --- a/test/dm/blk.c +++ b/test/dm/blk.c @@ -9,6 +9,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/test/dm/board.c b/test/dm/board.c index 5472c65fad..ff50d6c38b 100644 --- a/test/dm/board.c +++ b/test/dm/board.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "../../drivers/board/sandbox.h" diff --git a/test/dm/bootcount.c b/test/dm/bootcount.c index be0c278907..9fd3751ef7 100644 --- a/test/dm/bootcount.c +++ b/test/dm/bootcount.c @@ -9,6 +9,7 @@ #include #include #include +#include #include static int dm_test_bootcount(struct unit_test_state *uts) diff --git a/test/dm/bus.c b/test/dm/bus.c index 73eb3aede3..0707267361 100644 --- a/test/dm/bus.c +++ b/test/dm/bus.c @@ -14,6 +14,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/test/dm/clk.c b/test/dm/clk.c index 48fc3dd714..7a39760f25 100644 --- a/test/dm/clk.c +++ b/test/dm/clk.c @@ -12,6 +12,7 @@ #include #include #include +#include #include /* Base test of the clk uclass */ diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c index ae3a4d8a76..da2292a51a 100644 --- a/test/dm/clk_ccf.c +++ b/test/dm/clk_ccf.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include diff --git a/test/dm/core.c b/test/dm/core.c index d20c48443f..9b73ec3aa6 100644 --- a/test/dm/core.c +++ b/test/dm/core.c @@ -16,6 +16,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/test/dm/cpu.c b/test/dm/cpu.c index 46683d884a..0a75c91087 100644 --- a/test/dm/cpu.c +++ b/test/dm/cpu.c @@ -10,6 +10,7 @@ #include #include #include +#include #include static int dm_test_cpu(struct unit_test_state *uts) diff --git a/test/dm/dma.c b/test/dm/dma.c index 317ed4fe8c..1cdc813619 100644 --- a/test/dm/dma.c +++ b/test/dm/dma.c @@ -11,6 +11,7 @@ #include #include #include +#include #include static int dm_test_dma_m2m(struct unit_test_state *uts) diff --git a/test/dm/dsi_host.c b/test/dm/dsi_host.c index 59fcd5558f..97917a17c1 100644 --- a/test/dm/dsi_host.c +++ b/test/dm/dsi_host.c @@ -10,6 +10,7 @@ #include #include #include +#include #include static int dm_test_dsi_host_phy_init(void *priv_data) diff --git a/test/dm/eth.c b/test/dm/eth.c index b58c9640a2..1a3eb1839c 100644 --- a/test/dm/eth.c +++ b/test/dm/eth.c @@ -13,10 +13,11 @@ #include #include #include +#include #include #include #include -#include +#include #include #define DM_TEST_ETH_NUM 4 diff --git a/test/dm/firmware.c b/test/dm/firmware.c index 60fdcbb33f..2b4f49af80 100644 --- a/test/dm/firmware.c +++ b/test/dm/firmware.c @@ -8,6 +8,7 @@ #include #include #include +#include #include /* Base test of firmware probe */ diff --git a/test/dm/gpio.c b/test/dm/gpio.c index b7ee8fc3ca..f3c467e9ac 100644 --- a/test/dm/gpio.c +++ b/test/dm/gpio.c @@ -9,10 +9,11 @@ #include #include #include +#include #include #include #include -#include +#include #include /* Test that sandbox GPIOs work correctly */ diff --git a/test/dm/hwspinlock.c b/test/dm/hwspinlock.c index 09ec38b4f3..49c52bcd63 100644 --- a/test/dm/hwspinlock.c +++ b/test/dm/hwspinlock.c @@ -9,6 +9,7 @@ #include #include #include +#include #include /* Test that hwspinlock driver functions are called */ diff --git a/test/dm/i2c.c b/test/dm/i2c.c index 2025c4216d..25b2c7c617 100644 --- a/test/dm/i2c.c +++ b/test/dm/i2c.c @@ -16,6 +16,7 @@ #include #include #include +#include #include static const int busnum; diff --git a/test/dm/i2s.c b/test/dm/i2s.c index 49ebc3523c..7a017be064 100644 --- a/test/dm/i2s.c +++ b/test/dm/i2s.c @@ -7,9 +7,10 @@ #include #include #include -#include -#include #include +#include +#include +#include /* Basic test of the i2s codec uclass */ static int dm_test_i2s(struct unit_test_state *uts) diff --git a/test/dm/led.c b/test/dm/led.c index 00de7b3997..3d5ad9363b 100644 --- a/test/dm/led.c +++ b/test/dm/led.c @@ -8,6 +8,7 @@ #include #include #include +#include #include /* Base test of the led uclass */ diff --git a/test/dm/mailbox.c b/test/dm/mailbox.c index e6c521b8b5..e9c8ab1a95 100644 --- a/test/dm/mailbox.c +++ b/test/dm/mailbox.c @@ -8,6 +8,7 @@ #include #include #include +#include #include static int dm_test_mailbox(struct unit_test_state *uts) diff --git a/test/dm/mdio.c b/test/dm/mdio.c index ba1b54f27e..758bbb2cc5 100644 --- a/test/dm/mdio.c +++ b/test/dm/mdio.c @@ -7,10 +7,11 @@ #include #include #include -#include -#include -#include #include +#include +#include +#include +#include /* macros copied over from mdio_sandbox.c */ #define SANDBOX_PHY_ADDR 5 diff --git a/test/dm/mdio_mux.c b/test/dm/mdio_mux.c index f962e09dbc..0b3f85a53b 100644 --- a/test/dm/mdio_mux.c +++ b/test/dm/mdio_mux.c @@ -6,10 +6,11 @@ #include #include -#include -#include -#include #include +#include +#include +#include +#include /* macros copied over from mdio_sandbox.c */ #define SANDBOX_PHY_ADDR 5 diff --git a/test/dm/misc.c b/test/dm/misc.c index 26fd6acecb..641070972d 100644 --- a/test/dm/misc.c +++ b/test/dm/misc.c @@ -8,6 +8,7 @@ #include #include #include +#include #include static int dm_test_misc(struct unit_test_state *uts) diff --git a/test/dm/mmc.c b/test/dm/mmc.c index 49402b9c90..8e1fd3fe51 100644 --- a/test/dm/mmc.c +++ b/test/dm/mmc.c @@ -8,6 +8,7 @@ #include #include #include +#include #include /* diff --git a/test/dm/nop.c b/test/dm/nop.c index 2df29f3d15..8b3b646892 100644 --- a/test/dm/nop.c +++ b/test/dm/nop.c @@ -13,6 +13,7 @@ #include #include #include +#include #include static int noptest_bind(struct udevice *parent) diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c index 1114f34cbf..e01acc4fe9 100644 --- a/test/dm/ofnode.c +++ b/test/dm/ofnode.c @@ -5,6 +5,7 @@ #include #include #include +#include #include static int dm_test_ofnode_compatible(struct unit_test_state *uts) diff --git a/test/dm/osd.c b/test/dm/osd.c index 5739dfa0b8..8784867ecb 100644 --- a/test/dm/osd.c +++ b/test/dm/osd.c @@ -7,10 +7,11 @@ #include #include #include -#include -#include #include #include +#include +#include +#include #include "../../drivers/video/sandbox_osd.h" diff --git a/test/dm/panel.c b/test/dm/panel.c index 7e4ebd6d81..410e8f3907 100644 --- a/test/dm/panel.c +++ b/test/dm/panel.c @@ -14,8 +14,9 @@ #include #include #include -#include #include +#include +#include /* Basic test of the panel uclass */ static int dm_test_panel(struct unit_test_state *uts) diff --git a/test/dm/pch.c b/test/dm/pch.c index 54e33d187b..bf17a31ccf 100644 --- a/test/dm/pch.c +++ b/test/dm/pch.c @@ -8,6 +8,7 @@ #include #include #include +#include #include /* Test that sandbox PCH works correctly */ diff --git a/test/dm/pci.c b/test/dm/pci.c index 39e82b3699..a492fc0355 100644 --- a/test/dm/pci.c +++ b/test/dm/pci.c @@ -8,6 +8,7 @@ #include #include #include +#include #include /* Test that sandbox PCI works correctly */ diff --git a/test/dm/pci_ep.c b/test/dm/pci_ep.c index 101f861751..a29d00eebe 100644 --- a/test/dm/pci_ep.c +++ b/test/dm/pci_ep.c @@ -5,12 +5,13 @@ #include #include +#include +#include #include #include #include +#include #include -#include -#include /* Test that sandbox PCI EP works correctly */ static int dm_test_pci_ep_base(struct unit_test_state *uts) diff --git a/test/dm/phy.c b/test/dm/phy.c index 99f0119557..1a59899327 100644 --- a/test/dm/phy.c +++ b/test/dm/phy.c @@ -9,6 +9,7 @@ #include #include #include +#include #include /* Base test of the phy uclass */ diff --git a/test/dm/pmic.c b/test/dm/pmic.c index b582329a9c..8c2766aeac 100644 --- a/test/dm/pmic.c +++ b/test/dm/pmic.c @@ -10,16 +10,17 @@ #include #include #include +#include #include #include #include -#include #include #include +#include #include #include +#include #include -#include /* Test PMIC get method */ diff --git a/test/dm/power-domain.c b/test/dm/power-domain.c index 8baf5d09d1..52f88c5a36 100644 --- a/test/dm/power-domain.c +++ b/test/dm/power-domain.c @@ -8,6 +8,7 @@ #include #include #include +#include #include /* This must match the specifier for power-domains in the DT node */ diff --git a/test/dm/pwm.c b/test/dm/pwm.c index b52ee21a69..8cc911e1ad 100644 --- a/test/dm/pwm.c +++ b/test/dm/pwm.c @@ -7,6 +7,7 @@ #include #include #include +#include #include /* Basic test of the pwm uclass */ diff --git a/test/dm/ram.c b/test/dm/ram.c index 3efdb6b80b..2456466b56 100644 --- a/test/dm/ram.c +++ b/test/dm/ram.c @@ -7,6 +7,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/test/dm/regmap.c b/test/dm/regmap.c index 809494d585..42cc4cb0c0 100644 --- a/test/dm/regmap.c +++ b/test/dm/regmap.c @@ -12,6 +12,7 @@ #include #include #include +#include #include /* Base test of register maps */ diff --git a/test/dm/regulator.c b/test/dm/regulator.c index ca916eeebb..f412ec20c5 100644 --- a/test/dm/regulator.c +++ b/test/dm/regulator.c @@ -20,6 +20,7 @@ #include #include #include +#include #include enum { diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c index 9511c7dd6f..c6bf2c4c46 100644 --- a/test/dm/remoteproc.c +++ b/test/dm/remoteproc.c @@ -10,7 +10,9 @@ #include #include #include +#include #include + /** * dm_test_remoteproc_base() - test the operations after initializations * @uts: unit test state diff --git a/test/dm/reset.c b/test/dm/reset.c index 871d6400a0..8232807264 100644 --- a/test/dm/reset.c +++ b/test/dm/reset.c @@ -10,6 +10,7 @@ #include #include #include +#include #include /* This must match the specifier for mbox-names="test" in the DT node */ diff --git a/test/dm/rtc.c b/test/dm/rtc.c index dd037a6e17..42a9195b73 100644 --- a/test/dm/rtc.c +++ b/test/dm/rtc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include /* Simple RTC sanity check */ diff --git a/test/dm/serial.c b/test/dm/serial.c index 6237693cb8..a1b122ec1d 100644 --- a/test/dm/serial.c +++ b/test/dm/serial.c @@ -8,6 +8,7 @@ #include #include #include +#include #include static int dm_test_serial(struct unit_test_state *uts) diff --git a/test/dm/sf.c b/test/dm/sf.c index 9e7dead684..0f2808fca4 100644 --- a/test/dm/sf.c +++ b/test/dm/sf.c @@ -15,6 +15,7 @@ #include #include #include +#include #include /* Simple test of sandbox SPI flash */ diff --git a/test/dm/smem.c b/test/dm/smem.c index 4099a5f66c..21dd96e409 100644 --- a/test/dm/smem.c +++ b/test/dm/smem.c @@ -7,6 +7,7 @@ #include #include #include +#include #include /* Basic test of the smem uclass */ diff --git a/test/dm/sound.c b/test/dm/sound.c index aa5368f05b..9cb9961058 100644 --- a/test/dm/sound.c +++ b/test/dm/sound.c @@ -9,6 +9,7 @@ #include #include #include +#include #include /* Basic test of the sound codec uclass */ diff --git a/test/dm/spi.c b/test/dm/spi.c index ff2cddd245..10b89e7acf 100644 --- a/test/dm/spi.c +++ b/test/dm/spi.c @@ -13,6 +13,7 @@ #include #include #include +#include #include /* Test that we can find buses and chip-selects */ diff --git a/test/dm/spmi.c b/test/dm/spmi.c index 668b7e133f..4aae1f166d 100644 --- a/test/dm/spmi.c +++ b/test/dm/spmi.c @@ -14,6 +14,7 @@ #include #include #include +#include #include /* Test if bus childs got probed propperly*/ diff --git a/test/dm/syscon.c b/test/dm/syscon.c index 06a1c69ac5..b2d0ade95e 100644 --- a/test/dm/syscon.c +++ b/test/dm/syscon.c @@ -11,6 +11,7 @@ #include #include #include +#include #include /* Base test of system controllers */ diff --git a/test/dm/sysreset.c b/test/dm/sysreset.c index 5b2358ef67..e5cd18cd82 100644 --- a/test/dm/sysreset.c +++ b/test/dm/sysreset.c @@ -9,6 +9,7 @@ #include #include #include +#include #include /* Test that we can use particular sysreset devices */ diff --git a/test/dm/tee.c b/test/dm/tee.c index 632e9960b0..fec9551fb2 100644 --- a/test/dm/tee.c +++ b/test/dm/tee.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include diff --git a/test/dm/test-driver.c b/test/dm/test-driver.c index ba85fa313e..08bdf01194 100644 --- a/test/dm/test-driver.c +++ b/test/dm/test-driver.c @@ -11,9 +11,10 @@ #include #include #include -#include -#include #include +#include +#include +#include int dm_testdrv_op_count[DM_TEST_OP_COUNT]; static struct unit_test_state *uts = &global_dm_test_state; diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c index 8ef7c7a88e..c64ac405ed 100644 --- a/test/dm/test-fdt.c +++ b/test/dm/test-fdt.c @@ -18,6 +18,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/test/dm/test-main.c b/test/dm/test-main.c index 53e5ca321f..6d197d0d61 100644 --- a/test/dm/test-main.c +++ b/test/dm/test-main.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/test/dm/test-uclass.c b/test/dm/test-uclass.c index b6d629a285..760731b066 100644 --- a/test/dm/test-uclass.c +++ b/test/dm/test-uclass.c @@ -14,6 +14,7 @@ #include #include #include +#include #include static struct unit_test_state *uts = &global_dm_test_state; diff --git a/test/dm/timer.c b/test/dm/timer.c index 9367dab5d5..4aa5eeac75 100644 --- a/test/dm/timer.c +++ b/test/dm/timer.c @@ -7,6 +7,7 @@ #include #include #include +#include #include /* diff --git a/test/dm/usb.c b/test/dm/usb.c index b273a515ef..6cbb66c82b 100644 --- a/test/dm/usb.c +++ b/test/dm/usb.c @@ -14,6 +14,7 @@ #include #include #include +#include #include struct keyboard_test_data { diff --git a/test/dm/video.c b/test/dm/video.c index 19f78b6239..9523a0173d 100644 --- a/test/dm/video.c +++ b/test/dm/video.c @@ -15,6 +15,7 @@ #include #include #include +#include #include /* diff --git a/test/dm/virtio.c b/test/dm/virtio.c index 4a0c0b23b8..6361cd5333 100644 --- a/test/dm/virtio.c +++ b/test/dm/virtio.c @@ -9,9 +9,10 @@ #include #include #include -#include #include #include +#include +#include #include /* Basic test of the virtio uclass */ diff --git a/test/dm/wdt.c b/test/dm/wdt.c index 1d31ec55c6..c704098b24 100644 --- a/test/dm/wdt.c +++ b/test/dm/wdt.c @@ -9,6 +9,7 @@ #include #include #include +#include #include /* Test that watchdog driver functions are called */ diff --git a/test/lib/lmb.c b/test/lib/lmb.c index a0fe0f6b33..a344987509 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -4,10 +4,12 @@ */ #include +#include #include #include #include #include +#include #include static int check_lmb(struct unit_test_state *uts, struct lmb *lmb, diff --git a/tools/patman/test_checkpatch.py b/tools/patman/test_checkpatch.py index c9580adb54..792196e689 100644 --- a/tools/patman/test_checkpatch.py +++ b/tools/patman/test_checkpatch.py @@ -373,19 +373,19 @@ index 0000000..2234c87 self.checkSingleMessage(pm, 'NEW_UCLASS') def testLivetree(self): - """Test for Use the livetree API""" + """Test for using the livetree API""" pm = PatchMaker() pm.add_line('common/main.c', 'fdtdec_do_something()') self.checkSingleMessage(pm, 'LIVETREE') def testNewCommand(self): - """Test for Use the livetree API""" + """Test for adding a new command""" pm = PatchMaker() pm.add_line('common/main.c', 'do_wibble(struct cmd_tbl *cmd_tbl)') self.checkSingleMessage(pm, 'CMD_TEST') - def testNewCommand(self): - """Test for Use the livetree API""" + def testPreferIf(self): + """Test for using #ifdef""" pm = PatchMaker() pm.add_line('common/main.c', '#ifdef CONFIG_YELLOW') pm.add_line('common/init.h', '#ifdef CONFIG_YELLOW') @@ -393,11 +393,18 @@ index 0000000..2234c87 self.checkSingleMessage(pm, "PREFER_IF") def testCommandUseDefconfig(self): - """Test for Use the livetree API""" + """Test for enabling/disabling commands using preprocesor""" pm = PatchMaker() pm.add_line('common/main.c', '#undef CONFIG_CMD_WHICH') self.checkSingleMessage(pm, 'DEFINE_CONFIG_CMD', 'error') + def testBarredIncludeInHdr(self): + """Test for using a barred include in a header file""" + pm = PatchMaker() + #pm.add_line('include/myfile.h', '#include ') + pm.add_line('include/myfile.h', '#include ') + self.checkSingleMessage(pm, 'BARRED_INCLUDE_IN_HDR', 'error') + if __name__ == "__main__": unittest.main()