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riscv: complete the list of exception codes

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Only the first four exception codes are defined. Add the missing
exception codes from the definition in RISC-V Privileged Architecture
Version 1.10.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Lukas Auer
2018-11-22 11:26:20 +01:00
committed by Andes
parent f105d2efcb
commit 5a441736b7
1 changed files with 12 additions and 1 deletions
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13
arch/riscv/lib/interrupts.c
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@@ -67,7 +67,18 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
"Instruction access fault", "Instruction access fault",
"Illegal instruction", "Illegal instruction",
"Breakpoint", "Breakpoint",
"Load address misaligned" "Load address misaligned",
"Load access fault",
"Store/AMO address misaligned",
"Store/AMO access fault",
"Environment call from U-mode",
"Environment call from S-mode",
"Reserved",
"Environment call from M-mode",
"Instruction page fault",
"Load page fault",
"Reserved",
"Store/AMO page fault",
}; };
printf("exception code: %ld , %s , epc %lx , ra %lx\n", printf("exception code: %ld , %s , epc %lx , ra %lx\n",