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ddr: altera: Add SDRAM driver for Intel N5X device

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The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.

Configuration settings of controller, PHY and  memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and user settings from tool.

Configuration settings of memory clock manager is come from the HPS
handoff data in bitstream, however the register base address is defined
in device tree.

The calibration is fully done in HPS, which requires IMEM and DMEM
binaries loading to PHY SRAM for running this calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
This commit is contained in:
Tien Fong Chee
2021-08-10 11:26:37 +08:00
parent 1b378cc95a
commit 59d4230429
6 changed files with 2386 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/ddr/altera/Makefile
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@@ -4,11 +4,12 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
# Copyright (C) 2014 Altera Corporation <www.altera.com>
# Copyright (C) 2014-2021 Altera Corporation <www.altera.com>
ifdef CONFIG_$(SPL_)ALTERA_SDRAM
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o
endif

2298
drivers/ddr/altera/sdram_n5x.c Normal file
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File diff suppressed because it is too large Load Diff

70
drivers/ddr/altera/sdram_soc64.c
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@@ -100,12 +100,14 @@ int emif_reset(struct altera_sdram_plat *plat)
return 0;
}
#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
int poll_hmc_clock_status(void)
{
return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_HMC_CLK),
SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
}
#endif
void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
{
@@ -249,11 +251,78 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat)
return size;
}
void sdram_set_firewall(struct bd_info *bd)
{
u32 i;
phys_size_t value;
u32 lower, upper;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
if (!bd->bi_dram[i].size)
continue;
value = bd->bi_dram[i].start;
/* Keep first 1MB of SDRAM memory region as secure region when
* using ATF flow, where the ATF code is located.
*/
if (IS_ENABLED(CONFIG_SPL_ATF) && i == 0)
value += SZ_1M;
/* Setting non-secure MPU region base and base extended */
lower = lower_32_bits(value);
upper = upper_32_bits(value);
FW_MPU_DDR_SCR_WRITEL(lower,
FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE +
(i * 4 * sizeof(u32)));
FW_MPU_DDR_SCR_WRITEL(upper & 0xff,
FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT +
(i * 4 * sizeof(u32)));
/* Setting non-secure Non-MPU region base and base extended */
FW_MPU_DDR_SCR_WRITEL(lower,
FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASE +
(i * 4 * sizeof(u32)));
FW_MPU_DDR_SCR_WRITEL(upper & 0xff,
FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT +
(i * 4 * sizeof(u32)));
/* Setting non-secure MPU limit and limit extexded */
value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1;
lower = lower_32_bits(value);
upper = upper_32_bits(value);
FW_MPU_DDR_SCR_WRITEL(lower,
FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT +
(i * 4 * sizeof(u32)));
FW_MPU_DDR_SCR_WRITEL(upper & 0xff,
FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT +
(i * 4 * sizeof(u32)));
/* Setting non-secure Non-MPU limit and limit extexded */
FW_MPU_DDR_SCR_WRITEL(lower,
FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT +
(i * 4 * sizeof(u32)));
FW_MPU_DDR_SCR_WRITEL(upper & 0xff,
FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT +
(i * 4 * sizeof(u32)));
FW_MPU_DDR_SCR_WRITEL(BIT(i) | BIT(i + 8),
FW_MPU_DDR_SCR_EN_SET);
}
}
static int altera_sdram_of_to_plat(struct udevice *dev)
{
struct altera_sdram_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
/* These regs info are part of DDR handoff in bitstream */
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
return 0;
#endif
addr = dev_read_addr_index(dev, 0);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
@@ -314,6 +383,7 @@ static struct ram_ops altera_sdram_ops = {
static const struct udevice_id altera_sdram_ids[] = {
{ .compatible = "altr,sdr-ctl-s10" },
{ .compatible = "intel,sdr-ctl-agilex" },
{ .compatible = "intel,sdr-ctl-n5x" },
{ /* sentinel */ }
};

1
drivers/ddr/altera/sdram_soc64.h
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@@ -180,6 +180,7 @@ int emif_reset(struct altera_sdram_plat *plat);
int poll_hmc_clock_status(void);
void sdram_clear_mem(phys_addr_t addr, phys_size_t size);
void sdram_init_ecc_bits(struct bd_info *bd);
void sdram_set_firewall(struct bd_info *bd);
void sdram_size_check(struct bd_info *bd);
phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat);
int sdram_mmr_init_full(struct udevice *dev);