dany/u-boot-megous
1
0
Fork 0
mirror of https://xff.cz/git/u-boot/ synced 2025-09-03 17:52:07 +02:00
Code Issues Packages Projects Releases Wiki Activity

riscv: ax25: cache: Remove SPL_RISCV_MMODE config check

Browse Source 
CONFIG_IS_ENABLED(FOO) will check FOO config option for U-Boot,
SPL and TPL, so remove unnecessary CONFIG_IS_ENABLED()

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Pragnesh Patel
2020-03-14 19:12:28 +05:30
committed by Andes
parent caad316b31
commit 5988bb9dbf
1 changed files with 8 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
arch/riscv/cpu/ax25/cache.c
View File

@@ -12,7 +12,7 @@
#include <asm/csr.h> #include <asm/csr.h>
#ifdef CONFIG_RISCV_NDS_CACHE #ifdef CONFIG_RISCV_NDS_CACHE
#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) #if CONFIG_IS_ENABLED(RISCV_MMODE)
/* mcctlcommand */ /* mcctlcommand */
#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc #define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc
@@ -47,7 +47,7 @@ void flush_dcache_all(void)
{ {
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE #ifdef CONFIG_RISCV_NDS_CACHE
#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) #if CONFIG_IS_ENABLED(RISCV_MMODE)
csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
#endif #endif
#endif #endif
@@ -68,7 +68,7 @@ void icache_enable(void)
{ {
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE #ifdef CONFIG_RISCV_NDS_CACHE
#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) #if CONFIG_IS_ENABLED(RISCV_MMODE)
asm volatile ( asm volatile (
"csrr t1, mcache_ctl\n\t" "csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x1\n\t" "ori t0, t1, 0x1\n\t"
@@ -83,7 +83,7 @@ void icache_disable(void)
{ {
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE #ifdef CONFIG_RISCV_NDS_CACHE
#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) #if CONFIG_IS_ENABLED(RISCV_MMODE)
asm volatile ( asm volatile (
"fence.i\n\t" "fence.i\n\t"
"csrr t1, mcache_ctl\n\t" "csrr t1, mcache_ctl\n\t"
@@ -99,7 +99,7 @@ void dcache_enable(void)
{ {
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE #ifdef CONFIG_RISCV_NDS_CACHE
#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) #if CONFIG_IS_ENABLED(RISCV_MMODE)
asm volatile ( asm volatile (
"csrr t1, mcache_ctl\n\t" "csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x2\n\t" "ori t0, t1, 0x2\n\t"
@@ -117,7 +117,7 @@ void dcache_disable(void)
{ {
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE #ifdef CONFIG_RISCV_NDS_CACHE
#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) #if CONFIG_IS_ENABLED(RISCV_MMODE)
csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
asm volatile ( asm volatile (
"csrr t1, mcache_ctl\n\t" "csrr t1, mcache_ctl\n\t"
@@ -137,7 +137,7 @@ int icache_status(void)
int ret = 0; int ret = 0;
#ifdef CONFIG_RISCV_NDS_CACHE #ifdef CONFIG_RISCV_NDS_CACHE
#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) #if CONFIG_IS_ENABLED(RISCV_MMODE)
asm volatile ( asm volatile (
"csrr t1, mcache_ctl\n\t" "csrr t1, mcache_ctl\n\t"
"andi %0, t1, 0x01\n\t" "andi %0, t1, 0x01\n\t"
@@ -156,7 +156,7 @@ int dcache_status(void)
int ret = 0; int ret = 0;
#ifdef CONFIG_RISCV_NDS_CACHE #ifdef CONFIG_RISCV_NDS_CACHE
#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) #if CONFIG_IS_ENABLED(RISCV_MMODE)
asm volatile ( asm volatile (
"csrr t1, mcache_ctl\n\t" "csrr t1, mcache_ctl\n\t"
"andi %0, t1, 0x02\n\t" "andi %0, t1, 0x02\n\t"