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rockchip: clk: rk322x: fix assert clock value

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BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang
2019-04-02 20:41:23 +08:00
parent e4d0d61275
commit 5793e8c271
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk_rk322x.c
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@@ -121,10 +121,10 @@ static void rkclk_init(struct rk322x_cru *cru)
assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
rk_clrsetreg(&cru->cru_clksel_con[0], rk_clrsetreg(&cru->cru_clksel_con[0],
BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,