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mmc: tmio: sdhi: Add calibration tables
Instead of using single fixed value for the calibration offset, add tables which dynamically adjust this per calibration code from the SCC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
@@ -63,6 +63,49 @@
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#define RENESAS_SDHI_MAX_TAP 3
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#define RENESAS_SDHI_MAX_TAP 3
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#define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1)
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static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = {
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{ 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 5, 5, 6, 6, 7, 11,
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15, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 21 },
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{ 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 15,
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16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 22 }
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};
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static const u8 r8a7796_rev1_calib_table[2][CALIB_TABLE_MAX] = {
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 9,
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15, 15, 15, 16, 16, 16, 16, 16, 17, 18, 19, 20, 21, 21, 22, 22 },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
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2, 9, 16, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 23, 24}
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};
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static const u8 r8a7796_rev3_calib_table[2][CALIB_TABLE_MAX] = {
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{ 0, 0, 0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 9, 10,
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11, 12, 13, 15, 16, 17, 17, 18, 19, 19, 20, 21, 21, 22, 23, 23 },
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{ 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12,
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13, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22, 22, 23, 24, 24 }
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};
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static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = {
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{ 0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15,
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16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 29 },
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{ 0, 1, 2, 2, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 15,
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16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 31 }
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};
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static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ 0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 5, 6, 7, 8, 10, 11,
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12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
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};
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static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
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{
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/* On R-Car Gen3, MMC0 is at 0xee140000 */
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return (uintptr_t)(priv->regbase) == 0xee140000;
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}
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static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
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static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
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{
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{
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/* read mode */
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/* read mode */
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@@ -198,28 +241,30 @@ static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
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if (!priv->needs_adjust_hs400)
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if (!priv->needs_adjust_hs400)
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return;
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return;
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if (!priv->adjust_hs400_calib_table)
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return;
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/*
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/*
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* Enabled Manual adjust HS400 mode
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* Enabled Manual adjust HS400 mode
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*
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*
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* 1) Disabled Write Protect
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* 1) Disabled Write Protect
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* W(addr=0x00, WP_DISABLE_CODE)
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* W(addr=0x00, WP_DISABLE_CODE)
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* 2) Read Calibration code and adjust
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*
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* R(addr=0x26) - adjust value
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* 2) Read Calibration code
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* 3) Enabled Manual Calibration
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* read_value = R(addr=0x26)
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* 3) Refer to calibration table
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* Calibration code = table[read_value]
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* 4) Enabled Manual Calibration
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* W(addr=0x22, manual mode | Calibration code)
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* W(addr=0x22, manual mode | Calibration code)
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* 4) Set Offset value to TMPPORT3 Reg
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* 5) Set Offset value to TMPPORT3 Reg
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*/
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*/
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sd_scc_tmpport_write32(priv, 0x00,
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sd_scc_tmpport_write32(priv, 0x00,
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RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
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RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
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calib_code = sd_scc_tmpport_read32(priv, 0x26);
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calib_code = sd_scc_tmpport_read32(priv, 0x26);
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calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
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calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
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if (calib_code > priv->adjust_hs400_calibrate)
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calib_code -= priv->adjust_hs400_calibrate;
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else
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calib_code = 0;
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sd_scc_tmpport_write32(priv, 0x22,
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sd_scc_tmpport_write32(priv, 0x22,
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RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
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RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
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calib_code);
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priv->adjust_hs400_calib_table[calib_code]);
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tmio_sd_writel(priv, priv->adjust_hs400_offset,
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tmio_sd_writel(priv, priv->adjust_hs400_offset,
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RENESAS_SDHI_SCC_TMPPORT3);
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RENESAS_SDHI_SCC_TMPPORT3);
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@@ -705,18 +750,22 @@ static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
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static void renesas_sdhi_filter_caps(struct udevice *dev)
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static void renesas_sdhi_filter_caps(struct udevice *dev)
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{
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{
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struct tmio_sd_plat *plat = dev_get_platdata(dev);
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struct tmio_sd_priv *priv = dev_get_priv(dev);
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struct tmio_sd_priv *priv = dev_get_priv(dev);
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if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
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if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
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return;
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return;
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/* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1,ES1.2 */
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#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
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CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
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CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
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struct tmio_sd_plat *plat = dev_get_platdata(dev);
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/* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
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if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
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if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
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(rmobile_get_cpu_rev_integer() <= 1)) ||
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(rmobile_get_cpu_rev_integer() <= 1)) ||
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((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
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((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
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(rmobile_get_cpu_rev_integer() == 1) &&
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(rmobile_get_cpu_rev_integer() == 1) &&
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(rmobile_get_cpu_rev_fraction() <= 2)))
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(rmobile_get_cpu_rev_fraction() < 2)))
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plat->cfg.host_caps &= ~MMC_MODE_HS400;
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plat->cfg.host_caps &= ~MMC_MODE_HS400;
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/* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
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/* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
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@@ -728,28 +777,50 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
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(rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
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(rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
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priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
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priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
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/* H3 ES3.0 can use HS400 with manual adjustment */
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if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
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(rmobile_get_cpu_rev_integer() >= 3)) {
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priv->adjust_hs400_enable = true;
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priv->adjust_hs400_offset = 0;
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priv->adjust_hs400_calib_table =
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r8a7795_calib_table[!rmobile_is_gen3_mmc0(priv)];
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}
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/* M3W ES1.2 can use HS400 with manual adjustment */
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if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
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(rmobile_get_cpu_rev_integer() == 1) &&
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(rmobile_get_cpu_rev_fraction() == 2)) {
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priv->adjust_hs400_enable = true;
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priv->adjust_hs400_offset = 3;
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priv->adjust_hs400_calib_table =
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r8a7796_rev1_calib_table[!rmobile_is_gen3_mmc0(priv)];
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}
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/* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
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/* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
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if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
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if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
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(rmobile_get_cpu_rev_integer() == 1) &&
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(rmobile_get_cpu_rev_integer() == 1) &&
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(rmobile_get_cpu_rev_fraction() > 2)) {
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(rmobile_get_cpu_rev_fraction() > 2)) {
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priv->adjust_hs400_enable = true;
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priv->adjust_hs400_enable = true;
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priv->adjust_hs400_offset = 3;
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priv->adjust_hs400_offset = 0;
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priv->adjust_hs400_calibrate = 0x9;
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priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
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priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
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priv->adjust_hs400_calib_table =
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r8a7796_rev3_calib_table[!rmobile_is_gen3_mmc0(priv)];
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}
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}
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/* M3N can use HS400 with manual adjustment */
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/* M3N can use HS400 with manual adjustment */
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if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
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if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
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priv->adjust_hs400_enable = true;
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priv->adjust_hs400_enable = true;
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priv->adjust_hs400_offset = 3;
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priv->adjust_hs400_offset = 3;
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priv->adjust_hs400_calibrate = 0x0;
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priv->adjust_hs400_calib_table =
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r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)];
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}
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}
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/* E3 can use HS400 with manual adjustment */
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/* E3 can use HS400 with manual adjustment */
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if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
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if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
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priv->adjust_hs400_enable = true;
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priv->adjust_hs400_enable = true;
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priv->adjust_hs400_offset = 3;
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priv->adjust_hs400_offset = 3;
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priv->adjust_hs400_calibrate = 0x4;
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priv->adjust_hs400_calib_table =
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r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)];
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}
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}
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/* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */
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/* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */
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@@ -761,7 +832,7 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
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priv->nrtaps = 4;
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priv->nrtaps = 4;
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else
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else
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priv->nrtaps = 8;
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priv->nrtaps = 8;
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#endif
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/* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
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/* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
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if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
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if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
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(rmobile_get_cpu_rev_integer() <= 1)) ||
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(rmobile_get_cpu_rev_integer() <= 1)) ||
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@@ -146,6 +146,7 @@ struct tmio_sd_priv {
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u8 adjust_hs400_offset;
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u8 adjust_hs400_offset;
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u8 adjust_hs400_calibrate;
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u8 adjust_hs400_calibrate;
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u8 hs400_bad_tap;
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u8 hs400_bad_tap;
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const u8 *adjust_hs400_calib_table;
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#endif
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#endif
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ulong (*clk_get_rate)(struct tmio_sd_priv *);
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ulong (*clk_get_rate)(struct tmio_sd_priv *);
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};
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};
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