mirror of
https://xff.cz/git/u-boot/
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ddr: marvell: a38x: Add support for DDR4 from Marvell mv-ddr-marvell repository
This syncs drivers/ddr/marvell/a38x/ with the master branch of repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
up to the commit "mv_ddr: a3700: Use the right size for memset to not overflow"
d5acc10c287e40cc2feeb28710b92e45c93c702c
This patch was created by following steps:
1. Replace all a38x files in U-Boot tree by files from upstream github
Marvell mv-ddr-marvell repository.
2. Run following command to omit portions not relevant for a38x, ddr3, and ddr4:
files=drivers/ddr/marvell/a38x/*
unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_APN806 \
-UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \
-UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DCONFIG_ARMADA_38X -UCONFIG_ARMADA_39X \
-UCONFIG_64BIT $files
3. Manually change license to SPDX-License-Identifier
(upstream license in upstream github repository contains long license
texts and U-Boot is using just SPDX-License-Identifier.
After applying this patch, a38x, ddr3, and ddr4 code in upstream Marvell github
repository and in U-Boot would be fully identical. So in future applying
above steps could be used to sync code again.
The only change in this patch are:
1. Some fixes with include files.
2. Some function return and basic type defines changes in
mv_ddr_plat.c (to correct Marvell bug).
3. Remove of dead code in newly copied files (as a result of the
filter script stripping out everything other than a38x, dd3, and ddr4).
Reference:
"ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository"
107c3391b9
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Tony Dinh
Stefan Roese
@@ -30,6 +30,12 @@ u8 debug_training_hw_alg = DEBUG_LEVEL_ERROR;
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u8 debug_training_access = DEBUG_LEVEL_ERROR;
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u8 debug_training_device = DEBUG_LEVEL_ERROR;
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#if defined(CONFIG_DDR4)
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u8 debug_tap_tuning = DEBUG_LEVEL_ERROR;
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u8 debug_calibration = DEBUG_LEVEL_ERROR;
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u8 debug_ddr4_centralization = DEBUG_LEVEL_ERROR;
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u8 debug_dm_tuning = DEBUG_LEVEL_ERROR;
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#endif /* CONFIG_DDR4 */
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void mv_ddr_user_log_level_set(enum ddr_lib_debug_block block)
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{
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@@ -70,6 +76,17 @@ void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level)
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else
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is_reg_dump = 0;
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break;
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#if defined(CONFIG_DDR4)
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case DEBUG_TAP_TUNING_ENGINE:
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debug_tap_tuning = level;
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break;
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case DEBUG_BLOCK_CALIBRATION:
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debug_calibration = level;
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break;
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case DEBUG_BLOCK_DDR4_CENTRALIZATION:
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debug_ddr4_centralization = level;
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break;
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#endif /* CONFIG_DDR4 */
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case DEBUG_BLOCK_ALL:
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default:
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debug_training_static = level;
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@@ -80,6 +97,11 @@ void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level)
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debug_training_hw_alg = level;
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debug_training_access = level;
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debug_training_device = level;
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#if defined(CONFIG_DDR4)
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debug_tap_tuning = level;
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debug_calibration = level;
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debug_ddr4_centralization = level;
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#endif /* CONFIG_DDR4 */
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}
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}
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#endif /* SILENT_LIB */
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@@ -209,11 +231,13 @@ static char *convert_freq(enum mv_ddr_freq freq)
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case MV_DDR_FREQ_LOW_FREQ:
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return "MV_DDR_FREQ_LOW_FREQ";
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#if !defined(CONFIG_DDR4)
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case MV_DDR_FREQ_400:
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return "400";
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case MV_DDR_FREQ_533:
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return "533";
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#endif /* CONFIG_DDR4 */
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case MV_DDR_FREQ_667:
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return "667";
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@@ -227,6 +251,7 @@ static char *convert_freq(enum mv_ddr_freq freq)
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case MV_DDR_FREQ_1066:
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return "1066";
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#if !defined(CONFIG_DDR4)
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case MV_DDR_FREQ_311:
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return "311";
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@@ -247,6 +272,7 @@ static char *convert_freq(enum mv_ddr_freq freq)
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case MV_DDR_FREQ_1000:
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return "MV_DDR_FREQ_1000";
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#endif /* CONFIG_DDR4 */
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default:
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return "Unknown Frequency";
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@@ -463,6 +489,7 @@ int ddr3_tip_print_log(u32 dev_num, u32 mem_addr)
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(training_result[WRITE_LEVELING_TF]
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[if_id])));
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}
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#if !defined(CONFIG_DDR4)
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if (mask_tune_func & READ_LEVELING_TF_MASK_BIT) {
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DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
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("\tRL TF: %s\n",
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@@ -470,6 +497,7 @@ int ddr3_tip_print_log(u32 dev_num, u32 mem_addr)
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(training_result[READ_LEVELING_TF]
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[if_id])));
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}
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#endif /* CONFIG_DDR4 */
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if (mask_tune_func & WRITE_LEVELING_SUPP_TF_MASK_BIT) {
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DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
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("\tWL TF Supp: %s\n",
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@@ -499,6 +527,43 @@ int ddr3_tip_print_log(u32 dev_num, u32 mem_addr)
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(training_result[CENTRALIZATION_TX]
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[if_id])));
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}
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#if defined(CONFIG_DDR4)
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if (mask_tune_func & SW_READ_LEVELING_MASK_BIT) {
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DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
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("\tSW RL TF: %s\n",
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ddr3_tip_convert_tune_result
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(training_result[SW_READ_LEVELING]
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[if_id])));
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}
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if (mask_tune_func & RECEIVER_CALIBRATION_MASK_BIT) {
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DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
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("\tRX CAL: %s\n",
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ddr3_tip_convert_tune_result
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(training_result[RECEIVER_CALIBRATION]
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[if_id])));
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}
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if (mask_tune_func & WL_PHASE_CORRECTION_MASK_BIT) {
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DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
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("\tWL PHASE CORRECT: %s\n",
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ddr3_tip_convert_tune_result
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(training_result[WL_PHASE_CORRECTION]
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[if_id])));
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}
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if (mask_tune_func & DQ_VREF_CALIBRATION_MASK_BIT) {
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DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
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("\tDQ VREF CAL: %s\n",
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ddr3_tip_convert_tune_result
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(training_result[DQ_VREF_CALIBRATION]
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[if_id])));
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}
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if (mask_tune_func & DQ_MAPPING_MASK_BIT) {
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DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
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("\tDQ MAP: %s\n",
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ddr3_tip_convert_tune_result
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(training_result[DQ_MAPPING]
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[if_id])));
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}
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#endif /* CONFIG_DDR4 */
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}
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return MV_OK;
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@@ -512,6 +577,9 @@ int ddr3_tip_print_stability_log(u32 dev_num)
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{
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u8 if_id = 0, csindex = 0, bus_id = 0, idx = 0;
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u32 reg_data;
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#if defined(CONFIG_DDR4)
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u32 reg_data1;
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#endif /* CONFIG_DDR4 */
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u32 read_data[MAX_INTERFACE_NUM];
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unsigned int max_cs = mv_ddr_cs_num_get();
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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@@ -524,7 +592,13 @@ int ddr3_tip_print_stability_log(u32 dev_num)
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printf("CS%d , ", csindex);
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printf("\n");
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VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
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#if defined(CONFIG_DDR4)
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printf("DminTx, AreaTx, DminRx, AreaRx, WL_tot, WL_ADLL, WL_PH, RL_Tot, RL_ADLL, RL_PH, RL_Smp, CenTx, CenRx, Vref, DQVref,");
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for (idx = 0; idx < 11; idx++)
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printf("DC-Pad%d,", idx);
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#else /* CONFIG_DDR4 */
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printf("VWTx, VWRx, WL_tot, WL_ADLL, WL_PH, RL_Tot, RL_ADLL, RL_PH, RL_Smp, Cen_tx, Cen_rx, Vref, DQVref,");
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#endif /* CONFIG_DDR4 */
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printf("\t\t");
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for (idx = 0; idx < 11; idx++)
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printf("PBSTx-Pad%d,", idx);
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@@ -565,6 +639,40 @@ int ddr3_tip_print_stability_log(u32 dev_num)
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for (bus_id = 0; bus_id < MAX_BUS_NUM; bus_id++) {
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printf("\n");
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VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
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#if defined(CONFIG_DDR4)
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/* DminTx, areaTX */
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ddr3_tip_bus_read(dev_num, if_id,
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ACCESS_TYPE_UNICAST,
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bus_id, DDR_PHY_DATA,
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RESULT_PHY_REG +
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csindex, ®_data);
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ddr3_tip_bus_read(dev_num, if_id,
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ACCESS_TYPE_UNICAST,
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dmin_phy_reg_table
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[csindex * 5 + bus_id][0],
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DDR_PHY_CONTROL,
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dmin_phy_reg_table
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[csindex * 5 + bus_id][1],
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®_data1);
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printf("%d,%d,", 2 * (reg_data1 & 0xFF),
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reg_data);
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/* DminRx, areaRX */
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ddr3_tip_bus_read(dev_num, if_id,
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ACCESS_TYPE_UNICAST,
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bus_id, DDR_PHY_DATA,
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RESULT_PHY_REG +
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csindex + 4, ®_data);
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ddr3_tip_bus_read(dev_num, if_id,
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ACCESS_TYPE_UNICAST,
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dmin_phy_reg_table
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[csindex * 5 + bus_id][0],
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DDR_PHY_CONTROL,
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dmin_phy_reg_table
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[csindex * 5 + bus_id][1],
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®_data1);
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printf("%d,%d,", 2 * (reg_data1 >> 8),
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reg_data);
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#else /* CONFIG_DDR4 */
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ddr3_tip_bus_read(dev_num, if_id,
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ACCESS_TYPE_UNICAST,
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bus_id, DDR_PHY_DATA,
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@@ -572,6 +680,7 @@ int ddr3_tip_print_stability_log(u32 dev_num)
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csindex, ®_data);
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printf("%d,%d,", (reg_data & 0x1f),
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((reg_data & 0x3e0) >> 5));
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#endif /* CONFIG_DDR4 */
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/* WL */
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ddr3_tip_bus_read(dev_num, if_id,
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ACCESS_TYPE_UNICAST,
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@@ -628,6 +737,17 @@ int ddr3_tip_print_stability_log(u32 dev_num)
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/* DQVref */
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/* Need to add the Read Function from device */
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printf("%d,", 0);
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#if defined(CONFIG_DDR4)
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printf("\t\t");
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for (idx = 0; idx < 11; idx++) {
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ddr3_tip_bus_read(dev_num, if_id,
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ACCESS_TYPE_UNICAST,
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bus_id, DDR_PHY_DATA,
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0xd0 + 12 * csindex +
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idx, ®_data);
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printf("%d,", (reg_data & 0x3f));
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}
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#endif /* CONFIG_DDR4 */
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printf("\t\t");
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for (idx = 0; idx < 11; idx++) {
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ddr3_tip_bus_read(dev_num, if_id,
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