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Merge branch 'master' of git://git.denx.de/u-boot into master

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* 'master' of git://git.denx.de/u-boot: (40 commits)
  configs: powerpc: Don't set CONFIG_ENV_ADDR for QorIQ SPIFLASH
  disk: typo Terra Bytes
  doc/build/gcc.rst: add missing apt-get *install*
  gpio/mpc83xx_spisel_boot.c: include log.h
  spi: mpc8xxx_spi.c: fix cs activate/deactivate
  Prepare v2020.10-rc5
  configs: Resync with savedefconfig
  x86: acpi: Add memset to initialize SPCR table
  x86: acpi: Fix calculation of DSDT length
  x86: fsp: Replace e-mmc with emmc in devicetree bindings
  cmd: acpi: Print revisions in hex format
  x86: edison: Move config SYS_MALLOC_LEN to Kconfig
  efi: change 'env -e -i' usage syntax
  efi_selftest: check for RISC-V boot-hartid in FDT
  efi_selftest: rework device tree test
  efi_memory: refine overlap_only_ram description
  rng: stm32mp1: use log() instead of printf()
  cmd: mem: fix range of bitflip test
  configs: bcmstb: Disable networking support
  fs/squashfs: Fix Coverity Scan defects
  ...
This commit is contained in:
Ondrej Jirman
2020-09-23 14:18:43 +02:00
parent 4506bbd57b 5949f36f08
commit 51c90097b7
66 changed files with 200 additions and 139 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/dts/fsl-imx8qm-apalis.dts
View File

@@ -12,8 +12,8 @@
#include "fsl-imx8qm-apalis-u-boot.dtsi"
/ {
model = "Toradex Apalis iMX8QM";
compatible = "toradex,apalis-imx8qm", "fsl,imx8qm";
model = "Toradex Apalis iMX8";
compatible = "toradex,apalis-imx8", "fsl,imx8qm";
chosen {
bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200";
@@ -38,7 +38,7 @@
<&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>,
<&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>;
apalis-imx8qm {
apalis-imx8 {
pinctrl_gpio12: gpio12grp {
fsl,pins = <
/* Apalis GPIO1 */

6
arch/arm/dts/fsl-imx8qxp-colibri.dts
View File

@@ -9,8 +9,8 @@
#include "fsl-imx8qxp-colibri-u-boot.dtsi"
/ {
model = "Toradex Colibri iMX8QXP";
compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp";
model = "Toradex Colibri iMX8X";
compatible = "toradex,colibri-imx8x", "fsl,imx8qxp";
chosen {
bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200";
@@ -32,7 +32,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>;
colibri-imx8qxp {
colibri-imx8x {
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
SC_P_UART0_RX_ADMA_UART0_RX 0x06000020

2
arch/arm/include/asm/arch-imx/cpu.h
View File

@@ -41,9 +41,7 @@
#define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */
#define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */
#define MXC_CPU_IMX8MP 0x182/* dummy ID */
#define MXC_CPU_IMX8MP7 0x183 /* dummy ID */
#define MXC_CPU_IMX8MP6 0x184 /* dummy ID */
#define MXC_CPU_IMX8MP5 0x185 /* dummy ID */
#define MXC_CPU_IMX8MPL 0x186 /* dummy ID */
#define MXC_CPU_IMX8MPD 0x187 /* dummy ID */
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */

10
arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
View File

@@ -316,7 +316,7 @@ enum clk_src_index {
#define FRAC_PLL_LOCK_MASK BIT(31)
#define FRAC_PLL_CLKE_MASK BIT(21)
#define FRAC_PLL_PD_MASK BIT(19)
#define FRAC_PLL_REFCLK_SEL_MASK BIT(16)
#define FRAC_PLL_REFCLK_SEL_MASK (0x3 << 16)
#define FRAC_PLL_LOCK_SEL_MASK BIT(15)
#define FRAC_PLL_BYPASS_MASK BIT(14)
#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13)
@@ -358,10 +358,10 @@ enum clk_src_index {
#define SSCG_PLL_LOCK_SEL_MASK BIT(3)
#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2)
#define SSCG_PLL_REFCLK_SEL_MASK 0x3
#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16)
#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16)
#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)
#define SSCG_PLL_REFCLK_SEL_OSC_25M (0)
#define SSCG_PLL_REFCLK_SEL_OSC_27M (1)
#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2)
#define SSCG_PLL_REFCLK_SEL_CLK_PN (3)
#define SSCG_PLL_SSDS_MASK BIT(8)
#define SSCG_PLL_SSMD_MASK (0x7 << 5)

2
arch/arm/include/asm/arch-mx7/crm_regs.h
View File

@@ -57,7 +57,7 @@ struct mxc_ccm_reg {
uint32_t reserved_0[4092];
struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */
uint32_t reserved_1[3332];
struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */
struct mxc_ccm_root_slice root[125]; /* offset 0x8000 */
};

5
arch/arm/include/asm/mach-imx/sys_proto.h
View File

@@ -67,13 +67,10 @@ struct bd_info;
#define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
#define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
#define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \
is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP7) || \
is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MP5))
is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6))
#define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))
#define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL))
#define is_imx8mp7() (is_cpu_type(MXC_CPU_IMX8MP7))
#define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6))
#define is_imx8mp5() (is_cpu_type(MXC_CPU_IMX8MP5))
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))

4
arch/arm/mach-imx/cpu.c
View File

@@ -102,12 +102,8 @@ const char *get_imx_type(u32 imxtype)
return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
case MXC_CPU_IMX8MPL:
return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
case MXC_CPU_IMX8MP7:
return "8MP[7]"; /* Quad-core version of the imx8mp, VPU fused */
case MXC_CPU_IMX8MP6:
return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
case MXC_CPU_IMX8MP5:
return "8MP[5]"; /* Quad-core version of the imx8mp, ISP fused */
case MXC_CPU_IMX8MN:
return "8MNano Quad"; /* Quad-core version */
case MXC_CPU_IMX8MND:

1
arch/arm/mach-imx/imx8m/clock_imx8mm.c
View File

@@ -360,6 +360,7 @@ void init_clk_ecspi(u32 index)
clock_enable(CCGR_ECSPI2, 0);
clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_ECSPI2, 1);
return;
case 2:
clock_enable(CCGR_ECSPI3, 0);
clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));

12
arch/arm/mach-imx/imx8m/soc.c
View File

@@ -343,12 +343,8 @@ static u32 get_cpu_variant_type(u32 type)
switch (flag) {
case 7:
return MXC_CPU_IMX8MPL;
case 6:
return MXC_CPU_IMX8MP5;
case 2:
return MXC_CPU_IMX8MP6;
case 1:
return MXC_CPU_IMX8MP7;
default:
break;
}
@@ -889,16 +885,16 @@ usb_modify_speed:
disable_cpu_nodes(blob, 3);
#elif defined(CONFIG_IMX8MP)
if (is_imx8mpl() || is_imx8mp7())
if (is_imx8mpl())
disable_vpu_nodes(blob);
if (is_imx8mpl() || is_imx8mp6() || is_imx8mp5())
if (is_imx8mpl() || is_imx8mp6())
disable_npu_nodes(blob);
if (is_imx8mpl() || is_imx8mp5())
if (is_imx8mpl())
disable_isp_nodes(blob);
if (is_imx8mpl() || is_imx8mp7() || is_imx8mp6() || is_imx8mp5())
if (is_imx8mpl() || is_imx8mp6())
disable_dsp_nodes(blob);
if (is_imx8mpd())

15
arch/arm/mach-imx/mx6/ddr.c
View File

@@ -250,16 +250,31 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
static void mmdc_set_sdqs(bool set)
{
struct mx6sdl_iomux_ddr_regs *mx6sdl_ddr_iomux =
(struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux =
(struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
(struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
struct mx6sl_iomux_ddr_regs *mx6sl_ddr_iomux =
(struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
struct mx6ul_iomux_ddr_regs *mx6ul_ddr_iomux =
(struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
int i, sdqs_cnt;
u32 sdqs;
if (is_mx6sx()) {
sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0);
sdqs_cnt = 2;
} else if (is_mx6sl()) {
sdqs = (u32)(&mx6sl_ddr_iomux->dram_sdqs0);
sdqs_cnt = 2;
} else if (is_mx6ul() || is_mx6ull()) {
sdqs = (u32)(&mx6ul_ddr_iomux->dram_sdqs0);
sdqs_cnt = 2;
} else if (is_mx6sdl()) {
sdqs = (u32)(&mx6sdl_ddr_iomux->dram_sdqs0);
sdqs_cnt = 8;
} else { /* MX6DQ */
sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0);
sdqs_cnt = 8;

6
arch/x86/cpu/apollolake/fsp_bindings.c
View File

@@ -555,7 +555,7 @@ const struct fsp_binding fsp_m_bindings[] = {
}, {
.type = FSP_UINT8,
.offset = offsetof(struct fsp_m_config, e_mmc_trace_len),
.propname = "fspm,e-mmc-trace-len",
.propname = "fspm,emmc-trace-len",
}, {
.type = FSP_UINT8,
.offset = offsetof(struct fsp_m_config, skip_cse_rbp),
@@ -1465,11 +1465,11 @@ const struct fsp_binding fsp_s_bindings[] = {
}, {
.type = FSP_UINT8,
.offset = offsetof(struct fsp_s_config, e_mmc_enabled),
.propname = "fsps,e-mmc-enabled",
.propname = "fsps,emmc-enabled",
}, {
.type = FSP_UINT8,
.offset = offsetof(struct fsp_s_config, e_mmc_host_max_speed),
.propname = "fsps,e-mmc-host-max-speed",
.propname = "fsps,emmc-host-max-speed",
}, {
.type = FSP_UINT8,
.offset = offsetof(struct fsp_s_config, ufs_enabled),

6
arch/x86/lib/acpi_table.c
View File

@@ -252,6 +252,8 @@ static void acpi_create_spcr(struct acpi_spcr *spcr)
int space_id;
int ret = -ENODEV;
memset((void *)spcr, 0, sizeof(struct acpi_spcr));
/* Fill out header fields */
acpi_fill_header(header, "SPCR");
header->length = sizeof(struct acpi_spcr);
@@ -427,7 +429,7 @@ ulong write_acpi_tables(ulong start_addr)
(char *)&AmlCode + sizeof(struct acpi_table_header),
dsdt->length - sizeof(struct acpi_table_header));
acpi_inc_align(ctx, dsdt->length - sizeof(struct acpi_table_header));
acpi_inc(ctx, dsdt->length - sizeof(struct acpi_table_header));
/* Pack GNVS into the ACPI table area */
for (i = 0; i < dsdt->length; i++) {
@@ -450,6 +452,8 @@ ulong write_acpi_tables(ulong start_addr)
dsdt->checksum = 0;
dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length);
acpi_align(ctx);
/*
* Fill in platform-specific global NVS variables. If this fails we
* cannot return the error but this should only happen while debugging.