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8xx, icache: enabling ICache not before running from RAM

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with the new CONFIG_SYS_DELAYED_ICACHE config option, ICache
is not enabled before code runs from RAM.

Signed-off-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Heiko Schocher
2009-03-12 07:37:15 +01:00
committed by Wolfgang Denk
parent cabf7b9c83
commit 506f391888
6 changed files with 16 additions and 3 deletions
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5
README
View File

@@ -318,6 +318,11 @@ The following options need to be configured:
that this requires a (stable) reference clock (32 kHz that this requires a (stable) reference clock (32 kHz
RTC clock or CONFIG_SYS_8XX_XIN) RTC clock or CONFIG_SYS_8XX_XIN)
CONFIG_SYS_DELAYED_ICACHE
Define this option if you want to enable the
ICache only when Code runs from RAM.
- Intel Monahans options: - Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO

2
cpu/mpc8xx/start.S
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@@ -142,7 +142,7 @@ boot_warm:
lis r3, IDC_DISABLE@h /* Disable data cache */ lis r3, IDC_DISABLE@h /* Disable data cache */
mtspr DC_CST, r3 mtspr DC_CST, r3
#if !(defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM)) #if !defined(CONFIG_SYS_DELAYED_ICACHE)
/* On IP860 and PCU E, /* On IP860 and PCU E,
* we cannot enable IC yet * we cannot enable IC yet
*/ */

3
include/configs/FLAGADM.h
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@@ -173,6 +173,9 @@
#if defined(CONFIG_CMD_KGDB) #if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif #endif
#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
* running in RAM.
*/
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9 * SYPCR - System Protection Control 11-9

3
include/configs/IP860.h
View File

@@ -209,6 +209,9 @@
#if defined(CONFIG_CMD_KGDB) #if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif #endif
#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
* running in RAM.
*/
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9 * SYPCR - System Protection Control 11-9

3
include/configs/pcu_e.h
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@@ -246,6 +246,9 @@
*/ */
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
* running in RAM.
*/
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9 * SYPCR - System Protection Control 11-9

3
lib_ppc/board.c
View File

@@ -736,8 +736,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
WATCHDOG_RESET(); WATCHDOG_RESET();
#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || \ #if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83XX)
defined (CONFIG_FLAGADM) || defined(CONFIG_MPC83XX)
icache_enable (); /* it's time to enable the instruction cache */ icache_enable (); /* it's time to enable the instruction cache */
#endif #endif