From b277a95c6ece59392e77e475551b909e392229c0 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Wed, 20 Apr 2022 09:14:05 +0800 Subject: [PATCH 1/8] riscv: ae350: Fix OF_BOARD boot failure Enable OF_HAS_PRIOR_STAGE for ae350 boards with OF_BOARD Fixes: 239d22c79520 ("fdt: Enable OF_HAS_PRIOR_STAGE for most boards with OF_BOARD") Signed-off-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang --- board/AndesTech/ax25-ae350/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig index e50f505a2b..91eec35f47 100644 --- a/board/AndesTech/ax25-ae350/Kconfig +++ b/board/AndesTech/ax25-ae350/Kconfig @@ -35,5 +35,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SMP imply SPL_RAM_SUPPORT imply SPL_RAM_DEVICE + imply OF_HAS_PRIOR_STAGE endif From 9da5ced5c5e4b83f696f136fa78db0a9e0a6326a Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Wed, 20 Apr 2022 09:23:51 +0800 Subject: [PATCH 2/8] riscv: ae350: Fix OF_BOARD boot failure Disable BINMAN_FDT for ae350 boards which don't actually use it. Fixes: 836eac7c6fe3 ("fdt: Make OF_BOARD a bool option") Signed-off-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang --- configs/ae350_rv32_spl_defconfig | 1 + configs/ae350_rv32_spl_xip_defconfig | 1 + configs/ae350_rv64_spl_defconfig | 1 + configs/ae350_rv64_spl_xip_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 3a646e4222..8406eb5c33 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BINMAN_FDT is not set CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 4ac90fbf73..5db1a7cbd7 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BINMAN_FDT is not set CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 1e682df800..6abc9c1388 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BINMAN_FDT is not set CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 4f17d5ca1e..f3ace4453f 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BINMAN_FDT is not set CONFIG_SYS_PROMPT="RISC-V # " CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y From 73872eb05aee1173c145fe70c2ace42d5245af3e Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 7 May 2022 14:42:10 +0200 Subject: [PATCH 3/8] cmd/sbi: add implementation ID 6 - Coffer The sbi command displays the ID of the implementation of the RISC-V Supervisor Binary Interface Specification. A new ID for Coffer has recently been added. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- cmd/riscv/sbi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index 8fc8ab0ac5..ee11e0f88e 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -26,6 +26,7 @@ static struct sbi_imp implementations[] = { { 3, "KVM" }, { 4, "RustSBI" }, { 5, "Diosix" }, + { 6, "Coffer" }, }; static struct sbi_ext extensions[] = { From 8ac37b461c90987f02f011d17145f8d6ff484bc7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 May 2022 12:54:01 +0200 Subject: [PATCH 4/8] riscv: remove CONFIG_ARCH_MAP_SYSMEM from io.h Commit ba1ed5b022c6 ("Convert CONFIG_ARCH_MAP_SYSMEM to Kconfig") clearly defined that this option is available for SANDBOX (was also for already removed NDS32). That's why there is no way how this code can be enabled with current Kconfig layout for riscv. Based on this removing this code. Signed-off-by: Michal Simek Reviewed-by: Bin Meng --- arch/riscv/include/asm/io.h | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index fc39bb2c70..431cf1389d 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -17,28 +17,6 @@ static inline void sync(void) { } -#ifdef CONFIG_ARCH_MAP_SYSMEM -static inline void *map_sysmem(phys_addr_t paddr, unsigned long len) -{ - if (paddr < PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE) - paddr = paddr | 0x40000000; - return (void *)(uintptr_t)paddr; -} - -static inline void *unmap_sysmem(const void *vaddr) -{ - phys_addr_t paddr = (phys_addr_t)vaddr; - - paddr = paddr & ~0x40000000; - return (void *)(uintptr_t)paddr; -} - -static inline phys_addr_t map_to_sysmem(const void *ptr) -{ - return (phys_addr_t)(uintptr_t)ptr; -} -#endif - /* * Generic virtual read/write. Note that we don't support half-word * read/writes. We define __arch_*[bl] here, and leave __arch_*w From d5af15bf515f04f31fde22cab27feae84039e4d0 Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Thu, 19 May 2022 16:43:31 +0800 Subject: [PATCH 5/8] riscv: Clean up asm/io.h Clean up asm/io.h by - removing commented code - removing outdated comments - removing unused definitions (for mem_isa, mem_pci) This massively improves the readability of the file. Suggested by commits: 7ab2e47d27c9 ("arm: Clean up asm/io.h") 909d0399a519 ("ARM: asm/io.h: kill off confusing #ifdef __mem_pci block") Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Bin Meng --- arch/riscv/include/asm/io.h | 116 ------------------------------------ 1 file changed, 116 deletions(-) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 431cf1389d..220266e76f 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -7,8 +7,6 @@ #ifndef __ASM_RISCV_IO_H #define __ASM_RISCV_IO_H -#ifdef __KERNEL__ - #include #include #include @@ -17,11 +15,6 @@ static inline void sync(void) { } -/* - * Generic virtual read/write. Note that we don't support half-word - * read/writes. We define __arch_*[bl] here, and leave __arch_*w - * to the architecture specific code. - */ #define __arch_getb(a) (*(volatile unsigned char *)(a)) #define __arch_getw(a) (*(volatile unsigned short *)(a)) #define __arch_getl(a) (*(volatile unsigned int *)(a)) @@ -330,115 +323,6 @@ static inline void writesl(unsigned int *addr, const void *data, int longlen) #define insw_p(port, to, len) insw(port, to, len) #define insl_p(port, to, len) insl(port, to, len) -/* - * DMA-consistent mapping functions. These allocate/free a region of - * uncached, unwrite-buffered mapped memory space for use with DMA - * devices. This is the "generic" version. The PCI specific version - * is in pci.h - */ - -/* - * String version of IO memory access ops: - */ - -/* - * If this architecture has PCI memory IO, then define the read/write - * macros. These should only be used with the cookie passed from - * ioremap. - */ -#ifdef __mem_pci - -#define readb(c) ({ unsigned int __v = \ - __raw_readb(__mem_pci(c)); __v; }) -#define readw(c) ({ unsigned int __v = \ - le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c) ({ unsigned int __v = \ - le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) - -#define writeb(v, c) __raw_writeb(v, __mem_pci(c)) -#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c)) -#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c)) - -#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l)) -#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l)) -#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l)) - -#define eth_io_copy_and_sum(s, c, l, b) \ - eth_copy_and_sum((s), __mem_pci(c), (l), (b)) - -static inline int check_signature(ulong io_addr, const uchar *s, int len) -{ - int retval = 0; - - do { - if (readb(io_addr) != *s) - goto out; - io_addr++; - s++; - len--; - } while (len); - retval = 1; -out: - return retval; -} -#endif /* __mem_pci */ - -/* - * If this architecture has ISA IO, then define the isa_read/isa_write - * macros. - */ -#ifdef __mem_isa - -#define isa_readb(addr) __raw_readb(__mem_isa(addr)) -#define isa_readw(addr) __raw_readw(__mem_isa(addr)) -#define isa_readl(addr) __raw_readl(__mem_isa(addr)) -#define isa_writeb(val, addr) __raw_writeb(val, __mem_isa(addr)) -#define isa_writew(val, addr) __raw_writew(val, __mem_isa(addr)) -#define isa_writel(val, addr) __raw_writel(val, __mem_isa(addr)) -#define isa_memset_io(a, b, c) _memset_io(__mem_isa(a), (b), (c)) -#define isa_memcpy_fromio(a, b, c) _memcpy_fromio((a), __mem_isa(b), (c)) -#define isa_memcpy_toio(a, b, c) _memcpy_toio(__mem_isa((a)), (b), (c)) - -#define isa_eth_io_copy_and_sum(a, b, c, d) \ - eth_copy_and_sum((a), __mem_isa(b), (c), (d)) - -static inline int -isa_check_signature(ulong io_addr, const uchar *s, int len) -{ - int retval = 0; - - do { - if (isa_readb(io_addr) != *s) - goto out; - io_addr++; - s++; - len--; - } while (len); - retval = 1; -out: - return retval; -} - -#else /* __mem_isa */ - -#define isa_readb(addr) (__readwrite_bug("isa_readb"), 0) -#define isa_readw(addr) (__readwrite_bug("isa_readw"), 0) -#define isa_readl(addr) (__readwrite_bug("isa_readl"), 0) -#define isa_writeb(val, addr) __readwrite_bug("isa_writeb") -#define isa_writew(val, addr) __readwrite_bug("isa_writew") -#define isa_writel(val, addr) __readwrite_bug("isa_writel") -#define isa_memset_io(a, b, c) __readwrite_bug("isa_memset_io") -#define isa_memcpy_fromio(a, b, c) __readwrite_bug("isa_memcpy_fromio") -#define isa_memcpy_toio(a, b, c) __readwrite_bug("isa_memcpy_toio") - -#define isa_eth_io_copy_and_sum(a, b, c, d) \ - __readwrite_bug("isa_eth_io_copy_and_sum") - -#define isa_check_signature(io, sig, len) (0) - -#endif /* __mem_isa */ -#endif /* __KERNEL__ */ - #include #endif /* __ASM_RISCV_IO_H */ From b84d24c3c5963a9fd130c073d504f8d80b5d1a9c Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Tue, 24 May 2022 12:31:12 +0800 Subject: [PATCH 6/8] riscv: sifive: unmatched: Adjust for big ramdisk image Move kernel_comp_addr_r to an address that comes before the ramdisk image, since the decompressed kernel size is known to us. This way we can allow big ramdisk image to be loaded. Signed-off-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang --- include/configs/sifive-unmatched.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index 087764666b..fa734a66be 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -56,12 +56,12 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x84000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "scriptaddr=0x88100000\0" \ - "pxefile_addr_r=0x88200000\0" \ - "ramdisk_addr_r=0x88300000\0" \ - "kernel_comp_addr_r=0x90000000\0" \ + "kernel_comp_addr_r=0x88000000\0" \ "kernel_comp_size=0x4000000\0" \ + "fdt_addr_r=0x8c000000\0" \ + "scriptaddr=0x8c100000\0" \ + "pxefile_addr_r=0x8c200000\0" \ + "ramdisk_addr_r=0x8c300000\0" \ "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \ "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ From ce78c4cd6e8f5cd5e2322a026cc2d333f500781b Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Tue, 24 May 2022 12:31:13 +0800 Subject: [PATCH 7/8] riscv: sifive: unleashed: Set kernel_comp_addr_r for compressed kernel Set kernel_comp_addr_r and kernel_comp_size for compressed kernel. Adjust existing addresses for ramdisk, so that kernel_comp_addr_r comes before the ramdisk image, since the decompressed kernel size is known to us. This way we can allow big ramdisk image to be loaded. Update unleashed.rst to remove the manual environment configuration for compressed kernel boot. Signed-off-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang --- doc/board/sifive/unleashed.rst | 2 -- include/configs/sifive-unleashed.h | 10 ++++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/doc/board/sifive/unleashed.rst b/doc/board/sifive/unleashed.rst index c8a62068a7..ce38b701d7 100644 --- a/doc/board/sifive/unleashed.rst +++ b/doc/board/sifive/unleashed.rst @@ -216,8 +216,6 @@ Or if you want to use a compressed kernel image file such as Image.gz 1.2 MiB/s done Bytes transferred = 4809458 (4962f2 hex) - =>setenv kernel_comp_addr_r 0x90000000 - =>setenv kernel_comp_size 0x500000 By this time, correct kernel image is loaded and required environment variables are set. You can proceed to load the ramdisk and device tree from the tftp server diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index 920f3140f6..96e2eb6798 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -61,12 +61,14 @@ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr_r=0x84000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "scriptaddr=0x88100000\0" \ + "kernel_comp_addr_r=0x88000000\0" \ + "kernel_comp_size=0x4000000\0" \ + "fdt_addr_r=0x8c000000\0" \ + "scriptaddr=0x8c100000\0" \ "script_offset_f=0x1fff000\0" \ "script_size_f=0x1000\0" \ - "pxefile_addr_r=0x88200000\0" \ - "ramdisk_addr_r=0x88300000\0" \ + "pxefile_addr_r=0x8c200000\0" \ + "ramdisk_addr_r=0x8c300000\0" \ "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \ "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ From c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Tue, 24 May 2022 12:31:14 +0800 Subject: [PATCH 8/8] riscv: qemu: Set kernel_comp_addr_r for compressed kernel Set kernel_comp_addr_r and kernel_comp_size for compressed kernel. Adjust existing addresses for ramdisk, so that kernel_comp_addr_r comes before the ramdisk image, since the decompressed kernel size is known to us. This way we can allow big ramdisk image to be loaded. Signed-off-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang --- include/configs/qemu-riscv.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index 618c3b63d4..f462895fb5 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -54,10 +54,12 @@ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr_r=0x84000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "scriptaddr=0x88100000\0" \ - "pxefile_addr_r=0x88200000\0" \ - "ramdisk_addr_r=0x88300000\0" \ + "kernel_comp_addr_r=0x88000000\0" \ + "kernel_comp_size=0x4000000\0" \ + "fdt_addr_r=0x8c000000\0" \ + "scriptaddr=0x8c100000\0" \ + "pxefile_addr_r=0x8c200000\0" \ + "ramdisk_addr_r=0x8c300000\0" \ BOOTENV #endif