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driver/ddr: Change Freescale ARM DDR driver to support both big and little endian

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Initially it was believed the DDR controller on Freescale ARM would have
big endian. But some platform will have little endian.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun
2014-02-10 13:59:42 -08:00
committed by Tom Rini
parent 9c89614d3f
commit 4e5b1bd0df
5 changed files with 74 additions and 58 deletions
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9
include/fsl_ddr.h
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@@ -14,6 +14,14 @@
#include <common_timing_params.h>
#ifdef CONFIG_SYS_FSL_DDR_LE
#define ddr_in32(a) in_le32(a)
#define ddr_out32(a, v) out_le32(a, v)
#else
#define ddr_in32(a) in_be32(a)
#define ddr_out32(a, v) out_be32(a, v)
#endif
#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
/*
* Bind the main DDR setup driver's generic names
@@ -93,6 +101,7 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
void board_add_ram_info(int use_default);
/* processor specific function */
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,