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pci: pci-uclass: Add multi entry support for memory regions

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Enable PCI memory regions in ranges property to be of multiple entry.
This helps to add support for SoC's like OcteonTX/TX2 where every
peripheral is on PCI bus.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Suneel Garapati
2019-10-19 17:10:20 -07:00
committed by Stefan Roese
parent bc30140d20
commit 4cf56ec07f
6 changed files with 43 additions and 5 deletions
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22
test/dm/pci.c
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@@ -354,3 +354,25 @@ static int dm_test_pci_on_bus(struct unit_test_state *uts)
return 0;
}
DM_TEST(dm_test_pci_on_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
/*
* Test support for multiple memory regions enabled via
* CONFIG_PCI_REGION_MULTI_ENTRY. When this feature is not enabled,
* only the last region of one type is stored. In this test-case,
* we have 2 memory regions, the first at 0x3000.0000 and the 2nd
* at 0x3100.0000. A correct test results now in BAR1 located at
* 0x3000.0000.
*/
static int dm_test_pci_region_multi(struct unit_test_state *uts)
{
struct udevice *dev;
ulong mem_addr;
/* Test memory BAR1 on bus#1 */
ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &dev));
mem_addr = dm_pci_read_bar32(dev, 1);
ut_asserteq(mem_addr, 0x30000000);
return 0;
}
DM_TEST(dm_test_pci_region_multi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);