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pci: pci-uclass: Add multi entry support for memory regions
Enable PCI memory regions in ranges property to be of multiple entry. This helps to add support for SoC's like OcteonTX/TX2 where every peripheral is on PCI bus. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
committed by
Stefan Roese
parent
bc30140d20
commit
4cf56ec07f
@@ -666,8 +666,9 @@
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
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0x01000000 0 0x40000000 0x40000000 0 0x2000>;
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ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
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0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
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0x01000000 0 0x40000000 0x40000000 0 0x2000>;
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sandbox,dev-info = <0x08 0x00 0x1234 0x5678
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0x0c 0x00 0x1234 0x5678
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0x10 0x00 0x1234 0x5678>;
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