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azure/gitlab/travis: Add RISC-V SPL testing

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This adds QEMU RISC-V 32/64 SPL testing. Unlike QEMU RISC-V 32/64,
we test SPL running in M-mode and U-Boot proper running in S-mode,
with a 4-core SMP configuration.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Bin Meng
2020-03-28 07:25:29 -07:00
committed by Tom Rini
parent b2c2608161
commit 49fb28a4b2
3 changed files with 62 additions and 0 deletions
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22
.travis.yml
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@@ -191,6 +191,14 @@ before_script:
true &&
popd;
fi
- if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
wget -O - https://github.com/riscv/opensbi/releases/download/v0.6/opensbi-0.6-rv32-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-0.6-rv32-bin/platform/qemu/virt/firmware/fw_dynamic.bin;
fi
- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then
wget -O - https://github.com/riscv/opensbi/releases/download/v0.6/opensbi-0.6-rv64-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-0.6-rv64-bin/platform/qemu/virt/firmware/fw_dynamic.bin;
fi
script:
# Comments must be outside the command strings below, or the Travis parser
@@ -586,6 +594,20 @@ matrix:
QEMU_TARGET="riscv64-softmmu"
BUILDMAN="^qemu-riscv64$"
TOOLCHAIN="riscv"
- name: "test/py qemu-riscv32_spl"
env:
- TEST_PY_BD="qemu-riscv32_spl"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="riscv32-softmmu"
BUILDMAN="^qemu-riscv32_spl$"
TOOLCHAIN="riscv"
- name: "test/py qemu-riscv64_spl"
env:
- TEST_PY_BD="qemu-riscv64_spl"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="riscv64-softmmu"
BUILDMAN="^qemu-riscv64_spl$"
TOOLCHAIN="riscv"
- name: "test/py qemu-x86"
env:
- TEST_PY_BD="qemu-x86"