designware_i2c: Added s/w generation of stop bit

In the newer versions of designware i2c IP there is the possibility
of configuring it with IC_EMPTYFIFO_HOLD_MASTER_EN=1, which basically
requires the s/w to generate the stop bit condition directly, as
the h/w will not automatically generate it when TX_FIFO is empty.

To avoid generation of an extra 0x0 byte sent as data, the
IC_STOP command must be sent along with the last IC_CMD.

This patch always writes bit[9] of ic_data_cmd even in the
older versions, assuming that it is a noop there.

Signed-off-by: Armando Visconti <armando.visconti@st.com>

drivers/i2c/designware_i2c.h

@@ -95,6 +95,7 @@ struct i2c_regs {
 
 /* i2c data buffer and command register definitions */
 #define IC_CMD			0x0100
+#define IC_STOP			0x0200
 
 /* i2c interrupt status register definitions */
 #define IC_GEN_CALL		0x0800