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x86: irq: Fix some typos

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Fix some typos in arch/x86/include/asm/irq.h.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Wolfgang Wallner
2020-07-21 13:01:45 +02:00
committed by Bin Meng
parent a2d051e7b6
commit 491135805e
1 changed files with 3 additions and 3 deletions
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6
arch/x86/include/asm/irq.h
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@@ -12,8 +12,8 @@
* Intel interrupt router configuration mechanism * Intel interrupt router configuration mechanism
* *
* There are two known ways of Intel interrupt router configuration mechanism * There are two known ways of Intel interrupt router configuration mechanism
* so far. On most cases, the IRQ routing configuraiton is controlled by PCI * so far. On most cases, the IRQ routing configuration is controlled by PCI
* configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0). * configuration registers on the legacy bridge, normally PCI BDF(0, 31, 0).
* On some newer platforms like BayTrail and Braswell, the IRQ routing is now * On some newer platforms like BayTrail and Braswell, the IRQ routing is now
* in the IBASE register block where IBASE is memory-mapped. * in the IBASE register block where IBASE is memory-mapped.
*/ */
@@ -36,7 +36,7 @@ struct pirq_regmap {
* @link_base: link value base number * @link_base: link value base number
* @link_num: number of PIRQ links supported * @link_num: number of PIRQ links supported
* @has_regmap: has mapping table between PIRQ link and routing register offset * @has_regmap: has mapping table between PIRQ link and routing register offset
* @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means * @irq_mask: IRQ mask representing the 16 IRQs in 8259, bit N is 1 means
* IRQ N is available to be routed * IRQ N is available to be routed
* @lb_bdf: irq router's PCI bus/device/function number encoding * @lb_bdf: irq router's PCI bus/device/function number encoding
* @ibase: IBASE register block base address * @ibase: IBASE register block base address