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mtd: nand: omap: add support for BCH16_ECC - NAND driver updates
This patch add support for BCH16_ECC to omap_gpmc driver. *need to BCH16 ECC scheme* With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes Flash devices have become more suspectible to bit-flips. Thus stronger ECC schemes are required for protecting the data. But stronger ECC schemes have come with larger-sized ECC syndromes which require more space in OOB/Spare. This puts constrains like; (a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data. (b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B. Due to (b) this scheme can only be used with NAND devices which have enough OOB to satisfy following equation: OOBsize per page >= 26 * (page-size / 512) Signed-off-by: Pekon Gupta <pekon@ti.com>
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@@ -27,6 +27,8 @@ enum omap_ecc {
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OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
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/* 8-bit ECC calculation by GPMC, Error detection by ELM */
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OMAP_ECC_BCH8_CODE_HW,
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/* 16-bit ECC calculation by GPMC, Error detection by ELM */
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OMAP_ECC_BCH16_CODE_HW,
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};
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struct gpmc_cs {
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@@ -47,6 +49,10 @@ struct bch_res_0_3 {
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u32 bch_result_x[4];
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};
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struct bch_res_4_6 {
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u32 bch_result_x[3];
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};
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struct gpmc {
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u8 res1[0x10];
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u32 sysconfig; /* 0x10 */
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@@ -77,6 +83,8 @@ struct gpmc {
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u32 testmomde_ctrl; /* 0x230 */
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u8 res8[12]; /* 0x234 */
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struct bch_res_0_3 bch_result_0_3[GPMC_MAX_SECTORS]; /* 0x240,0x250, */
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u8 res9[16 * 4]; /* 0x2C0 - 0x2FF */
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struct bch_res_4_6 bch_result_4_6[GPMC_MAX_SECTORS]; /* 0x300,0x310, */
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};
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/* Used for board specific gpmc initialization */
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