mirror of
https://xff.cz/git/u-boot/
synced 2026-01-06 19:49:18 +01:00
Merge branch 'master' of git://git.denx.de/u-boot-arm
This commit is contained in:
Wolfgang Denk
@@ -36,6 +36,8 @@
|
||||
((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c)
|
||||
|
||||
#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34)
|
||||
#define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50)
|
||||
#define SYSRST_CNT_1SEC_VAL (25*1000000)
|
||||
#define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0)
|
||||
|
||||
enum memory_bank {
|
||||
|
||||
@@ -28,6 +28,18 @@
|
||||
|
||||
extern void imx_gpio_mode (int gpio_mode);
|
||||
|
||||
#ifdef CONFIG_MXC_UART
|
||||
extern void mx27_uart_init_pins(void);
|
||||
#endif /* CONFIG_MXC_UART */
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
extern void mx27_fec_init_pins(void);
|
||||
#endif /* CONFIG_FEC_MXC */
|
||||
|
||||
#ifdef CONFIG_MXC_MMC
|
||||
extern void mx27_sd2_init_pins(void);
|
||||
#endif /* CONFIG_MXC_MMC */
|
||||
|
||||
/* AIPI */
|
||||
struct aipi_regs {
|
||||
u32 psr0;
|
||||
|
||||
@@ -12,36 +12,6 @@
|
||||
|
||||
#include <linux/config.h>
|
||||
|
||||
#define set_cr(x) \
|
||||
__asm__ __volatile__( \
|
||||
"mcr p15, 0, %0, c1, c0 @ set CR" \
|
||||
: : "r" (x))
|
||||
|
||||
#define CR_M (1 << 0) /* MMU enable */
|
||||
#define CR_A (1 << 1) /* Alignment abort enable */
|
||||
#define CR_C (1 << 2) /* Dcache enable */
|
||||
#define CR_W (1 << 3) /* Write buffer enable */
|
||||
#define CR_P (1 << 4) /* 32-bit exception handler */
|
||||
#define CR_D (1 << 5) /* 32-bit data address range */
|
||||
#define CR_L (1 << 6) /* Implementation defined */
|
||||
#define CD_B (1 << 7) /* Big endian */
|
||||
#define CR_S (1 << 8) /* System MMU protection */
|
||||
#define CD_R (1 << 9) /* ROM MMU protection */
|
||||
#define CR_F (1 << 10) /* Implementation defined */
|
||||
#define CR_Z (1 << 11) /* Implementation defined */
|
||||
#define CR_I (1 << 12) /* Icache enable */
|
||||
#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
|
||||
#define CR_RR (1 << 14) /* Round Robin cache replacement */
|
||||
|
||||
extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
|
||||
extern unsigned long cr_alignment; /* defined in entry-armv.S */
|
||||
|
||||
#if __LINUX_ARM_ARCH__ >= 4
|
||||
#define vectors_base() ((cr_alignment & CR_V) ? 0xffff0000 : 0)
|
||||
#else
|
||||
#define vectors_base() (0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Save the current interrupt enable state & disable IRQs
|
||||
*/
|
||||
|
||||
182
include/configs/davinci_dm365evm.h
Normal file
182
include/configs/davinci_dm365evm.h
Normal file
@@ -0,0 +1,182 @@
|
||||
/*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
#include <asm/sizes.h>
|
||||
|
||||
/* Spectrum Digital TMS320DM365 EVM board */
|
||||
#define DAVINCI_DM365EVM
|
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
|
||||
#define CONFIG_SKIP_RELOCATE_UBOOT
|
||||
#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||
|
||||
/* SoC Configuration */
|
||||
#define CONFIG_ARM926EJS /* arm926ejs CPU */
|
||||
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
|
||||
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_SOC_DM365
|
||||
|
||||
/* Memory Info */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM_1 0x80000000
|
||||
#define PHYS_SDRAM_1_SIZE SZ_128M
|
||||
|
||||
/* Serial Driver info: UART0 for console */
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE -4
|
||||
#define CONFIG_SYS_NS16550_COM1 0x01c20000
|
||||
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* EEPROM definitions for EEPROM on DM365 EVM */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
|
||||
|
||||
/* Network Configuration */
|
||||
#define CONFIG_DRIVER_TI_EMAC
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_BOOTP_DEFAULT
|
||||
#define CONFIG_BOOTP_DNS
|
||||
#define CONFIG_BOOTP_DNS2
|
||||
#define CONFIG_BOOTP_SEND_HOSTNAME
|
||||
#define CONFIG_NET_RETRY_COUNT 10
|
||||
#define CONFIG_NET_MULTI
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_DRIVER_DAVINCI_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
|
||||
|
||||
/* NAND: socketed, two chipselects, normally 2 GBytes */
|
||||
#define CONFIG_NAND_DAVINCI
|
||||
#define CONFIG_SYS_NAND_HW_ECC
|
||||
#define CONFIG_SYS_NAND_USE_FLASH_BBT
|
||||
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
|
||||
#define CONFIG_SYS_NAND_PAGE_2K
|
||||
|
||||
#define CONFIG_SYS_NAND_LARGEPAGE
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
|
||||
/* socket has two chipselects, nCE0 gated by address BIT(14) */
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_MAX_CHIPS 2
|
||||
|
||||
/* U-Boot command configuration */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#undef CONFIG_CMD_BDI
|
||||
#undef CONFIG_CMD_FLASH
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_SETGETDCR
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SAVES
|
||||
#define CONFIG_CMD_SAVEENV
|
||||
|
||||
#ifdef CONFIG_NAND_DAVINCI
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_MTD_PARTITIONS
|
||||
#define CONFIG_MTD_DEVICE
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_UBI
|
||||
#define CONFIG_RBTREE
|
||||
#endif
|
||||
|
||||
#define CONFIG_CRC32_VERIFY
|
||||
#define CONFIG_MX_CYCLIC
|
||||
|
||||
/* U-Boot general configuration */
|
||||
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
|
||||
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
|
||||
#define CONFIG_SYS_PROMPT "DM365 EVM # " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
|
||||
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
|
||||
#ifdef CONFIG_NAND_DAVINCI
|
||||
#define CONFIG_ENV_SIZE SZ_256K
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_OFFSET 0x3C0000
|
||||
#undef CONFIG_ENV_IS_IN_FLASH
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"dhcp;bootm"
|
||||
#define CONFIG_BOOTARGS \
|
||||
"console=ttyS0,115200n8 " \
|
||||
"root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
#define CONFIG_TIMESTAMP
|
||||
|
||||
/* U-Boot memory configuration */
|
||||
#define CONFIG_STACKSIZE SZ_256K /* regular stack */
|
||||
#define CONFIG_SYS_MALLOC_LEN SZ_1M /* malloc() arena */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
|
||||
|
||||
/* Linux interfacing */
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
|
||||
|
||||
|
||||
/* NAND configuration issocketed with two chipselects just like the DM355 EVM.
|
||||
* It normally comes with a 2GByte SLC part with 2KB pages
|
||||
* (and 128KB erase blocks); other
|
||||
* 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC
|
||||
* pretty much demands the 4-bit ECC support.) You can of course swap in
|
||||
* other parts, including small page ones.
|
||||
*/
|
||||
#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
|
||||
|
||||
#ifdef CONFIG_SYS_NAND_LARGEPAGE
|
||||
/* Use same layout for 128K/256K blocks; allow some bad blocks */
|
||||
#define PART_BOOT "2m(bootloader)ro,"
|
||||
#else
|
||||
/* Assume 16K erase blocks; allow a few bad ones. */
|
||||
#define PART_BOOT "512k(bootloader)ro,"
|
||||
#endif
|
||||
|
||||
#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
|
||||
#define PART_REST "-(filesystem)"
|
||||
|
||||
#define MTDPARTS_DEFAULT \
|
||||
"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
307
include/configs/devkit8000.h
Normal file
307
include/configs/devkit8000.h
Normal file
@@ -0,0 +1,307 @@
|
||||
/*
|
||||
* (C) Copyright 2006-2008
|
||||
* Texas Instruments.
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <x0khasim@ti.com>
|
||||
*
|
||||
* (C) Copyright 2009
|
||||
* Frederik Kriewitz <frederik@kriewitz.eu>
|
||||
*
|
||||
* Configuration settings for the DevKit8000 board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
#include <asm/sizes.h>
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
|
||||
#define CONFIG_OMAP 1 /* in a TI OMAP core */
|
||||
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
|
||||
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
|
||||
#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
|
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */
|
||||
#include <asm/arch/omap3.h>
|
||||
|
||||
/* Display CPU and Board information */
|
||||
#define CONFIG_DISPLAY_CPUINFO 1
|
||||
#define CONFIG_DISPLAY_BOARDINFO 1
|
||||
|
||||
/* Clock Defines */
|
||||
#define V_OSCK 26000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK >> 1)
|
||||
|
||||
#undef CONFIG_USE_IRQ /* no support for IRQs */
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
#define CONFIG_REVISION_TAG 1
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
|
||||
/* Sector */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
|
||||
/* initial data */
|
||||
|
||||
/* Hardware drivers */
|
||||
|
||||
/* DM9000 */
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
#define CONFIG_DRIVER_DM9000 1
|
||||
#define CONFIG_DM9000_BASE 0x2c000000
|
||||
#define DM9000_IO CONFIG_DM9000_BASE
|
||||
#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
|
||||
#define CONFIG_DM9000_USE_16BIT 1
|
||||
#define CONFIG_DM9000_NO_SROM 1
|
||||
#undef CONFIG_DM9000_DEBUG
|
||||
|
||||
/* NS16550 Configuration */
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
|
||||
|
||||
/* select serial console configuration */
|
||||
#define CONFIG_CONS_INDEX 3
|
||||
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
|
||||
#define CONFIG_SERIAL3 3
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
|
||||
115200}
|
||||
|
||||
/* MMC */
|
||||
#define CONFIG_MMC 1
|
||||
#define CONFIG_OMAP3_MMC 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
||||
|
||||
/* TWL4030 */
|
||||
#define CONFIG_TWL4030_POWER 1
|
||||
#define CONFIG_TWL4030_LED 1
|
||||
|
||||
/* Board NAND Info */
|
||||
#define CONFIG_SYS_NO_FLASH /* no NOR flash */
|
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
|
||||
#define MTDIDS_DEFAULT "nand0=nand"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=nand:" \
|
||||
"512k(x-loader)," \
|
||||
"1920k(u-boot)," \
|
||||
"128k(u-boot-env)," \
|
||||
"4m(kernel)," \
|
||||
"-(fs)"
|
||||
|
||||
#define CONFIG_NAND_OMAP_GPMC
|
||||
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
|
||||
/* to access nand */
|
||||
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
|
||||
/* to access nand at */
|
||||
/* CS0 */
|
||||
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
|
||||
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
|
||||
/* devices */
|
||||
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
|
||||
|
||||
#define CONFIG_JFFS2_NAND
|
||||
/* nand device jffs2 lives on */
|
||||
#define CONFIG_JFFS2_DEV "nand0"
|
||||
/* start of jffs2 partition */
|
||||
#define CONFIG_JFFS2_PART_OFFSET 0x680000
|
||||
#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
|
||||
/* partition */
|
||||
|
||||
/* commands to include */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP /* DHCP support */
|
||||
#define CONFIG_CMD_EXT2 /* EXT2 Support */
|
||||
#define CONFIG_CMD_FAT /* FAT support */
|
||||
#define CONFIG_CMD_I2C /* I2C serial bus support */
|
||||
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
|
||||
#define CONFIG_CMD_MMC /* MMC support */
|
||||
#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
|
||||
#define CONFIG_CMD_NAND /* NAND support */
|
||||
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
|
||||
|
||||
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
|
||||
#undef CONFIG_CMD_IMI /* iminfo */
|
||||
|
||||
/* BOOTP/DHCP options */
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_NISDOMAIN
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_DNS
|
||||
#define CONFIG_BOOTP_DNS2
|
||||
#define CONFIG_BOOTP_SEND_HOSTNAME
|
||||
#define CONFIG_BOOTP_NTPSERVER
|
||||
#define CONFIG_BOOTP_TIMEOFFSET
|
||||
#undef CONFIG_BOOTP_VENDOREX
|
||||
|
||||
/* Environment information */
|
||||
#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"loadaddr=0x82000000\0" \
|
||||
"console=ttyS2,115200n8\0" \
|
||||
"vram=12M\0" \
|
||||
"dvimode=1024x768MR-16@60\0" \
|
||||
"defaultdisplay=dvi\0" \
|
||||
"nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
|
||||
"kernelopts=rw\0" \
|
||||
"commonargs=" \
|
||||
"setenv bootargs console=${console} " \
|
||||
"vram=${vram} " \
|
||||
"omapfb.mode=dvi:${dvimode} " \
|
||||
"omapdss.def_disp=${defaultdisplay}\0" \
|
||||
"mmcargs=" \
|
||||
"run commonargs; " \
|
||||
"setenv bootargs ${bootargs} " \
|
||||
"root=/dev/mmcblk0p2 " \
|
||||
"${kernelopts}\0" \
|
||||
"nandargs=" \
|
||||
"run commonargs; " \
|
||||
"setenv bootargs ${bootargs} " \
|
||||
"omapfb.mode=dvi:${dvimode} " \
|
||||
"omapdss.def_disp=${defaultdisplay} " \
|
||||
"root=/dev/mtdblock4 " \
|
||||
"rootfstype=jffs2 " \
|
||||
"${kernelopts}\0" \
|
||||
"netargs=" \
|
||||
"run commonargs; " \
|
||||
"setenv bootargs ${bootargs} " \
|
||||
"root=/dev/nfs " \
|
||||
"nfsroot=${serverip}:${rootpath},${nfsopts} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
|
||||
"${kernelopts} " \
|
||||
"dnsip1=${dnsip} " \
|
||||
"dnsip2=${dnsip2}\0" \
|
||||
"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source ${loadaddr}\0" \
|
||||
"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
|
||||
"eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"nandboot=echo Booting from nand ...; " \
|
||||
"run nandargs; " \
|
||||
"nand read ${loadaddr} 280000 400000; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"netboot=echo Booting from network ...; " \
|
||||
"dhcp ${loadaddr}; " \
|
||||
"run netargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"autoboot=if mmc init 0; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run nandboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run nandboot; fi\0"
|
||||
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run autoboot"
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_AUTO_COMPLETE 1
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # "
|
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 128 /* max number of command args */
|
||||
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
|
||||
0x01000000) /* 16MB */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
|
||||
|
||||
/*
|
||||
* OMAP3 has 12 GP timers, they can be driven by the system clock
|
||||
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
|
||||
* This rate is divided by a local divisor.
|
||||
*/
|
||||
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
|
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* The stack sizes are set up in start.S using the settings below */
|
||||
#define CONFIG_STACKSIZE SZ_128K /* regular stack */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
|
||||
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
|
||||
#define PHYS_SDRAM_1_SIZE SZ_128M /* at least 128 meg */
|
||||
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
|
||||
|
||||
/* SDRAM Bank Allocation method */
|
||||
#define SDRC_R_B_C 1
|
||||
|
||||
/* NAND and environment organization */
|
||||
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
|
||||
|
||||
#define CONFIG_ENV_OFFSET boot_flash_off
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern struct gpmc *gpmc_cfg;
|
||||
extern unsigned int boot_flash_base;
|
||||
extern volatile unsigned int boot_flash_env_addr;
|
||||
extern unsigned int boot_flash_off;
|
||||
extern unsigned int boot_flash_sec;
|
||||
extern unsigned int boot_flash_type;
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
252
include/configs/imx27lite.h
Normal file
252
include/configs/imx27lite.h
Normal file
@@ -0,0 +1,252 @@
|
||||
/*
|
||||
* Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* SoC Configuration
|
||||
*/
|
||||
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
|
||||
#define CONFIG_MX27
|
||||
#define CONFIG_IMX27LITE
|
||||
#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
|
||||
/*
|
||||
* Lowlevel configuration
|
||||
*/
|
||||
#define SDRAM_ESDCFG_REGISTER_VAL(cas) \
|
||||
(ESDCFG_TRC(10) | \
|
||||
ESDCFG_TRCD(3) | \
|
||||
ESDCFG_TCAS(cas) | \
|
||||
ESDCFG_TRRD(1) | \
|
||||
ESDCFG_TRAS(5) | \
|
||||
ESDCFG_TWR | \
|
||||
ESDCFG_TMRD(2) | \
|
||||
ESDCFG_TRP(2) | \
|
||||
ESDCFG_TXP(3))
|
||||
|
||||
#define SDRAM_ESDCTL_REGISTER_VAL \
|
||||
(ESDCTL_PRCT(0) | \
|
||||
ESDCTL_BL | \
|
||||
ESDCTL_PWDT(0) | \
|
||||
ESDCTL_SREFR(3) | \
|
||||
ESDCTL_DSIZ_32 | \
|
||||
ESDCTL_COL10 | \
|
||||
ESDCTL_ROW13 | \
|
||||
ESDCTL_SDE)
|
||||
|
||||
#define SDRAM_ALL_VAL 0xf00
|
||||
|
||||
#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */
|
||||
#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000
|
||||
|
||||
#define MPCTL0_VAL 0x1ef15d5
|
||||
|
||||
#define SPCTL0_VAL 0x043a1c09
|
||||
|
||||
#define CSCR_VAL 0x33f08107
|
||||
|
||||
#define PCDR0_VAL 0x120470c3
|
||||
#define PCDR1_VAL 0x03030303
|
||||
#define PCCR0_VAL 0xffffffff
|
||||
#define PCCR1_VAL 0xfffffffc
|
||||
|
||||
#define AIPI1_PSR0_VAL 0x20040304
|
||||
#define AIPI1_PSR1_VAL 0xdffbfcfb
|
||||
#define AIPI2_PSR0_VAL 0x07ffc200
|
||||
#define AIPI2_PSR1_VAL 0xffffffff
|
||||
|
||||
/*
|
||||
* Memory Info
|
||||
*/
|
||||
/* malloc() len */
|
||||
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024)
|
||||
/* reserved for initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128
|
||||
/* memtest start address */
|
||||
#define CONFIG_SYS_MEMTEST_START 0xA0000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
|
||||
#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */
|
||||
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
|
||||
|
||||
/*
|
||||
* Serial Driver info
|
||||
*/
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_SYS_MX27_UART1
|
||||
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
|
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* Flash & Environment
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
/* Use buffered writes (~10x faster) */
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
|
||||
/* Use hardware sector protection */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION 1
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
|
||||
#define CONFIG_SYS_FLASH_SECT_SZ 0x2000 /* 8KB sect size Intel Flash */
|
||||
/* end of flash */
|
||||
#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x20000)
|
||||
/* CS2 Base address */
|
||||
#define PHYS_FLASH_1 0xc0000000
|
||||
/* Flash Base for U-Boot */
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
|
||||
/* Flash size 2MB */
|
||||
#define PHYS_FLASH_SIZE 0x200000
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \
|
||||
CONFIG_SYS_FLASH_SECT_SZ)
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* Env sector Size */
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1f
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_NET_MULTI
|
||||
|
||||
/*
|
||||
* MTD
|
||||
*/
|
||||
#define CONFIG_MTD_DEVICE
|
||||
|
||||
/*
|
||||
* NAND
|
||||
*/
|
||||
#define CONFIG_NAND_MXC
|
||||
#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0xd8000000
|
||||
#define CONFIG_JFFS2_NAND
|
||||
#define CONFIG_MXC_NAND_HWECC
|
||||
|
||||
/*
|
||||
* SD/MMC
|
||||
*/
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_MXC_MMC
|
||||
#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/*
|
||||
* MTD partitions
|
||||
*/
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0"
|
||||
#define MTDPARTS_DEFAULT \
|
||||
"mtdparts=" \
|
||||
"physmap-flash.0:" \
|
||||
"256k(U-Boot)," \
|
||||
"1664k(user)," \
|
||||
"64k(env1)," \
|
||||
"64k(env2);" \
|
||||
"mxc_nand.0:" \
|
||||
"128k(IPL-SPL)," \
|
||||
"4m(kernel)," \
|
||||
"22m(rootfs)," \
|
||||
"-(userfs)"
|
||||
|
||||
/*
|
||||
* U-Boot general configuration
|
||||
*/
|
||||
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
/* Print buffer sz */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
|
||||
/*
|
||||
* U-Boot commands
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
|
||||
#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define xstr(s) str(s)
|
||||
#define str(s) #s
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs}" \
|
||||
" console=ttymxc0,${baudrate}\0" \
|
||||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"addmisc=setenv bootargs ${bootargs}\0" \
|
||||
"u-boot=imx27/u-boot.bin\0" \
|
||||
"kernel_addr_r=a0800000\0" \
|
||||
"hostname=imx27\0" \
|
||||
"bootfile=imx27/uImage\0" \
|
||||
"rootpath=/opt/eldk-4.2-arm/arm\0" \
|
||||
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
|
||||
"run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm\0" \
|
||||
"bootcmd=run net_nfs\0" \
|
||||
"load=tftp ${loadaddr} ${u-boot}\0" \
|
||||
"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
|
||||
" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
|
||||
" +${filesize};cp.b ${fileaddr} " \
|
||||
xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
|
||||
"upd=run load update\0" \
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
194
include/configs/sbc35_a9g20.h
Normal file
194
include/configs/sbc35_a9g20.h
Normal file
@@ -0,0 +1,194 @@
|
||||
/*
|
||||
* Copyright (C) 2009
|
||||
* Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
|
||||
*
|
||||
* Configuation settings for the Calao SBC35-A9G20 board
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#if defined(CONFIG_SBC35_A9G20_NANDFLASH) || defined(CONFIG_SBC35_A9G20_EEPROM)
|
||||
#define CONFIG_SBC35_A9G20
|
||||
#endif
|
||||
|
||||
#define CONFIG_AT91SAM9G20
|
||||
|
||||
#if defined(CONFIG_SBC35_A9G20_NANDFLASH)
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_EEPROM
|
||||
#endif
|
||||
|
||||
/* ARM asynchronous clock */
|
||||
#define AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
|
||||
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#define CONFIG_SKIP_RELOCATE_UBOOT
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
#define CONFIG_ATMEL_USART
|
||||
#define CONFIG_USART0
|
||||
#undef CONFIG_USART1
|
||||
#undef CONFIG_USART2
|
||||
#undef CONFIG_USART3
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE 1
|
||||
#define CONFIG_BOOTP_BOOTPATH 1
|
||||
#define CONFIG_BOOTP_GATEWAY 1
|
||||
#define CONFIG_BOOTP_HOSTNAME 1
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
#undef CONFIG_CMD_BDI
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_IMI
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#undef CONFIG_CMD_SOURCE
|
||||
|
||||
#define CONFIG_CMD_PING 1
|
||||
#define CONFIG_CMD_DHCP 1
|
||||
#define CONFIG_CMD_USB 1
|
||||
|
||||
/* SDRAM */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM 0x20000000
|
||||
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
|
||||
|
||||
/* SPI EEPROM */
|
||||
#define CONFIG_SPI
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_ATMEL_SPI
|
||||
#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
|
||||
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_SPI_M95XXX
|
||||
#define CONFIG_SYS_EEPROM_SIZE 0x10000
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
|
||||
|
||||
/* SPI RTC */
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_RTC_M41T94
|
||||
#define CONFIG_M41T94_SPI_BUS 0
|
||||
#define CONFIG_M41T94_SPI_CS 0
|
||||
|
||||
/* NAND flash */
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_NAND_ATMEL
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_DBW_8 1
|
||||
/* our ALE is AD21 */
|
||||
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
|
||||
/* our CLE is AD22 */
|
||||
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
|
||||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
|
||||
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
|
||||
|
||||
/* NOR flash - no real flash on this board */
|
||||
#define CONFIG_SYS_NO_FLASH 1
|
||||
|
||||
/* Ethernet */
|
||||
#define CONFIG_MACB 1
|
||||
#define CONFIG_RMII 1
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
#define CONFIG_RESET_PHY_R 1
|
||||
#define CONFIG_MACB_SEARCH_PHY 1
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_USB_ATMEL
|
||||
#define CONFIG_USB_OHCI_NEW 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
|
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
|
||||
#define CONFIG_USB_STORAGE 1
|
||||
#define CONFIG_CMD_FAT 1
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
|
||||
#define CONFIG_SYS_MEMTEST_END 0x23e00000
|
||||
|
||||
/* Env in EEPROM, bootstrap + u-boot in NAND*/
|
||||
#ifdef CONFIG_ENV_IS_IN_EEPROM
|
||||
#define CONFIG_ENV_OFFSET 0x20
|
||||
#define CONFIG_ENV_SIZE 0x1000
|
||||
#endif
|
||||
|
||||
/* Env, bootstrap and u-boot in NAND */
|
||||
#ifdef CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_OFFSET 0x60000
|
||||
#define CONFIG_ENV_OFFSET_REDUND 0x80000
|
||||
#define CONFIG_ENV_SIZE 0x20000
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
|
||||
"root=/dev/mtdblock1 " \
|
||||
"mtdparts=atmel_nand:16M(kernel)ro," \
|
||||
"120M(rootfs),-(other) " \
|
||||
"rw rootfstype=jffs2"
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
|
||||
|
||||
#define CONFIG_SYS_PROMPT "U-Boot> "
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_LONGHELP 1
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
|
||||
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#error CONFIG_USE_IRQ not supported
|
||||
#endif
|
||||
|
||||
#endif
|
||||
172
include/configs/tny_a9260.h
Normal file
172
include/configs/tny_a9260.h
Normal file
@@ -0,0 +1,172 @@
|
||||
/*
|
||||
* (C) Copyright 2007-2008
|
||||
* Stelian Pop <stelian.pop@leadtechdesign.com>
|
||||
* Lead Tech Design <www.leadtechdesign.com>
|
||||
*
|
||||
* Copyright (C) 2009
|
||||
* Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
|
||||
*
|
||||
* Configuation settings for the Calao TNY-A9260 and TNY-A9G20 boards
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9260_EEPROM)
|
||||
#define CONFIG_TNY_A9260
|
||||
#elif defined(CONFIG_TNY_A9G20_NANDFLASH) || defined(CONFIG_TNY_A9G20_EEPROM)
|
||||
#define CONFIG_TNY_A9G20
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TNY_A9260
|
||||
#define CONFIG_AT91SAM9260
|
||||
#else
|
||||
#define CONFIG_AT91SAM9G20
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9G20_NANDFLASH)
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_EEPROM
|
||||
#endif
|
||||
|
||||
/* ARM asynchronous clock */
|
||||
#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#define CONFIG_SKIP_RELOCATE_UBOOT
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
#define CONFIG_ATMEL_USART 1
|
||||
#undef CONFIG_USART0
|
||||
#undef CONFIG_USART1
|
||||
#undef CONFIG_USART2
|
||||
#define CONFIG_USART3 1 /* USART 3 is DBGU */
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
#undef CONFIG_CMD_BDI
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_IMI
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#undef CONFIG_CMD_NET
|
||||
#undef CONFIG_CMD_SOURCE
|
||||
#undef CONFIG_CMD_USB
|
||||
|
||||
/* SDRAM */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM 0x20000000
|
||||
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
|
||||
|
||||
/* SPI EEPROM */
|
||||
#define CONFIG_SPI
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_ATMEL_SPI
|
||||
#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
|
||||
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_SPI_M95XXX
|
||||
#define CONFIG_SYS_EEPROM_SIZE 0x10000
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
|
||||
|
||||
/* NAND flash */
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_NAND_ATMEL
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_DBW_8 1
|
||||
/* our ALE is AD21 */
|
||||
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
|
||||
/* our CLE is AD22 */
|
||||
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
|
||||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
|
||||
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
|
||||
|
||||
/* NOR flash - no real flash on this board */
|
||||
#define CONFIG_SYS_NO_FLASH 1
|
||||
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#define CONFIG_CMD_FAT 1
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
|
||||
#define CONFIG_SYS_MEMTEST_END 0x23e00000
|
||||
|
||||
/* Env in EEPROM, bootstrap + u-boot in NAND*/
|
||||
#ifdef CONFIG_ENV_IS_IN_EEPROM
|
||||
#define CONFIG_ENV_OFFSET 0x20
|
||||
#define CONFIG_ENV_SIZE 0x1000
|
||||
#endif
|
||||
|
||||
/* Env, bootstrap and u-boot in NAND */
|
||||
#ifdef CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_OFFSET 0x60000
|
||||
#define CONFIG_ENV_OFFSET_REDUND 0x80000
|
||||
#define CONFIG_ENV_SIZE 0x20000
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
|
||||
"root=/dev/mtdblock1 " \
|
||||
"mtdparts=atmel_nand:16M(kernel)ro," \
|
||||
"120M(rootfs),-(other) " \
|
||||
"rw rootfstype=jffs2"
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
|
||||
|
||||
#define CONFIG_SYS_PROMPT "U-Boot> "
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_LONGHELP 1
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
|
||||
|
||||
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#error CONFIG_USE_IRQ not supported
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user