dts: add device tree for STM32MP157C-ED1 board

Add minimal devicetree for STM32MP157C-ED1 board,
with only the devices to allow boot from SDCARD:
- RCC for clock and reset
- UART4 for console
- I2C and PMIC
- DDR
- SDMMC0 for SDCard

Waiting Kernel upstream for alignment.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

include/dt-bindings/clock/stm32mp1-clks.h

@@ -0,0 +1,243 @@
+/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
+ */
+/* OSCILLATOR clocks */
+#define CK_HSE 0
+#define CK_CSI 1
+#define CK_LSI 2
+#define CK_LSE 3
+#define CK_HSI 4
+#define CK_HSE_DIV2 5
+
+/* Bus clocks */
+#define TIM2 6
+#define TIM3 7
+#define TIM4 8
+#define TIM5 9
+#define TIM6 10
+#define TIM7 11
+#define TIM12 12
+#define TIM13 13
+#define TIM14 14
+#define LPTIM1 15
+#define SPI2 16
+#define SPI3 17
+#define USART2 18
+#define USART3 19
+#define UART4 20
+#define UART5 21
+#define UART7 22
+#define UART8 23
+#define I2C1 24
+#define I2C2 25
+#define I2C3 26
+#define I2C5 27
+#define SPDIF 28
+#define CEC 29
+#define DAC12 30
+#define MDIO 31
+#define TIM1 32
+#define TIM8 33
+#define TIM15 34
+#define TIM16 35
+#define TIM17 36
+#define SPI1 37
+#define SPI4 38
+#define SPI5 39
+#define USART6 40
+#define SAI1 41
+#define SAI2 42
+#define SAI3 43
+#define DFSDM 44
+#define FDCAN 45
+#define LPTIM2 46
+#define LPTIM3 47
+#define LPTIM4 48
+#define LPTIM5 49
+#define SAI4 50
+#define SYSCFG 51
+#define VREF 52
+#define TMPSENS 53
+#define PMBCTRL 54
+#define HDP 55
+#define LTDC 56
+#define DSI 57
+#define IWDG2 58
+#define USBPHY 59
+#define STGENRO 60
+#define SPI6 61
+#define I2C4 62
+#define I2C6 63
+#define USART1 64
+#define RTCAPB 65
+#define TZC 66
+#define TZPC 67
+#define IWDG1 68
+#define BSEC 69
+#define STGEN 70
+#define DMA1 71
+#define DMA2 72
+#define DMAMUX 73
+#define ADC12 74
+#define USBO 75
+#define SDMMC3 76
+#define DCMI 77
+#define CRYP2 78
+#define HASH2 79
+#define RNG2 80
+#define CRC2 81
+#define HSEM 82
+#define IPCC 83
+#define GPIOA 84
+#define GPIOB 85
+#define GPIOC 86
+#define GPIOD 87
+#define GPIOE 88
+#define GPIOF 89
+#define GPIOG 90
+#define GPIOH 91
+#define GPIOI 92
+#define GPIOJ 93
+#define GPIOK 94
+#define GPIOZ 95
+#define CRYP1 96
+#define HASH1 97
+#define RNG1 98
+#define BKPSRAM 99
+#define MDMA 100
+#define DMA2D 101
+#define GPU 102
+#define ETHCK 103
+#define ETHTX 104
+#define ETHRX 105
+#define ETHMAC 106
+#define FMC 107
+#define QSPI 108
+#define SDMMC1 109
+#define SDMMC2 110
+#define CRC1 111
+#define USBH 112
+#define ETHSTP 113
+
+/* Kernel clocks */
+#define SDMMC1_K 114
+#define SDMMC2_K 115
+#define SDMMC3_K 116
+#define FMC_K 117
+#define QSPI_K 118
+#define ETHMAC_K 119
+#define RNG1_K 120
+#define RNG2_K 121
+#define GPU_K 122
+#define USBPHY_K 123
+#define STGEN_K 124
+#define SPDIF_K 125
+#define SPI1_K 126
+#define SPI2_K 127
+#define SPI3_K 128
+#define SPI4_K 129
+#define SPI5_K 130
+#define SPI6_K 131
+#define CEC_K 132
+#define I2C1_K 133
+#define I2C2_K 134
+#define I2C3_K 135
+#define I2C4_K 136
+#define I2C5_K 137
+#define I2C6_K 138
+#define LPTIM1_K 139
+#define LPTIM2_K 140
+#define LPTIM3_K 141
+#define LPTIM4_K 142
+#define LPTIM5_K 143
+#define USART1_K 144
+#define USART2_K 145
+#define USART3_K 146
+#define UART4_K 147
+#define UART5_K 148
+#define USART6_K 149
+#define UART7_K 150
+#define UART8_K 151
+#define DFSDM_K 152
+#define FDCAN_K 153
+#define SAI1_K 154
+#define SAI2_K 155
+#define SAI3_K 156
+#define SAI4_K 157
+#define ADC12_K 158
+#define DSI_K 159
+#define ADFSDM_K 160
+#define USBO_K 161
+#define LTDC_K 162
+
+/* PLL */
+#define PLL1 163
+#define PLL2 164
+#define PLL3 165
+#define PLL4 166
+
+/* ODF */
+#define PLL1_P 167
+#define PLL1_Q 168
+#define PLL1_R 169
+#define PLL2_P 170
+#define PLL2_Q 171
+#define PLL2_R 172
+#define PLL3_P 173
+#define PLL3_Q 174
+#define PLL3_R 175
+#define PLL4_P 176
+#define PLL4_Q 177
+#define PLL4_R 178
+
+/* AUX */
+#define RTC 179
+
+/* MCLK */
+#define CK_PER 180
+#define CK_MPU 181
+#define CK_AXI 182
+#define CK_MCU 183
+
+/* Time base */
+#define TIM2_K 184
+#define TIM3_K 185
+#define TIM4_K 186
+#define TIM5_K 187
+#define TIM6_K 188
+#define TIM7_K 189
+#define TIM12_K 190
+#define TIM13_K 191
+#define TIM14_K 192
+#define TIM1_K 193
+#define TIM8_K 194
+#define TIM15_K 195
+#define TIM16_K 196
+#define TIM17_K 197
+
+/* MCO clocks */
+#define CK_MCO1 198
+#define CK_MCO2 199
+
+/* TRACE & DEBUG clocks */
+#define DBG 200
+#define CK_DBG 201
+#define CK_TRACE 202
+
+/* DDR */
+#define DDRC1 203
+#define DDRC1LP 204
+#define DDRC2 205
+#define DDRC2LP 206
+#define DDRPHYC 207
+#define DDRPHYCLP 208
+#define DDRCAPB 209
+#define DDRCAPBLP 210
+#define AXIDCG 211
+#define DDRPHYCAPB 212
+#define DDRPHYCAPBLP 213
+#define DDRPERFM 214
+
+#define STM32MP1_LAST_CLK 215

include/dt-bindings/reset-controller/stm32mp1-resets.h

@@ -0,0 +1,97 @@
+#define	LTDC_R		3072
+#define	DSI_R		3076
+#define DDRPERFM_R	3080
+#define	USBPHY_R	3088
+#define	SPI6_R		3136
+#define	I2C4_R		3138
+#define	I2C6_R		3139
+#define	USART1_R	3140
+#define	STGEN_R		3156
+#define	GPIOZ_R		3200
+#define	CRYP1_R		3204
+#define	HASH1_R		3205
+#define	RNG1_R		3206
+#define AXIM_R		3216
+#define	GPU_R		3269
+#define	ETHMAC_R	3274
+#define	FMC_R		3276
+#define	QSPI_R		3278
+#define	SDMMC1_R	3280
+#define	SDMMC2_R	3281
+#define	CRC1_R		3284
+#define	USBH_R		3288
+#define	MDMA_R		3328
+#define MCU_R		8225
+#define	TIM2_R		19456
+#define	TIM3_R		19457
+#define	TIM4_R		19458
+#define	TIM5_R		19459
+#define	TIM6_R		19460
+#define	TIM7_R		19461
+#define	TIM12_R		16462
+#define	TIM13_R		16463
+#define	TIM14_R		16464
+#define	LPTIM1_R	19465
+#define	SPI2_R		19467
+#define	SPI3_R		19468
+#define	USART2_R	19470
+#define	USART3_R	19471
+#define	UART4_R		19472
+#define	UART5_R		19473
+#define	UART7_R		19474
+#define	UART8_R		19475
+#define	I2C1_R		19477
+#define	I2C2_R		19478
+#define	I2C3_R		19479
+#define	I2C5_R		19480
+#define	SPDIF_R		19482
+#define	CEC_R		19483
+#define	DAC12_R		19485
+#define	MDIO_R		19847
+#define	TIM1_R		19520
+#define	TIM8_R		19521
+#define	TIM15_R		19522
+#define	TIM16_R		19523
+#define	TIM17_R		19524
+#define	SPI1_R		19528
+#define	SPI4_R		19529
+#define	SPI5_R		19530
+#define	USART6_R	19533
+#define	SAI1_R		19536
+#define	SAI2_R		19537
+#define	SAI3_R		19538
+#define	DFSDM_R		19540
+#define	FDCAN_R		19544
+#define	LPTIM2_R	19584
+#define	LPTIM3_R	19585
+#define	LPTIM4_R	19586
+#define	LPTIM5_R	19587
+#define	SAI4_R		19592
+#define	SYSCFG_R	19595
+#define	VREF_R		19597
+#define	TMPSENS_R	19600
+#define	PMBCTRL_R	19601
+#define	DMA1_R		19648
+#define	DMA2_R		19649
+#define	DMAMUX_R	19650
+#define	ADC12_R		19653
+#define	USBO_R		19656
+#define	SDMMC3_R	19664
+#define	CAMITF_R	19712
+#define	CRYP2_R		19716
+#define	HASH2_R		19717
+#define	RNG2_R		19718
+#define	CRC2_R		19719
+#define	HSEM_R		19723
+#define	MBOX_R		19724
+#define	GPIOA_R		19776
+#define	GPIOB_R		19777
+#define	GPIOC_R		19778
+#define	GPIOD_R		19779
+#define	GPIOE_R		19780
+#define	GPIOF_R		19781
+#define	GPIOG_R		19782
+#define	GPIOH_R		19783
+#define	GPIOI_R		19784
+#define	GPIOJ_R		19785
+#define	GPIOK_R		19786