mirror of
https://xff.cz/git/u-boot/
synced 2025-08-31 16:22:36 +02:00
mx6sxsabresd: Keep only one target
Currently there are two targets for the i.MX6SX SabreSD board: mx6sxsabresd_defconfig and mx6sxsabresd_spl_defconfig. This brings additional maintainance effort without a clear advantage. Keep only the mx6sxsabresd_defconfig one and remove mx6sxsabresd_spl_defconfig to keep it simpler. Also remove the SPL related code from the board file. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Fabio Estevam
committed by
Stefano Babic
Stefano Babic
parent
19ba4808c1
commit
3ce1ef5b8f
@@ -4,4 +4,3 @@ S: Maintained
|
|||||||
F: board/freescale/mx6sxsabresd/
|
F: board/freescale/mx6sxsabresd/
|
||||||
F: include/configs/mx6sxsabresd.h
|
F: include/configs/mx6sxsabresd.h
|
||||||
F: configs/mx6sxsabresd_defconfig
|
F: configs/mx6sxsabresd_defconfig
|
||||||
F: configs/mx6sxsabresd_spl_defconfig
|
|
||||||
|
|||||||
@@ -321,239 +321,3 @@ int checkboard(void)
|
|||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_SPL_BUILD
|
|
||||||
#include <linux/libfdt.h>
|
|
||||||
#include <spl.h>
|
|
||||||
#include <asm/arch/mx6-ddr.h>
|
|
||||||
|
|
||||||
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
|
|
||||||
{USDHC2_BASE_ADDR, 0, 4},
|
|
||||||
{USDHC3_BASE_ADDR},
|
|
||||||
{USDHC4_BASE_ADDR},
|
|
||||||
};
|
|
||||||
|
|
||||||
#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
|
|
||||||
#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
|
|
||||||
#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
|
|
||||||
|
|
||||||
static iomux_v3_cfg_t const usdhc2_pads[] = {
|
|
||||||
MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
};
|
|
||||||
|
|
||||||
static iomux_v3_cfg_t const usdhc3_pads[] = {
|
|
||||||
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
|
|
||||||
/* CD pin */
|
|
||||||
MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
||||||
|
|
||||||
/* RST_B, used for power reset cycle */
|
|
||||||
MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
||||||
};
|
|
||||||
|
|
||||||
static iomux_v3_cfg_t const usdhc4_pads[] = {
|
|
||||||
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
||||||
};
|
|
||||||
|
|
||||||
int board_mmc_init(bd_t *bis)
|
|
||||||
{
|
|
||||||
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
|
|
||||||
u32 val;
|
|
||||||
u32 port;
|
|
||||||
|
|
||||||
val = readl(&src_regs->sbmr1);
|
|
||||||
|
|
||||||
if ((val & 0xc0) != 0x40) {
|
|
||||||
printf("Not boot from USDHC!\n");
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
port = (val >> 11) & 0x3;
|
|
||||||
printf("port %d\n", port);
|
|
||||||
switch (port) {
|
|
||||||
case 1:
|
|
||||||
imx_iomux_v3_setup_multiple_pads(
|
|
||||||
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
|
||||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
|
||||||
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
|
|
||||||
break;
|
|
||||||
case 2:
|
|
||||||
imx_iomux_v3_setup_multiple_pads(
|
|
||||||
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
|
||||||
gpio_direction_input(USDHC3_CD_GPIO);
|
|
||||||
gpio_direction_output(USDHC3_PWR_GPIO, 1);
|
|
||||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
||||||
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
|
|
||||||
break;
|
|
||||||
case 3:
|
|
||||||
imx_iomux_v3_setup_multiple_pads(
|
|
||||||
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
|
|
||||||
gpio_direction_input(USDHC4_CD_GPIO);
|
|
||||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
|
||||||
usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
|
|
||||||
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
|
||||||
}
|
|
||||||
|
|
||||||
int board_mmc_getcd(struct mmc *mmc)
|
|
||||||
{
|
|
||||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
|
||||||
int ret = 0;
|
|
||||||
|
|
||||||
switch (cfg->esdhc_base) {
|
|
||||||
case USDHC2_BASE_ADDR:
|
|
||||||
ret = 1; /* Assume uSDHC2 is always present */
|
|
||||||
break;
|
|
||||||
case USDHC3_BASE_ADDR:
|
|
||||||
ret = !gpio_get_value(USDHC3_CD_GPIO);
|
|
||||||
break;
|
|
||||||
case USDHC4_BASE_ADDR:
|
|
||||||
ret = !gpio_get_value(USDHC4_CD_GPIO);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
|
|
||||||
.dram_dqm0 = 0x00000028,
|
|
||||||
.dram_dqm1 = 0x00000028,
|
|
||||||
.dram_dqm2 = 0x00000028,
|
|
||||||
.dram_dqm3 = 0x00000028,
|
|
||||||
.dram_ras = 0x00000020,
|
|
||||||
.dram_cas = 0x00000020,
|
|
||||||
.dram_odt0 = 0x00000020,
|
|
||||||
.dram_odt1 = 0x00000020,
|
|
||||||
.dram_sdba2 = 0x00000000,
|
|
||||||
.dram_sdcke0 = 0x00003000,
|
|
||||||
.dram_sdcke1 = 0x00003000,
|
|
||||||
.dram_sdclk_0 = 0x00000030,
|
|
||||||
.dram_sdqs0 = 0x00000028,
|
|
||||||
.dram_sdqs1 = 0x00000028,
|
|
||||||
.dram_sdqs2 = 0x00000028,
|
|
||||||
.dram_sdqs3 = 0x00000028,
|
|
||||||
.dram_reset = 0x00000020,
|
|
||||||
};
|
|
||||||
|
|
||||||
const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
|
|
||||||
.grp_addds = 0x00000020,
|
|
||||||
.grp_ddrmode_ctl = 0x00020000,
|
|
||||||
.grp_ddrpke = 0x00000000,
|
|
||||||
.grp_ddrmode = 0x00020000,
|
|
||||||
.grp_b0ds = 0x00000028,
|
|
||||||
.grp_b1ds = 0x00000028,
|
|
||||||
.grp_ctlds = 0x00000020,
|
|
||||||
.grp_ddr_type = 0x000c0000,
|
|
||||||
.grp_b2ds = 0x00000028,
|
|
||||||
.grp_b3ds = 0x00000028,
|
|
||||||
};
|
|
||||||
|
|
||||||
const struct mx6_mmdc_calibration mx6_mmcd_calib = {
|
|
||||||
.p0_mpwldectrl0 = 0x00290025,
|
|
||||||
.p0_mpwldectrl1 = 0x00220022,
|
|
||||||
.p0_mpdgctrl0 = 0x41480144,
|
|
||||||
.p0_mpdgctrl1 = 0x01340130,
|
|
||||||
.p0_mprddlctl = 0x3C3E4244,
|
|
||||||
.p0_mpwrdlctl = 0x34363638,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct mx6_ddr3_cfg mem_ddr = {
|
|
||||||
.mem_speed = 1600,
|
|
||||||
.density = 4,
|
|
||||||
.width = 32,
|
|
||||||
.banks = 8,
|
|
||||||
.rowaddr = 15,
|
|
||||||
.coladdr = 10,
|
|
||||||
.pagesz = 2,
|
|
||||||
.trcd = 1375,
|
|
||||||
.trcmin = 4875,
|
|
||||||
.trasmin = 3500,
|
|
||||||
};
|
|
||||||
|
|
||||||
static void ccgr_init(void)
|
|
||||||
{
|
|
||||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
||||||
|
|
||||||
writel(0xFFFFFFFF, &ccm->CCGR0);
|
|
||||||
writel(0xFFFFFFFF, &ccm->CCGR1);
|
|
||||||
writel(0xFFFFFFFF, &ccm->CCGR2);
|
|
||||||
writel(0xFFFFFFFF, &ccm->CCGR3);
|
|
||||||
writel(0xFFFFFFFF, &ccm->CCGR4);
|
|
||||||
writel(0xFFFFFFFF, &ccm->CCGR5);
|
|
||||||
writel(0xFFFFFFFF, &ccm->CCGR6);
|
|
||||||
writel(0xFFFFFFFF, &ccm->CCGR7);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void spl_dram_init(void)
|
|
||||||
{
|
|
||||||
struct mx6_ddr_sysinfo sysinfo = {
|
|
||||||
.dsize = mem_ddr.width/32,
|
|
||||||
.cs_density = 24,
|
|
||||||
.ncs = 1,
|
|
||||||
.cs1_mirror = 0,
|
|
||||||
.rtt_wr = 2,
|
|
||||||
.rtt_nom = 2, /* RTT_Nom = RZQ/2 */
|
|
||||||
.walat = 1, /* Write additional latency */
|
|
||||||
.ralat = 5, /* Read additional latency */
|
|
||||||
.mif3_mode = 3, /* Command prediction working mode */
|
|
||||||
.bi_on = 1, /* Bank interleaving enabled */
|
|
||||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
|
|
||||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
|
||||||
.ddr_type = DDR_TYPE_DDR3,
|
|
||||||
.refsel = 1, /* Refresh cycles at 32KHz */
|
|
||||||
.refr = 7, /* 8 refresh commands per refresh cycle */
|
|
||||||
};
|
|
||||||
|
|
||||||
mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
|
|
||||||
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
|
|
||||||
}
|
|
||||||
|
|
||||||
void board_init_f(ulong dummy)
|
|
||||||
{
|
|
||||||
/* setup AIPS and disable watchdog */
|
|
||||||
arch_cpu_init();
|
|
||||||
|
|
||||||
ccgr_init();
|
|
||||||
|
|
||||||
/* iomux and setup of i2c */
|
|
||||||
board_early_init_f();
|
|
||||||
|
|
||||||
/* setup GP timer */
|
|
||||||
timer_init();
|
|
||||||
|
|
||||||
/* UART clocks enabled and gd valid - init serial console */
|
|
||||||
preloader_console_init();
|
|
||||||
|
|
||||||
/* DDR initialization */
|
|
||||||
spl_dram_init();
|
|
||||||
|
|
||||||
/* Clear the BSS. */
|
|
||||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
|
||||||
|
|
||||||
/* load/boot image from boot device */
|
|
||||||
board_init_r(NULL, 0);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|||||||
@@ -1,69 +0,0 @@
|
|||||||
CONFIG_ARM=y
|
|
||||||
CONFIG_ARCH_MX6=y
|
|
||||||
CONFIG_SYS_TEXT_BASE=0x87800000
|
|
||||||
CONFIG_SPL_GPIO_SUPPORT=y
|
|
||||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
|
||||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
|
||||||
CONFIG_TARGET_MX6SXSABRESD=y
|
|
||||||
CONFIG_ENV_SIZE=0x2000
|
|
||||||
CONFIG_ENV_OFFSET=0xE0000
|
|
||||||
CONFIG_DM_GPIO=y
|
|
||||||
CONFIG_SPL_MMC_SUPPORT=y
|
|
||||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
|
||||||
CONFIG_SPL=y
|
|
||||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
|
||||||
# CONFIG_CMD_BMODE is not set
|
|
||||||
CONFIG_NXP_BOARD_REVISION=y
|
|
||||||
CONFIG_SPL_TEXT_BASE=0x00908000
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
|
|
||||||
# CONFIG_CONSOLE_MUX is not set
|
|
||||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
|
||||||
CONFIG_SUPPORT_RAW_INITRD=y
|
|
||||||
CONFIG_BOUNCE_BUFFER=y
|
|
||||||
CONFIG_SPL_FS_EXT4=y
|
|
||||||
CONFIG_SPL_I2C_SUPPORT=y
|
|
||||||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
|
||||||
CONFIG_HUSH_PARSER=y
|
|
||||||
CONFIG_CMD_BOOTZ=y
|
|
||||||
CONFIG_CMD_GPIO=y
|
|
||||||
CONFIG_CMD_I2C=y
|
|
||||||
CONFIG_CMD_MMC=y
|
|
||||||
CONFIG_CMD_PCI=y
|
|
||||||
CONFIG_CMD_USB=y
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_CMD_DHCP=y
|
|
||||||
CONFIG_CMD_MII=y
|
|
||||||
CONFIG_CMD_PING=y
|
|
||||||
CONFIG_CMD_BMP=y
|
|
||||||
CONFIG_CMD_CACHE=y
|
|
||||||
CONFIG_CMD_TIME=y
|
|
||||||
CONFIG_CMD_EXT2=y
|
|
||||||
CONFIG_CMD_EXT4=y
|
|
||||||
CONFIG_CMD_EXT4_WRITE=y
|
|
||||||
CONFIG_CMD_FAT=y
|
|
||||||
CONFIG_CMD_FS_GENERIC=y
|
|
||||||
CONFIG_OF_CONTROL=y
|
|
||||||
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
|
|
||||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|
||||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
|
||||||
CONFIG_DM_I2C=y
|
|
||||||
CONFIG_DM_MMC=y
|
|
||||||
CONFIG_FSL_USDHC=y
|
|
||||||
CONFIG_PHYLIB=y
|
|
||||||
CONFIG_MII=y
|
|
||||||
CONFIG_PCI=y
|
|
||||||
CONFIG_PINCTRL=y
|
|
||||||
CONFIG_PINCTRL_IMX6=y
|
|
||||||
CONFIG_DM_PMIC=y
|
|
||||||
CONFIG_DM_PMIC_PFUZE100=y
|
|
||||||
CONFIG_DM_REGULATOR=y
|
|
||||||
CONFIG_DM_REGULATOR_PFUZE100=y
|
|
||||||
CONFIG_DM_REGULATOR_FIXED=y
|
|
||||||
CONFIG_DM_REGULATOR_GPIO=y
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_DM_USB=y
|
|
||||||
CONFIG_USB_STORAGE=y
|
|
||||||
CONFIG_USB_HOST_ETHER=y
|
|
||||||
CONFIG_USB_ETHER_ASIX=y
|
|
||||||
CONFIG_VIDEO=y
|
|
||||||
Reference in New Issue
Block a user