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net: mscc: Move ocelot_send and ocelot_recv in a different file.
This functions can be reused by other MSCC SoCs therefore, make them more generic and move them in separate files. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
This commit is contained in:
Horatiu Vultur
committed by
Daniel Schwierzeck
Daniel Schwierzeck
parent
2fff4a9b59
commit
36d04f52ff
@@ -1,2 +1,2 @@
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obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o
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obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o
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139
drivers/net/mscc_eswitch/mscc_xfer.c
Normal file
139
drivers/net/mscc_eswitch/mscc_xfer.c
Normal file
@@ -0,0 +1,139 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <linux/io.h>
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#include "mscc_xfer.h"
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#define QS_XTR_FLUSH_FLUSH GENMASK(1, 0)
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#define QS_INJ_CTRL_GAP_SIZE(x) ((x) << 21)
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#define QS_INJ_CTRL_EOF BIT(19)
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#define QS_INJ_CTRL_SOF BIT(18)
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#define QS_INJ_CTRL_VLD_BYTES(x) ((x) << 16)
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#define XTR_EOF_0 ntohl(0x80000000u)
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#define XTR_EOF_1 ntohl(0x80000001u)
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#define XTR_EOF_2 ntohl(0x80000002u)
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#define XTR_EOF_3 ntohl(0x80000003u)
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#define XTR_PRUNED ntohl(0x80000004u)
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#define XTR_ABORT ntohl(0x80000005u)
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#define XTR_ESCAPE ntohl(0x80000006u)
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#define XTR_NOT_READY ntohl(0x80000007u)
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#define BUF_CELL_SZ 60
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#define XTR_VALID_BYTES(x) (4 - ((x) & 3))
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int mscc_send(void __iomem *regs, const unsigned long *mscc_qs_offset,
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u32 *ifh, size_t ifh_len, u32 *buff, size_t buff_len)
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{
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int i, count = (buff_len + 3) / 4, last = buff_len % 4;
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writel(QS_INJ_CTRL_GAP_SIZE(1) | QS_INJ_CTRL_SOF,
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regs + mscc_qs_offset[MSCC_QS_INJ_CTRL]);
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for (i = 0; i < ifh_len; i++)
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writel(ifh[i], regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
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for (i = 0; i < count; i++)
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writel(buff[i], regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
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/* Add padding */
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while (i < (BUF_CELL_SZ / 4)) {
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writel(0, regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
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i++;
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}
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/* Indicate EOF and valid bytes in last word */
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writel(QS_INJ_CTRL_GAP_SIZE(1) |
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QS_INJ_CTRL_VLD_BYTES(buff_len < BUF_CELL_SZ ? 0 : last) |
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QS_INJ_CTRL_EOF, regs + mscc_qs_offset[MSCC_QS_INJ_CTRL]);
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/* Add dummy CRC */
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writel(0, regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
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return 0;
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}
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int mscc_recv(void __iomem *regs, const unsigned long *mscc_qs_offset,
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u32 *rxbuf, size_t ifh_len, bool byte_swap)
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{
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u8 grp = 0; /* Recv everything on CPU group 0 */
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int i, byte_cnt = 0;
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bool eof_flag = false, pruned_flag = false, abort_flag = false;
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if (!(readl(regs + mscc_qs_offset[MSCC_QS_XTR_DATA_PRESENT]) &
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BIT(grp)))
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return -EAGAIN;
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/* skip IFH */
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for (i = 0; i < ifh_len; i++)
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readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
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while (!eof_flag) {
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u32 val = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
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u32 cmp = val;
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if (byte_swap)
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cmp = ntohl(val);
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switch (cmp) {
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case XTR_NOT_READY:
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debug("%d NOT_READY...?\n", byte_cnt);
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break;
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case XTR_ABORT:
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*rxbuf = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
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abort_flag = true;
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eof_flag = true;
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debug("XTR_ABORT\n");
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break;
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case XTR_EOF_0:
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case XTR_EOF_1:
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case XTR_EOF_2:
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case XTR_EOF_3:
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byte_cnt += XTR_VALID_BYTES(val);
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*rxbuf = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
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eof_flag = true;
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debug("EOF\n");
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break;
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case XTR_PRUNED:
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/* But get the last 4 bytes as well */
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eof_flag = true;
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pruned_flag = true;
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debug("PRUNED\n");
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/* fallthrough */
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case XTR_ESCAPE:
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*rxbuf = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
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byte_cnt += 4;
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rxbuf++;
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debug("ESCAPED\n");
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break;
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default:
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*rxbuf = val;
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byte_cnt += 4;
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rxbuf++;
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}
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}
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if (abort_flag || pruned_flag || !eof_flag) {
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debug("Discarded frame: abort:%d pruned:%d eof:%d\n",
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abort_flag, pruned_flag, eof_flag);
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return -EAGAIN;
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}
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return byte_cnt;
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}
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void mscc_flush(void __iomem *regs, const unsigned long *mscc_qs_offset)
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{
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/* All Queues flush */
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setbits_le32(regs + mscc_qs_offset[MSCC_QS_XTR_FLUSH],
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QS_XTR_FLUSH_FLUSH);
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/* Allow to drain */
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mdelay(1);
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/* All Queues normal */
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clrbits_le32(regs + mscc_qs_offset[MSCC_QS_XTR_FLUSH],
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QS_XTR_FLUSH_FLUSH);
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}
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20
drivers/net/mscc_eswitch/mscc_xfer.h
Normal file
20
drivers/net/mscc_eswitch/mscc_xfer.h
Normal file
@@ -0,0 +1,20 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <common.h>
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enum mscc_regs_qs {
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MSCC_QS_XTR_RD,
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MSCC_QS_XTR_FLUSH,
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MSCC_QS_XTR_DATA_PRESENT,
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MSCC_QS_INJ_WR,
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MSCC_QS_INJ_CTRL,
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};
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int mscc_send(void __iomem *regs, const unsigned long *mscc_qs_offset,
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u32 *ifh, size_t ifh_len, u32 *buff, size_t buff_len);
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int mscc_recv(void __iomem *regs, const unsigned long *mscc_qs_offset,
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u32 *rxbuf, size_t ifh_len, bool byte_swap);
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void mscc_flush(void __iomem *regs, const unsigned long *mscc_qs_offset);
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@@ -16,6 +16,7 @@
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#include <wait_bit.h>
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#include "mscc_miim.h"
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#include "mscc_xfer.h"
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#define PHY_CFG 0x0
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#define PHY_CFG_ENA 0xF
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@@ -87,37 +88,16 @@
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#define QS_XTR_GRP_CFG_MODE(x) ((x) << 2)
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#define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)
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#define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
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#define QS_XTR_RD(x) (0x8 + 4 * (x))
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#define QS_XTR_FLUSH 0x18
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#define QS_XTR_FLUSH_FLUSH GENMASK(1, 0)
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#define QS_XTR_DATA_PRESENT 0x1c
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#define QS_INJ_GRP_CFG(x) (0x24 + (x) * 4)
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#define QS_INJ_GRP_CFG_MODE(x) ((x) << 2)
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#define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
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#define QS_INJ_WR(x) (0x2c + 4 * (x))
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#define QS_INJ_CTRL(x) (0x34 + 4 * (x))
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#define QS_INJ_CTRL_GAP_SIZE(x) ((x) << 21)
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#define QS_INJ_CTRL_EOF BIT(19)
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#define QS_INJ_CTRL_SOF BIT(18)
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#define QS_INJ_CTRL_VLD_BYTES(x) ((x) << 16)
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#define XTR_EOF_0 ntohl(0x80000000u)
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#define XTR_EOF_1 ntohl(0x80000001u)
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#define XTR_EOF_2 ntohl(0x80000002u)
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#define XTR_EOF_3 ntohl(0x80000003u)
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#define XTR_PRUNED ntohl(0x80000004u)
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#define XTR_ABORT ntohl(0x80000005u)
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#define XTR_ESCAPE ntohl(0x80000006u)
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#define XTR_NOT_READY ntohl(0x80000007u)
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#define IFH_INJ_BYPASS BIT(31)
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#define IFH_TAG_TYPE_C 0
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#define XTR_VALID_BYTES(x) (4 - ((x) & 3))
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#define MAC_VID 1
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#define CPU_PORT 11
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#define INTERNAL_PORT_MSK 0xF
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#define IFH_LEN 4
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#define OCELOT_BUF_CELL_SZ 60
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#define ETH_ALEN 6
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#define PGID_BROADCAST 13
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#define PGID_UNICAST 14
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@@ -181,6 +161,14 @@ struct ocelot_private {
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void *tx_adj_buf;
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};
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static const unsigned long ocelot_regs_qs[] = {
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[MSCC_QS_XTR_RD] = 0x8,
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[MSCC_QS_XTR_FLUSH] = 0x18,
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[MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
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[MSCC_QS_INJ_WR] = 0x2c,
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[MSCC_QS_INJ_CTRL] = 0x34,
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};
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struct mscc_miim_dev miim[NUM_PHY];
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static int mscc_miim_reset(struct mii_dev *bus)
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@@ -367,16 +355,6 @@ static int ocelot_switch_init(struct ocelot_private *priv)
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return 0;
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}
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static void ocelot_switch_flush(struct ocelot_private *priv)
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{
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/* All Queues flush */
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setbits_le32(priv->regs[QS] + QS_XTR_FLUSH, QS_XTR_FLUSH_FLUSH);
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/* Allow to drain */
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mdelay(1);
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/* All Queues normal */
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clrbits_le32(priv->regs[QS] + QS_XTR_FLUSH, QS_XTR_FLUSH_FLUSH);
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}
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static int ocelot_initialize(struct ocelot_private *priv)
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{
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int ret, i;
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@@ -394,7 +372,7 @@ static int ocelot_initialize(struct ocelot_private *priv)
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writel(0, priv->regs[ANA] + ANA_PGID(PGID_SRC + i));
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/* Flush queues */
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ocelot_switch_flush(priv);
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mscc_flush(priv->regs[QS], ocelot_regs_qs);
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/* Setup frame ageing - "2 sec" - The unit is 6.5us on Ocelot */
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writel(SYS_FRM_AGING_ENA | (20000000 / 65),
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@@ -503,13 +481,8 @@ static int ocelot_send(struct udevice *dev, void *packet, int length)
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struct ocelot_private *priv = dev_get_priv(dev);
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u32 ifh[IFH_LEN];
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int port = BIT(0); /* use port 0 */
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u8 grp = 0; /* Send everything on CPU group 0 */
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int i, count = (length + 3) / 4, last = length % 4;
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u32 *buf = packet;
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writel(QS_INJ_CTRL_GAP_SIZE(1) | QS_INJ_CTRL_SOF,
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priv->regs[QS] + QS_INJ_CTRL(grp));
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/*
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* Generate the IFH for frame injection
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*
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@@ -526,91 +499,18 @@ static int ocelot_send(struct udevice *dev, void *packet, int length)
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ifh[2] = (0xff & port) << 24;
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ifh[3] = (IFH_TAG_TYPE_C << 16);
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for (i = 0; i < IFH_LEN; i++)
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writel(ifh[i], priv->regs[QS] + QS_INJ_WR(grp));
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for (i = 0; i < count; i++)
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writel(buf[i], priv->regs[QS] + QS_INJ_WR(grp));
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/* Add padding */
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while (i < (OCELOT_BUF_CELL_SZ / 4)) {
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writel(0, priv->regs[QS] + QS_INJ_WR(grp));
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i++;
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}
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/* Indicate EOF and valid bytes in last word */
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writel(QS_INJ_CTRL_GAP_SIZE(1) |
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QS_INJ_CTRL_VLD_BYTES(length < OCELOT_BUF_CELL_SZ ? 0 : last) |
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QS_INJ_CTRL_EOF, priv->regs[QS] + QS_INJ_CTRL(grp));
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/* Add dummy CRC */
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writel(0, priv->regs[QS] + QS_INJ_WR(grp));
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return 0;
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return mscc_send(priv->regs[QS], ocelot_regs_qs,
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ifh, IFH_LEN, buf, length);
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}
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static int ocelot_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct ocelot_private *priv = dev_get_priv(dev);
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u8 grp = 0; /* Send everything on CPU group 0 */
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u32 *rxbuf = (u32 *)net_rx_packets[0];
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int i, byte_cnt = 0;
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bool eof_flag = false, pruned_flag = false, abort_flag = false;
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int byte_cnt;
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if (!(readl(priv->regs[QS] + QS_XTR_DATA_PRESENT) & BIT(grp)))
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return -EAGAIN;
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/* skip IFH */
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for (i = 0; i < IFH_LEN; i++)
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readl(priv->regs[QS] + QS_XTR_RD(grp));
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while (!eof_flag) {
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u32 val = readl(priv->regs[QS] + QS_XTR_RD(grp));
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switch (val) {
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case XTR_NOT_READY:
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debug("%d NOT_READY...?\n", byte_cnt);
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break;
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case XTR_ABORT:
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/* really nedeed?? not done in linux */
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*rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
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abort_flag = true;
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eof_flag = true;
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debug("XTR_ABORT\n");
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break;
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case XTR_EOF_0:
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case XTR_EOF_1:
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case XTR_EOF_2:
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case XTR_EOF_3:
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byte_cnt += XTR_VALID_BYTES(val);
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*rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
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eof_flag = true;
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debug("EOF\n");
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break;
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case XTR_PRUNED:
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/* But get the last 4 bytes as well */
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eof_flag = true;
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pruned_flag = true;
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debug("PRUNED\n");
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/* fallthrough */
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case XTR_ESCAPE:
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*rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
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byte_cnt += 4;
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rxbuf++;
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debug("ESCAPED\n");
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break;
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default:
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*rxbuf = val;
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byte_cnt += 4;
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rxbuf++;
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}
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}
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if (abort_flag || pruned_flag || !eof_flag) {
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debug("Discarded frame: abort:%d pruned:%d eof:%d\n",
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abort_flag, pruned_flag, eof_flag);
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return -EAGAIN;
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}
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byte_cnt = mscc_recv(priv->regs[QS], ocelot_regs_qs, rxbuf, IFH_LEN,
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false);
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*packetp = net_rx_packets[0];
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