dany/u-boot-megous
1
0
Fork 0
mirror of https://xff.cz/git/u-boot/ synced 2025-10-31 10:26:10 +01:00
Code Issues Packages Projects Releases Wiki Activity

dra7xx: Enable USB_PHY3 32KHz clock

Browse Source 
DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled
for USB1 instance in Super-Speed.

Signed-off-by: Roger Quadros <rogerq@ti.com>
This commit is contained in:
Roger Quadros
2016-05-23 17:37:49 +03:00
committed by Tom Rini
parent 55efadde7e
commit 3599774eec
3 changed files with 14 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
arch/arm/cpu/armv7/omap5/hw_data.c
View File

@@ -614,9 +614,14 @@ void enable_usb_clocks(int index)
setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
OPTFCLKEN_REFCLK960M); OPTFCLKEN_REFCLK960M);
/* Enable 32 KHz clock for dwc3 */ /* Enable 32 KHz clock for USB_PHY1 */
setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
/* Enable 32 KHz clock for USB_PHY3 */
if (is_dra7xx())
setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
} else if (index == 1) { } else if (index == 1) {
cm_l3init_usb_otg_ss_clkctrl = cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss2_clkctrl; (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
@@ -664,9 +669,14 @@ void disable_usb_clocks(int index)
clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
OPTFCLKEN_REFCLK960M); OPTFCLKEN_REFCLK960M);
/* Disable 32 KHz clock for dwc3 */ /* Disable 32 KHz clock for USB_PHY1 */
clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
/* Disable 32 KHz clock for USB_PHY3 */
if (is_dra7xx())
clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
} else if (index == 1) { } else if (index == 1) {
cm_l3init_usb_otg_ss_clkctrl = cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss2_clkctrl; (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;

1
arch/arm/cpu/armv7/omap5/prcm-regs.c
View File

@@ -820,6 +820,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_clkmode_dpll_gmac = 0x4a0052a8, .cm_clkmode_dpll_gmac = 0x4a0052a8,
.cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640, .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640,
.cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688, .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
.cm_coreaon_usb_phy3_core_clkctrl = 0x4a008698,
.cm_coreaon_l3init_60m_gfclk_clkctrl = 0x4a0086c0, .cm_coreaon_l3init_60m_gfclk_clkctrl = 0x4a0086c0,
/* cm1.mpu */ /* cm1.mpu */

1
arch/arm/include/asm/omap_common.h
View File

@@ -145,6 +145,7 @@ struct prcm_regs {
u32 cm_ssc_modfreqdiv_dpll_unipro; u32 cm_ssc_modfreqdiv_dpll_unipro;
u32 cm_coreaon_usb_phy1_core_clkctrl; u32 cm_coreaon_usb_phy1_core_clkctrl;
u32 cm_coreaon_usb_phy2_core_clkctrl; u32 cm_coreaon_usb_phy2_core_clkctrl;
u32 cm_coreaon_usb_phy3_core_clkctrl;
u32 cm_coreaon_l3init_60m_gfclk_clkctrl; u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
/* cm2.core */ /* cm2.core */