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driver/ddr/fsl: Add DDR4 support to Freescale DDR driver
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun
@@ -1,5 +1,5 @@
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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* Copyright 2008-2014 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@@ -290,11 +290,220 @@ typedef struct ddr3_spd_eeprom_s {
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} ddr3_spd_eeprom_t;
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/* From JEEC Standard No. 21-C release 23A */
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struct ddr4_spd_eeprom_s {
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/* General Section: Bytes 0-127 */
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uint8_t info_size_crc; /* 0 # bytes */
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uint8_t spd_rev; /* 1 Total # bytes of SPD */
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uint8_t mem_type; /* 2 Key Byte / mem type */
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uint8_t module_type; /* 3 Key Byte / Module Type */
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uint8_t density_banks; /* 4 Density and Banks */
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uint8_t addressing; /* 5 Addressing */
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uint8_t package_type; /* 6 Package type */
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uint8_t opt_feature; /* 7 Optional features */
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uint8_t thermal_ref; /* 8 Thermal and refresh */
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uint8_t oth_opt_features; /* 9 Other optional features */
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uint8_t res_10; /* 10 Reserved */
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uint8_t module_vdd; /* 11 Module nominal voltage */
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uint8_t organization; /* 12 Module Organization */
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uint8_t bus_width; /* 13 Module Memory Bus Width */
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uint8_t therm_sensor; /* 14 Module Thermal Sensor */
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uint8_t ext_type; /* 15 Extended module type */
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uint8_t res_16;
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uint8_t timebases; /* 17 MTb and FTB */
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uint8_t tck_min; /* 18 tCKAVGmin */
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uint8_t tck_max; /* 19 TCKAVGmax */
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uint8_t caslat_b1; /* 20 CAS latencies, 1st byte */
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uint8_t caslat_b2; /* 21 CAS latencies, 2nd byte */
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uint8_t caslat_b3; /* 22 CAS latencies, 3rd byte */
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uint8_t caslat_b4; /* 23 CAS latencies, 4th byte */
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uint8_t taa_min; /* 24 Min CAS Latency Time */
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uint8_t trcd_min; /* 25 Min RAS# to CAS# Delay Time */
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uint8_t trp_min; /* 26 Min Row Precharge Delay Time */
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uint8_t tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */
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uint8_t tras_min_lsb; /* 28 tRASmin, lsb */
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uint8_t trc_min_lsb; /* 29 tRCmin, lsb */
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uint8_t trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */
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uint8_t trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */
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uint8_t trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */
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uint8_t trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */
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uint8_t trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */
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uint8_t trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */
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uint8_t tfaw_msb; /* 36 Upper Nibble for tFAW */
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uint8_t tfaw_min; /* 37 tFAW, lsb */
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uint8_t trrds_min; /* 38 tRRD_Smin, MTB */
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uint8_t trrdl_min; /* 39 tRRD_Lmin, MTB */
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uint8_t tccdl_min; /* 40 tCCS_Lmin, MTB */
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uint8_t res_41[60-41]; /* 41 Rserved */
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uint8_t mapping[78-60]; /* 60~77 Connector to SDRAM bit map */
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uint8_t res_78[117-78]; /* 78~116, Reserved */
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int8_t fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */
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int8_t fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */
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int8_t fine_trrds_min; /* 119 Fine offset for tRRD_Smin */
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int8_t fine_trc_min; /* 120 Fine offset for tRCmin */
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int8_t fine_trp_min; /* 121 Fine offset for tRPmin */
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int8_t fine_trcd_min; /* 122 Fine offset for tRCDmin */
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int8_t fine_taa_min; /* 123 Fine offset for tAAmin */
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int8_t fine_tck_max; /* 124 Fine offset for tCKAVGmax */
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int8_t fine_tck_min; /* 125 Fine offset for tCKAVGmin */
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/* CRC: Bytes 126-127 */
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uint8_t crc[2]; /* 126-127 SPD CRC */
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/* Module-Specific Section: Bytes 128-255 */
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union {
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struct {
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/* 128 (Unbuffered) Module Nominal Height */
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uint8_t mod_height;
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/* 129 (Unbuffered) Module Maximum Thickness */
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uint8_t mod_thickness;
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/* 130 (Unbuffered) Reference Raw Card Used */
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uint8_t ref_raw_card;
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/* 131 (Unbuffered) Address Mapping from
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Edge Connector to DRAM */
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uint8_t addr_mapping;
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/* 132~253 (Unbuffered) Reserved */
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uint8_t res_132[254-132];
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/* 254~255 CRC */
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uint8_t crc[2];
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} unbuffered;
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struct {
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/* 128 (Registered) Module Nominal Height */
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uint8_t mod_height;
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/* 129 (Registered) Module Maximum Thickness */
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uint8_t mod_thickness;
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/* 130 (Registered) Reference Raw Card Used */
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uint8_t ref_raw_card;
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/* 131 DIMM Module Attributes */
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uint8_t modu_attr;
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/* 132 RDIMM Thermal Heat Spreader Solution */
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uint8_t thermal;
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/* 133 Register Manufacturer ID Code, LSB */
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uint8_t reg_id_lo;
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/* 134 Register Manufacturer ID Code, MSB */
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uint8_t reg_id_hi;
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/* 135 Register Revision Number */
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uint8_t reg_rev;
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/* 136 Address mapping from register to DRAM */
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uint8_t reg_map;
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/* 137~253 Reserved */
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uint8_t res_137[254-137];
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/* 254~255 CRC */
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uint8_t crc[2];
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} registered;
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struct {
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/* 128 (Loadreduced) Module Nominal Height */
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uint8_t mod_height;
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/* 129 (Loadreduced) Module Maximum Thickness */
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uint8_t mod_thickness;
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/* 130 (Loadreduced) Reference Raw Card Used */
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uint8_t ref_raw_card;
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/* 131 DIMM Module Attributes */
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uint8_t modu_attr;
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/* 132 RDIMM Thermal Heat Spreader Solution */
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uint8_t thermal;
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/* 133 Register Manufacturer ID Code, LSB */
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uint8_t reg_id_lo;
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/* 134 Register Manufacturer ID Code, MSB */
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uint8_t reg_id_hi;
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/* 135 Register Revision Number */
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uint8_t reg_rev;
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/* 136 Address mapping from register to DRAM */
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uint8_t reg_map;
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/* 137 Register Output Drive Strength for CMD/Add*/
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uint8_t reg_drv;
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/* 138 Register Output Drive Strength for CK */
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uint8_t reg_drv_ck;
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/* 139 Data Buffer Revision Number */
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uint8_t data_buf_rev;
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/* 140 DRAM VrefDQ for Package Rank 0 */
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uint8_t vrefqe_r0;
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/* 141 DRAM VrefDQ for Package Rank 1 */
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uint8_t vrefqe_r1;
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/* 142 DRAM VrefDQ for Package Rank 2 */
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uint8_t vrefqe_r2;
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/* 143 DRAM VrefDQ for Package Rank 3 */
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uint8_t vrefqe_r3;
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/* 144 Data Buffer VrefDQ for DRAM Interface */
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uint8_t data_intf;
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/*
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* 145 Data Buffer MDQ Drive Strength and RTT
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* for data rate <= 1866
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*/
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uint8_t data_drv_1866;
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/*
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* 146 Data Buffer MDQ Drive Strength and RTT
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* for 1866 < data rate <= 2400
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*/
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uint8_t data_drv_2400;
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/*
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* 147 Data Buffer MDQ Drive Strength and RTT
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* for 2400 < data rate <= 3200
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*/
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uint8_t data_drv_3200;
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/* 148 DRAM Drive Strength */
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uint8_t dram_drv;
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/*
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* 149 DRAM ODT (RTT_WR, RTT_NOM)
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* for data rate <= 1866
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*/
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uint8_t dram_odt_1866;
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/*
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* 150 DRAM ODT (RTT_WR, RTT_NOM)
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* for 1866 < data rate <= 2400
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*/
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uint8_t dram_odt_2400;
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/*
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* 151 DRAM ODT (RTT_WR, RTT_NOM)
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* for 2400 < data rate <= 3200
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*/
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uint8_t dram_odt_3200;
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/*
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* 152 DRAM ODT (RTT_PARK)
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* for data rate <= 1866
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*/
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uint8_t dram_odt_park_1866;
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/*
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* 153 DRAM ODT (RTT_PARK)
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* for 1866 < data rate <= 2400
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*/
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uint8_t dram_odt_park_2400;
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/*
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* 154 DRAM ODT (RTT_PARK)
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* for 2400 < data rate <= 3200
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*/
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uint8_t dram_odt_park_3200;
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uint8_t res_155[254-155]; /* Reserved */
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/* 254~255 CRC */
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uint8_t crc[2];
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} loadreduced;
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uint8_t uc[128]; /* 128-255 Module-Specific Section */
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} mod_section;
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uint8_t res_256[320-256]; /* 256~319 Reserved */
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/* Module supplier's data: Byte 320~383 */
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uint8_t mmid_lsb; /* 320 Module MfgID Code LSB */
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uint8_t mmid_msb; /* 321 Module MfgID Code MSB */
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uint8_t mloc; /* 322 Mfg Location */
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uint8_t mdate[2]; /* 323~324 Mfg Date */
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uint8_t sernum[4]; /* 325~328 Module Serial Number */
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uint8_t mpart[20]; /* 329~348 Mfg's Module Part Number */
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uint8_t mrev; /* 349 Module Revision Code */
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uint8_t dmid_lsb; /* 350 DRAM MfgID Code LSB */
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uint8_t dmid_msb; /* 351 DRAM MfgID Code MSB */
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uint8_t stepping; /* 352 DRAM stepping */
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uint8_t msd[29]; /* 353~381 Mfg's Specific Data */
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uint8_t res_382[2]; /* 382~383 Reserved */
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uint8_t user[512-384]; /* 384~511 End User Programmable */
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};
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extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd);
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extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd);
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extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd);
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extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd);
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extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
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unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd);
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/*
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* Byte 2 Fundamental Memory Types.
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@@ -310,6 +519,7 @@ extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
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#define SPD_MEMTYPE_DDR2_FBDIMM (0x09)
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#define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A)
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#define SPD_MEMTYPE_DDR3 (0x0B)
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#define SPD_MEMTYPE_DDR4 (0x0C)
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/* DIMM Type for DDR2 SPD (according to v1.3) */
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#define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00)
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@@ -338,4 +548,18 @@ extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
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#define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C)
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#define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D)
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/* DIMM Type for DDR4 SPD */
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#define DDR4_SPD_MODULETYPE_MASK (0x0f)
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#define DDR4_SPD_MODULETYPE_EXT (0x00)
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#define DDR4_SPD_MODULETYPE_RDIMM (0x01)
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#define DDR4_SPD_MODULETYPE_UDIMM (0x02)
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#define DDR4_SPD_MODULETYPE_SO_DIMM (0x03)
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#define DDR4_SPD_MODULETYPE_LRDIMM (0x04)
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#define DDR4_SPD_MODULETYPE_MINI_RDIMM (0x05)
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#define DDR4_SPD_MODULETYPE_MINI_UDIMM (0x06)
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#define DDR4_SPD_MODULETYPE_72B_SO_UDIMM (0x08)
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#define DDR4_SPD_MODULETYPE_72B_SO_RDIMM (0x09)
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#define DDR4_SPD_MODULETYPE_16B_SO_DIMM (0x0C)
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#define DDR4_SPD_MODULETYPE_32B_SO_DIMM (0x0D)
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#endif /* _DDR_SPD_H_ */
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