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rockchip: rk3568: Read cpuid from otp

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The cpuid on RK3568 is located at 0xa instead of 0x7 as all other SoCs.
Add and use a CFG_CPUID_OFFSET to define this offset.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jonas Karlman
2023-02-22 22:44:41 +00:00
committed by Kever Yang
parent 628fb0683b
commit 2eedb6d93f
5 changed files with 21 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/dts/rk356x-u-boot.dtsi
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@@ -20,6 +20,18 @@
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
status = "okay"; status = "okay";
}; };
otp: nvmem@fe38c000 {
compatible = "rockchip,rk3568-otp";
reg = <0x0 0xfe38c000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
cpu_id: id@a {
reg = <0x0a 0x10>;
};
};
}; };
&combphy1 { &combphy1 {

2
arch/arm/mach-rockchip/Kconfig
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@@ -289,6 +289,8 @@ config ROCKCHIP_RK3568
select DM_REGULATOR_FIXED select DM_REGULATOR_FIXED
select DM_RESET select DM_RESET
imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_OTP
imply MISC_INIT_R
help help
The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55, The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
including NEON and GPU, 512K L3 cache, Mali-G52 based graphics, including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,

2
arch/arm/mach-rockchip/board.c
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@@ -323,7 +323,7 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
#ifdef CONFIG_MISC_INIT_R #ifdef CONFIG_MISC_INIT_R
__weak int misc_init_r(void) __weak int misc_init_r(void)
{ {
const u32 cpuid_offset = 0x7; const u32 cpuid_offset = CFG_CPUID_OFFSET;
const u32 cpuid_length = 0x10; const u32 cpuid_length = 0x10;
u8 cpuid[cpuid_length]; u8 cpuid[cpuid_length];
int ret; int ret;

2
include/configs/rk3568_common.h
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@@ -6,6 +6,8 @@
#ifndef __CONFIG_RK3568_COMMON_H #ifndef __CONFIG_RK3568_COMMON_H
#define __CONFIG_RK3568_COMMON_H #define __CONFIG_RK3568_COMMON_H
#define CFG_CPUID_OFFSET 0xa
#include "rockchip-common.h" #include "rockchip-common.h"
#define CFG_IRAM_BASE 0xfdcc0000 #define CFG_IRAM_BASE 0xfdcc0000

4
include/configs/rockchip-common.h
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@@ -7,6 +7,10 @@
#define _ROCKCHIP_COMMON_H_ #define _ROCKCHIP_COMMON_H_
#include <linux/sizes.h> #include <linux/sizes.h>
#ifndef CFG_CPUID_OFFSET
#define CFG_CPUID_OFFSET 0x7
#endif
/* ((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512) */ /* ((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512) */
#ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SPL_BUILD