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arm: socfpga: move gen5 SDR driver to DM

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To clean up reset handling for socfpga gen5, port the DDR driver to DM
using UCLASS_RAM and implement proper reset handling.

This gets us rid of one ad-hoc call to socfpga_per_reset().

The gen5 driver is implemented in 2 distinct files. One of it (containing
the calibration training) is not touched much and is kept at using
hard coded addresses since the code grows even more otherwise.

SPL is changed from calling hard into the DDR driver code to just
probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM
driver after that.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This commit is contained in:
Simon Goldschmidt
2019-04-16 22:04:39 +02:00
committed by Marek Vasut
parent ede6e7b64f
commit 29873c74f3
7 changed files with 184 additions and 42 deletions
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35
drivers/ddr/altera/sequencer.h
View File

@@ -223,4 +223,39 @@ struct socfpga_data_mgr {
u32 mem_t_add;
u32 t_rl_add;
};
/* This struct describes the controller @ SOCFPGA_SDR_ADDRESS */
struct socfpga_sdr {
/* SDR_PHYGRP_SCCGRP_ADDRESS */
u8 _align1[0xe00];
/* SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00 */
struct socfpga_sdr_scc_mgr sdr_scc_mgr;
u8 _align2[0x1bc];
/* SDR_PHYGRP_PHYMGRGRP_ADDRESS */
struct socfpga_phy_mgr_cmd phy_mgr_cmd;
u8 _align3[0x2c];
/* SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40 */
struct socfpga_phy_mgr_cfg phy_mgr_cfg;
u8 _align4[0xfa0];
/* SDR_PHYGRP_RWMGRGRP_ADDRESS */
u8 rwmgr_grp[0x800];
/* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800 */
struct socfpga_sdr_rw_load_manager sdr_rw_load_mgr_regs;
u8 _align5[0x3f0];
/* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00 */
struct socfpga_sdr_rw_load_jump_manager sdr_rw_load_jump_mgr_regs;
u8 _align6[0x13f0];
/* SDR_PHYGRP_DATAMGRGRP_ADDRESS */
struct socfpga_data_mgr data_mgr;
u8 _align7[0x7f0];
/* SDR_PHYGRP_REGFILEGRP_ADDRESS */
struct socfpga_sdr_reg_file sdr_reg_file;
u8 _align8[0x7c8];
/* SDR_CTRLGRP_ADDRESS */
struct socfpga_sdr_ctrl sdr_ctrl;
u8 _align9[0xea4];
};
int sdram_calibration_full(struct socfpga_sdr *sdr);
#endif /* _SEQUENCER_H_ */