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arm64: versal: fpga: Add PL bit stream load support

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This patch adds PL bitstream load support for Versal platform. The PL
bitstream is loaded by making an SMC to ATF which in turn communicates
with platform firmware which configures and loads PL bitstream on to PL.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Siva Durga Prasad Paladugu
2019-08-05 15:54:59 +05:30
committed by Michal Simek
parent 13210cd951
commit 26e054c943
7 changed files with 100 additions and 1 deletions
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2
include/xilinx.h
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@@ -21,6 +21,7 @@ typedef enum { /* typedef xilinx_iface */
slave_selectmap, /* slave SelectMap (virtex2) */
devcfg, /* devcfg interface (zynq) */
csu_dma, /* csu_dma interface (zynqmp) */
cfi, /* CFI interface(versal) */
max_xilinx_iface_type /* insert all new types before this */
} xilinx_iface; /* end, typedef xilinx_iface */
@@ -32,6 +33,7 @@ typedef enum { /* typedef xilinx_family */
xilinx_spartan3, /* Spartan-III Family */
xilinx_zynq, /* Zynq Family */
xilinx_zynqmp, /* ZynqMP Family */
xilinx_versal, /* Versal Family */
max_xilinx_type /* insert all new types before this */
} xilinx_family; /* end, typedef xilinx_family */