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mtd: Drop unused fsl_upm driver
This is not used since this commit:
8d1e3cb140 powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support
Drop the driver and Kconfig option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
This commit is contained in:
Simon Glass
Tom Rini
@@ -56,7 +56,6 @@ obj-$(CONFIG_NAND_DENALI) += denali.o
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obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o
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obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
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obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
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obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
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obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o
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obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
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obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
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@@ -1,187 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* FSL UPM NAND driver
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*/
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#include <config.h>
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#include <common.h>
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#include <log.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/fsl_upm.h>
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#include <nand.h>
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static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
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{
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clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
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(void)in_be32(upm->mxmr);
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}
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static void fsl_upm_end_pattern(struct fsl_upm *upm)
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{
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clrbits_be32(upm->mxmr, MxMR_OP_RUNP);
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while (in_be32(upm->mxmr) & MxMR_OP_RUNP)
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eieio();
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}
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static void fsl_upm_run_pattern(struct fsl_upm *upm, int width,
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void __iomem *io_addr, u32 mar)
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{
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out_be32(upm->mar, mar);
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(void)in_be32(upm->mar);
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switch (width) {
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case 8:
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out_8(io_addr, 0x0);
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break;
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case 16:
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out_be16(io_addr, 0x0);
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break;
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case 32:
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out_be32(io_addr, 0x0);
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break;
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}
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}
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static void fun_wait(struct fsl_upm_nand *fun)
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{
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if (fun->dev_ready) {
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while (!fun->dev_ready(fun->chip_nr))
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debug("unexpected busy state\n");
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} else {
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/*
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* If the R/B pin is not connected,
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* a short delay is necessary.
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*/
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udelay(1);
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}
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}
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#if CONFIG_SYS_NAND_MAX_CHIPS > 1
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static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct fsl_upm_nand *fun = nand_get_controller_data(chip);
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if (chip_nr >= 0) {
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fun->chip_nr = chip_nr;
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chip->IO_ADDR_R = chip->IO_ADDR_W =
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fun->upm.io_addr + fun->chip_offset * chip_nr;
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} else if (chip_nr == -1) {
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chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
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}
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}
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#endif
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static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct fsl_upm_nand *fun = nand_get_controller_data(chip);
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void __iomem *io_addr;
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u32 mar;
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if (!(ctrl & fun->last_ctrl)) {
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fsl_upm_end_pattern(&fun->upm);
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if (cmd == NAND_CMD_NONE)
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return;
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fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
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}
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_ALE)
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fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
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else if (ctrl & NAND_CLE)
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fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
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}
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mar = cmd << (32 - fun->width);
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io_addr = fun->upm.io_addr;
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#if CONFIG_SYS_NAND_MAX_CHIPS > 1
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if (fun->chip_nr > 0) {
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io_addr += fun->chip_offset * fun->chip_nr;
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if (fun->upm_mar_chip_offset)
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mar |= fun->upm_mar_chip_offset * fun->chip_nr;
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}
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#endif
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fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
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/*
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* Some boards/chips needs this. At least the MPC8360E-RDK
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* needs it. Probably weird chip, because I don't see any
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* need for this on MPC8555E + Samsung K9F1G08U0A. Usually
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* here are 0-2 unexpected busy states per block read.
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*/
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if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
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fun_wait(fun);
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}
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static u8 upm_nand_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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return in_8(chip->IO_ADDR_R);
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}
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static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct fsl_upm_nand *fun = nand_get_controller_data(chip);
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for (i = 0; i < len; i++) {
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out_8(chip->IO_ADDR_W, buf[i]);
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if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
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fun_wait(fun);
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}
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if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
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fun_wait(fun);
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}
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static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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struct nand_chip *chip = mtd_to_nand(mtd);
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for (i = 0; i < len; i++)
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buf[i] = in_8(chip->IO_ADDR_R);
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}
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static int nand_dev_ready(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct fsl_upm_nand *fun = nand_get_controller_data(chip);
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return fun->dev_ready(fun->chip_nr);
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}
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int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
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{
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if (fun->width != 8 && fun->width != 16 && fun->width != 32)
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return -ENOSYS;
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fun->last_ctrl = NAND_CLE;
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nand_set_controller_data(chip, fun);
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chip->chip_delay = fun->chip_delay;
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chip->ecc.mode = NAND_ECC_SOFT;
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chip->cmd_ctrl = fun_cmd_ctrl;
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#if CONFIG_SYS_NAND_MAX_CHIPS > 1
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chip->select_chip = fun_select_chip;
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#endif
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chip->read_byte = upm_nand_read_byte;
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chip->read_buf = upm_nand_read_buf;
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chip->write_buf = upm_nand_write_buf;
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if (fun->dev_ready)
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chip->dev_ready = nand_dev_ready;
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return 0;
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}
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@@ -1,44 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* FSL UPM NAND driver
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*/
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#ifndef __LINUX_MTD_NAND_FSL_UPM
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#define __LINUX_MTD_NAND_FSL_UPM
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#include <linux/mtd/rawnand.h>
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#define FSL_UPM_WAIT_RUN_PATTERN 0x1
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#define FSL_UPM_WAIT_WRITE_BYTE 0x2
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#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
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struct fsl_upm {
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void __iomem *mdr;
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void __iomem *mxmr;
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void __iomem *mar;
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void __iomem *io_addr;
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};
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struct fsl_upm_nand {
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struct fsl_upm upm;
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int width;
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int upm_cmd_offset;
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int upm_addr_offset;
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int upm_mar_chip_offset;
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int wait_flags;
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int (*dev_ready)(int chip_nr);
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int chip_delay;
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int chip_offset;
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int chip_nr;
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/* no need to fill */
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int last_ctrl;
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};
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extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun);
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#endif
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