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ddr: marvell: a38x: Allow boards to specify CK_DELAY parameter

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For some layouts it is necessary to adjust the CK_DELAY parameter to
successfully complete DDR training. Add the ability to specify the
CK_DELAY in the mv_ddr_topology_map.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
This commit is contained in:
Chris Packham
2020-01-30 12:50:44 +13:00
committed by Stefan Roese
parent 8914831860
commit 236609d93c
5 changed files with 24 additions and 1 deletions
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6
board/alliedtelesis/x530/x530.c
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@@ -66,7 +66,11 @@ static struct mv_ddr_topology_map board_topology_map = {
BUS_MASK_32BIT_ECC, /* subphys mask */ BUS_MASK_32BIT_ECC, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */ { {0} }, /* raw spd data */
{0} /* timing parameters */ {0}, /* timing parameters */
{ {0} }, /* electrical configuration */
{0}, /* electrical parameters */
0, /* Clock enable mask */
160 /* Clock delay */
}; };
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)

5
drivers/ddr/marvell/a38x/ddr3_init.c
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@@ -106,8 +106,10 @@ static int mv_ddr_training_params_set(u8 dev_num)
struct tune_train_params params; struct tune_train_params params;
int status; int status;
u32 cs_num; u32 cs_num;
int ck_delay;
cs_num = mv_ddr_cs_num_get(); cs_num = mv_ddr_cs_num_get();
ck_delay = mv_ddr_ck_delay_get();
/* NOTE: do not remove any field initilization */ /* NOTE: do not remove any field initilization */
params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY; params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY;
@@ -131,6 +133,9 @@ static int mv_ddr_training_params_set(u8 dev_num)
params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS; params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS;
} }
if (ck_delay > 0)
params.ck_delay = ck_delay;
status = ddr3_tip_tune_training_params(dev_num, &params); status = ddr3_tip_tune_training_params(dev_num, &params);
if (MV_OK != status) { if (MV_OK != status) {
printf("%s Training Sequence - FAILED\n", ddr_type); printf("%s Training Sequence - FAILED\n", ddr_type);

3
drivers/ddr/marvell/a38x/ddr_topology_def.h
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@@ -127,6 +127,9 @@ struct mv_ddr_topology_map {
/* Clock enable mask */ /* Clock enable mask */
u32 clk_enable; u32 clk_enable;
/* Clock delay */
int ck_delay;
}; };
enum mv_ddr_iface_mode { enum mv_ddr_iface_mode {

10
drivers/ddr/marvell/a38x/mv_ddr_topology.c
View File

@@ -229,6 +229,16 @@ int mv_ddr_is_ecc_ena(void)
return 0; return 0;
} }
int mv_ddr_ck_delay_get(void)
{
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
if (tm->ck_delay)
return tm->ck_delay;
return -1;
}
/* translate topology map definition to real memory size in bits */ /* translate topology map definition to real memory size in bits */
static unsigned int mem_size[] = { static unsigned int mem_size[] = {
ADDR_SIZE_512MB, ADDR_SIZE_512MB,

1
drivers/ddr/marvell/a38x/mv_ddr_topology.h
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@@ -319,6 +319,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void);
unsigned int mv_ddr_if_bus_width_get(void); unsigned int mv_ddr_if_bus_width_get(void);
unsigned int mv_ddr_cs_num_get(void); unsigned int mv_ddr_cs_num_get(void);
int mv_ddr_is_ecc_ena(void); int mv_ddr_is_ecc_ena(void);
int mv_ddr_ck_delay_get(void);
unsigned long long mv_ddr_mem_sz_per_cs_get(void); unsigned long long mv_ddr_mem_sz_per_cs_get(void);
unsigned long long mv_ddr_mem_sz_get(void); unsigned long long mv_ddr_mem_sz_get(void);
unsigned int mv_ddr_rtt_nom_get(void); unsigned int mv_ddr_rtt_nom_get(void);