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ddr: altera: sequencer: Pluck out RW_MGR_* macros from code

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Actually convert the sequencer code to use socfpga_sdram_rw_mgr_config
instead of the RW_MGR_* macros. This is just an sed exercise here, no
manual coding needed.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
This commit is contained in:
Marek Vasut
2015-08-02 18:44:06 +02:00
parent d718a26b0c
commit 1fa0c8c4e3
2 changed files with 153 additions and 153 deletions
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14
drivers/ddr/altera/sequencer.h
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@@ -7,14 +7,14 @@
#ifndef _SEQUENCER_H_
#define _SEQUENCER_H_
#define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH \
/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH \
/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
#define RW_MGR_NUM_DM_PER_WRITE_GROUP (rwcfg->mem_data_mask_width \
/ rwcfg->mem_if_write_dqs_width)
#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (rwcfg->true_mem_data_mask_width \
/ rwcfg->mem_if_write_dqs_width)
#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH \
/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
#define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS)
#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (rwcfg->mem_if_read_dqs_width \
/ rwcfg->mem_if_write_dqs_width)
#define NUM_RANKS_PER_SHADOW_REG (rwcfg->mem_number_of_ranks / NUM_SHADOW_REGS)
#define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0
#define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400