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lx2160aqds : Add support for LX2160AQDS platform

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LX2160AQDS is a development board that supports LX2160A
family SoCs. This patch add base support for this board.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
[PK: Sqaush patch for "secure boot defconfig" & add maintainer]
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Pankaj Bansal
2019-02-08 10:29:58 +00:00
committed by Prabhakar Kushwaha
parent edc975b8aa
commit 1eba723c72
14 changed files with 1526 additions and 3 deletions
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10
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@@ -2,7 +2,7 @@
/*
* LayerScape Internal Memory Map
*
* Copyright 2017-2018 NXP
* Copyright 2017-2019 NXP
* Copyright 2014 Freescale Semiconductor, Inc.
*/
@@ -350,6 +350,14 @@ struct ccsr_gur {
#define FSL_CHASSIS3_SRDS1_REGSR 29
#define FSL_CHASSIS3_SRDS2_REGSR 29
#define FSL_CHASSIS3_SRDS3_REGSR 29
#define FSL_CHASSIS3_RCWSR12_REGSR 12
#define FSL_CHASSIS3_RCWSR13_REGSR 13
#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000
#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24
#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038
#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3
#define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00
#define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9
#elif defined(CONFIG_ARCH_LS1088A)
#define FSL_CHASSIS3_EC1_REGSR 26
#define FSL_CHASSIS3_EC2_REGSR 26