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ARM: DRA7/ OMAP5: implement Auxiliary Control Register configuration

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Implement logic for ACR(Auxiliary Control Register) configuration using
ROM Code smc service.

Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Nishanth Menon
2015-07-27 16:26:06 -05:00
committed by Tom Rini
parent a615d0be6a
commit 1bbb556a6a
2 changed files with 7 additions and 0 deletions
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6
arch/arm/cpu/armv7/omap5/hwinit.c
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@@ -418,3 +418,9 @@ void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
{
omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
}
void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
u32 cpu_variant, u32 cpu_rev)
{
omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
}

1
arch/arm/include/asm/arch-omap5/sys_proto.h
View File

@@ -81,5 +81,6 @@ static inline u32 usec_to_32k(u32 usec)
}
#define OMAP5_SERVICE_L2ACTLR_SET 0x104
#define OMAP5_SERVICE_ACR_SET 0x107
#endif