dany/u-boot-megous
1
0
Fork 0
mirror of https://xff.cz/git/u-boot/ synced 2025-10-01 15:31:27 +02:00
Code Issues Packages Projects Releases Wiki Activity

powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards

Browse Source 
P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
York Sun
2012-02-29 12:36:51 +00:00
committed by Andy Fleming
parent 119a55f9cf
commit 1ba62f1017
4 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
board/freescale/p1_p2_rdb_pc/ddr.c
View File

@@ -15,7 +15,7 @@
#include <asm/io.h>
#include <asm/fsl_law.h>
#ifdef CONFIG_DDR_RAW_TIMING
#ifdef CONFIG_SYS_DDR_RAW_TIMING
#if defined(CONFIG_P1020RDB_PROTO) || \
defined(CONFIG_P1021RDB) || \
defined(CONFIG_P1020UTM)
@@ -204,7 +204,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
return 0;
}
#endif /* CONFIG_DDR_RAW_TIMING */
#endif /* CONFIG_SYS_DDR_RAW_TIMING */
/* Fixed sdram init -- doesn't use serial presence detect. */
phys_size_t fixed_sdram(void)