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powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards

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P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
York Sun
2012-02-29 12:36:51 +00:00
committed by Andy Fleming
parent 119a55f9cf
commit 1ba62f1017
4 changed files with 7 additions and 7 deletions
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6
board/freescale/p1010rdb/ddr.c
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@@ -31,7 +31,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_DDR_RAW_TIMING
#ifndef CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_DRAM_SIZE 1024
fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
@@ -165,7 +165,7 @@ phys_size_t fixed_sdram(void)
return ddr_size;
}
#else /* CONFIG_DDR_RAW_TIMING */
#else /* CONFIG_SYS_DDR_RAW_TIMING */
/*
* Samsung K4B2G0846C-HCF8
* The following timing are for "downshift"
@@ -247,4 +247,4 @@ void fsl_ddr_board_options(memctl_options_t *popts,
}
}
#endif /* CONFIG_DDR_RAW_TIMING */
#endif /* CONFIG_SYS_DDR_RAW_TIMING */