Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh into next

arch/arm/mach-rmobile/Kconfig

@@ -1,5 +1,22 @@
 if ARCH_RMOBILE
 
+# Renesas ARM SoCs R-Car Gen3/Gen4 (64bit)
+config RCAR_64
+	bool
+	select ARM64
+	select CMD_CACHE
+	select OF_BOARD_SETUP
+	select PHY
+	select PINCONF
+	select PINCTRL
+	select PINCTRL_PFC
+	select POSITION_INDEPENDENT
+	imply CMD_FS_UUID
+	imply CMD_GPT
+	imply CMD_MMC_SWRITE if MMC
+	imply CMD_UUID
+	imply SUPPORT_EMMC_RPMB if MMC
+
 choice
 	prompt "Target Renesas SoC select"
 	default RCAR_32
@@ -10,20 +27,8 @@ config RCAR_32
 
 config RCAR_GEN3
 	bool "Renesas ARM SoCs R-Car Gen3 (64bit)"
-	select ARM64
+	select RCAR_64
-	select PHY
-	select CMD_CACHE
-	select OF_BOARD_SETUP
-	select PINCTRL
-	select PINCONF
-	select PINCTRL_PFC
-	select POSITION_INDEPENDENT
 	select SUPPORT_SPL
-	imply CMD_FS_UUID
-	imply CMD_GPT
-	imply CMD_UUID
-	imply CMD_MMC_SWRITE if MMC
-	imply SUPPORT_EMMC_RPMB if MMC
 	imply SPL
 	imply SPL_BOARD_INIT
 	imply SPL_GZIP
@@ -32,8 +37,8 @@ config RCAR_GEN3
 	imply SPL_SERIAL
 	imply SPL_SYS_MALLOC_SIMPLE
 	imply SPL_TINY_MEMSET
-	imply SPL_YMODEM_SUPPORT
 	imply SPL_USE_TINY_PRINTF
+	imply SPL_YMODEM_SUPPORT
 
 config RZA1
 	prompt "Renesas ARM SoCs RZ/A1 (32bit)"
@@ -41,6 +46,9 @@ config RZA1
 
 endchoice
 
+config SYS_SOC
+	default "rmobile" if ARCH_RMOBILE
+
 source "arch/arm/mach-rmobile/Kconfig.32"
 source "arch/arm/mach-rmobile/Kconfig.64"
 source "arch/arm/mach-rmobile/Kconfig.rza1"

arch/arm/mach-rmobile/Kconfig.32

@@ -125,9 +125,6 @@ endchoice
 config TMU_TIMER
 	bool
 
-config SYS_SOC
-	default "rmobile"
-
 config RMOBILE_EXTRAM_BOOT
 	bool "Enable boot from RAM"
 	depends on TARGET_ALT || TARGET_BLANCHE || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT

arch/arm/mach-rmobile/Kconfig.64

@@ -1,207 +1,11 @@
-if RCAR_GEN3
+if RCAR_64
-
-menu "Select Target SoC"
-
-config R8A774A1
-	bool "Renesas SoC R8A774A1"
-	select GICV2
-	imply CLK_R8A774A1
-	imply PINCTRL_PFC_R8A774A1
-
-config R8A774B1
-	bool "Renesas SoC R8A774B1"
-	select GICV2
-	imply CLK_R8A774B1
-	imply PINCTRL_PFC_R8A774B1
-
-config R8A774C0
-	bool "Renesas SoC R8A774C0"
-	select GICV2
-	imply CLK_R8A774C0
-	imply PINCTRL_PFC_R8A774C0
-
-config R8A774E1
-	bool "Renesas SoC R8A774E1"
-	select GICV2
-	imply CLK_R8A774E1
-	imply PINCTRL_PFC_R8A774E1
-
-config R8A7795
-	bool "Renesas SoC R8A7795"
-	select GICV2
-	imply CLK_R8A7795
-	imply PINCTRL_PFC_R8A77951
-
-config R8A7796
-	bool "Renesas SoC R8A7796"
-	select GICV2
-	imply CLK_R8A77960
-	imply CLK_R8A77961
-	imply PINCTRL_PFC_R8A77960
-	imply PINCTRL_PFC_R8A77961
-
-config R8A77965
-	bool "Renesas SoC R8A77965"
-	select GICV2
-	imply CLK_R8A77965
-	imply PINCTRL_PFC_R8A77965
-
-config R8A77970
-	bool "Renesas SoC R8A77970"
-	select GICV2
-	imply CLK_R8A77970
-	imply PINCTRL_PFC_R8A77970
-
-config R8A77980
-	bool "Renesas SoC R8A77980"
-	select GICV2
-	imply CLK_R8A77980
-	imply PINCTRL_PFC_R8A77980
-
-config R8A77990
-	bool "Renesas SoC R8A77990"
-	select GICV2
-	imply CLK_R8A77990
-	imply PINCTRL_PFC_R8A77990
-
-config R8A77995
-	bool "Renesas SoC R8A77995"
-	select GICV2
-	imply CLK_R8A77995
-	imply PINCTRL_PFC_R8A77995
-
-config R8A779A0
-	bool "Renesas SoC R8A779A0"
-	select GICV3
-	imply CLK_R8A779A0
-	imply PINCTRL_PFC_R8A779A0
-
-config RZ_G2
-	bool "Renesas ARM SoCs RZ/G2 (64bit)"
-
-endmenu
-
-choice
-	prompt "Renesas ARM64 SoCs board select"
-	optional
-
-config TARGET_BEACON_RZG2M
-	bool "Beacon EmbeddedWorks RZ/G2 Dev Kit"
-	select R8A774A1
-	select R8A774B1
-	select R8A774E1
-	select RZ_G2
-	select PINCTRL_PFC_R8A774A1
-	select PINCTRL_PFC_R8A774B1
-	select PINCTRL_PFC_R8A774E1
-	imply MULTI_DTB_FIT
-	imply MULTI_DTB_FIT_USER_DEFINED_AREA
-	imply CLK_VERSACLOCK
-	imply CLK_CCF
-
-config TARGET_CONDOR
-	bool "Condor board"
-	imply R8A77980
-	help
-          Support for Renesas R-Car Gen3 Condor platform
-
-config TARGET_DRAAK
-	bool "Draak board"
-	imply R8A77995
-	help
-          Support for Renesas R-Car Gen3 Draak platform
-
-config TARGET_EAGLE
-	bool "Eagle board"
-	imply R8A77970
-	help
-          Support for Renesas R-Car Gen3 Eagle platform
-
-config TARGET_EBISU
-	bool "Ebisu board"
-	imply R8A77990
-	help
-          Support for Renesas R-Car Gen3 Ebisu platform
-
-config TARGET_FALCON
-	bool "Falcon board"
-	imply R8A779A0
-	help
-          Support for Renesas R-Car Gen3 Falcon platform
-
-config TARGET_HIHOPE_RZG2
-	bool "HiHope RZ/G2 board"
-	imply R8A774A1
-	imply R8A774B1
-	imply R8A774E1
-	imply RZ_G2
-	imply SYS_MALLOC_F
-	imply MULTI_DTB_FIT
-	imply MULTI_DTB_FIT_USER_DEFINED_AREA
-	help
-          Support for RZG2 HiHope platform
-
-config TARGET_SILINUX_EK874
-	bool "Silicon Linux EK874 board"
-	imply R8A774C0
-	imply RZ_G2
-	help
-          Support for Silicon Linux EK874 platform
-
-config TARGET_SALVATOR_X
-	bool "Salvator-X board"
-	imply R8A7795
-	imply R8A7796
-	imply R8A77965
-	imply SYS_MALLOC_F
-	imply MULTI_DTB_FIT
-	imply MULTI_DTB_FIT_USER_DEFINED_AREA
-	help
-          Support for Renesas R-Car Gen3 platform
-
-config TARGET_ULCB
-	bool "ULCB board"
-	imply R8A7795
-	imply R8A7796
-	imply R8A77965
-	imply SYS_MALLOC_F
-	imply MULTI_DTB_FIT
-	imply MULTI_DTB_FIT_USER_DEFINED_AREA
-	help
-          Support for Renesas R-Car Gen3 ULCB platform
-
-endchoice
-
-config SYS_SOC
-	default "rmobile"
-
-source "board/renesas/condor/Kconfig"
-source "board/renesas/draak/Kconfig"
-source "board/renesas/eagle/Kconfig"
-source "board/renesas/ebisu/Kconfig"
-source "board/renesas/falcon/Kconfig"
-source "board/renesas/salvator-x/Kconfig"
-source "board/renesas/ulcb/Kconfig"
-source "board/beacon/beacon-rzg2m/Kconfig"
-source "board/hoperun/hihope-rzg2/Kconfig"
-source "board/silinux/ek874/Kconfig"
-
-config MULTI_DTB_FIT_UNCOMPRESS_SZ
-	default 0x80000 if TARGET_BEACON_RZG2M
-	default 0x80000 if TARGET_HIHOPE_RZG2
-	default 0x80000 if TARGET_SALVATOR_X
-	default 0x80000 if TARGET_ULCB
-
-config MULTI_DTB_FIT_USER_DEF_ADDR
-	default 0x49000000 if TARGET_BEACON_RZG2M
-	default 0x49000000 if TARGET_HIHOPE_RZG2
-	default 0x49000000 if TARGET_SALVATOR_X
-	default 0x49000000 if TARGET_ULCB
 
 config SYS_MALLOC_F_LEN
-	default 0x8000 if RCAR_GEN3
+	default 0x8000 if RCAR_64
 
-config DM_RESET
+config OF_LIBFDT_OVERLAY
-	default y if RCAR_GEN3
+	default y if RCAR_64
+
+source "arch/arm/mach-rmobile/Kconfig.rcar3"
 
 endif

arch/arm/mach-rmobile/Kconfig.rcar3

@@ -0,0 +1,201 @@
+if RCAR_GEN3
+
+menu "Select Target SoC"
+
+config R8A774A1
+	bool "Renesas SoC R8A774A1"
+	select GICV2
+	imply CLK_R8A774A1
+	imply PINCTRL_PFC_R8A774A1
+
+config R8A774B1
+	bool "Renesas SoC R8A774B1"
+	select GICV2
+	imply CLK_R8A774B1
+	imply PINCTRL_PFC_R8A774B1
+
+config R8A774C0
+	bool "Renesas SoC R8A774C0"
+	select GICV2
+	imply CLK_R8A774C0
+	imply PINCTRL_PFC_R8A774C0
+
+config R8A774E1
+	bool "Renesas SoC R8A774E1"
+	select GICV2
+	imply CLK_R8A774E1
+	imply PINCTRL_PFC_R8A774E1
+
+config R8A7795
+	bool "Renesas SoC R8A7795"
+	select GICV2
+	imply CLK_R8A7795
+	imply PINCTRL_PFC_R8A77951
+
+config R8A7796
+	bool "Renesas SoC R8A7796"
+	select GICV2
+	imply CLK_R8A77960
+	imply CLK_R8A77961
+	imply PINCTRL_PFC_R8A77960
+	imply PINCTRL_PFC_R8A77961
+
+config R8A77965
+	bool "Renesas SoC R8A77965"
+	select GICV2
+	imply CLK_R8A77965
+	imply PINCTRL_PFC_R8A77965
+
+config R8A77970
+	bool "Renesas SoC R8A77970"
+	select GICV2
+	imply CLK_R8A77970
+	imply PINCTRL_PFC_R8A77970
+
+config R8A77980
+	bool "Renesas SoC R8A77980"
+	select GICV2
+	imply CLK_R8A77980
+	imply PINCTRL_PFC_R8A77980
+
+config R8A77990
+	bool "Renesas SoC R8A77990"
+	select GICV2
+	imply CLK_R8A77990
+	imply PINCTRL_PFC_R8A77990
+
+config R8A77995
+	bool "Renesas SoC R8A77995"
+	select GICV2
+	imply CLK_R8A77995
+	imply PINCTRL_PFC_R8A77995
+
+config R8A779A0
+	bool "Renesas SoC R8A779A0"
+	select GICV3
+	imply CLK_R8A779A0
+	imply PINCTRL_PFC_R8A779A0
+
+config RZ_G2
+	bool "Renesas ARM SoCs RZ/G2 (64bit)"
+
+endmenu
+
+choice
+	prompt "Renesas ARM64 SoCs board select"
+	optional
+
+config TARGET_BEACON_RZG2M
+	bool "Beacon EmbeddedWorks RZ/G2 Dev Kit"
+	select PINCTRL_PFC_R8A774A1
+	select PINCTRL_PFC_R8A774B1
+	select PINCTRL_PFC_R8A774E1
+	select R8A774A1
+	select R8A774B1
+	select R8A774E1
+	select RZ_G2
+	imply CLK_CCF
+	imply CLK_VERSACLOCK
+	imply MULTI_DTB_FIT
+	imply MULTI_DTB_FIT_USER_DEFINED_AREA
+
+config TARGET_CONDOR
+	bool "Condor board"
+	imply R8A77980
+	help
+          Support for Renesas R-Car Gen3 Condor platform
+
+config TARGET_DRAAK
+	bool "Draak board"
+	imply R8A77995
+	help
+          Support for Renesas R-Car Gen3 Draak platform
+
+config TARGET_EAGLE
+	bool "Eagle board"
+	imply R8A77970
+	help
+          Support for Renesas R-Car Gen3 Eagle platform
+
+config TARGET_EBISU
+	bool "Ebisu board"
+	imply R8A77990
+	help
+          Support for Renesas R-Car Gen3 Ebisu platform
+
+config TARGET_FALCON
+	bool "Falcon board"
+	imply R8A779A0
+	help
+          Support for Renesas R-Car Gen3 Falcon platform
+
+config TARGET_HIHOPE_RZG2
+	bool "HiHope RZ/G2 board"
+	imply MULTI_DTB_FIT
+	imply MULTI_DTB_FIT_USER_DEFINED_AREA
+	imply R8A774A1
+	imply R8A774B1
+	imply R8A774E1
+	imply RZ_G2
+	imply SYS_MALLOC_F
+	help
+          Support for RZG2 HiHope platform
+
+config TARGET_SILINUX_EK874
+	bool "Silicon Linux EK874 board"
+	imply R8A774C0
+	imply RZ_G2
+	help
+          Support for Silicon Linux EK874 platform
+
+config TARGET_SALVATOR_X
+	bool "Salvator-X board"
+	imply MULTI_DTB_FIT
+	imply MULTI_DTB_FIT_USER_DEFINED_AREA
+	imply R8A7795
+	imply R8A7796
+	imply R8A77965
+	imply SYS_MALLOC_F
+	help
+          Support for Renesas R-Car Gen3 platform
+
+config TARGET_ULCB
+	bool "ULCB board"
+	imply MULTI_DTB_FIT
+	imply MULTI_DTB_FIT_USER_DEFINED_AREA
+	imply R8A7795
+	imply R8A7796
+	imply R8A77965
+	imply SYS_MALLOC_F
+	help
+          Support for Renesas R-Car Gen3 ULCB platform
+
+endchoice
+
+source "board/renesas/condor/Kconfig"
+source "board/renesas/draak/Kconfig"
+source "board/renesas/eagle/Kconfig"
+source "board/renesas/ebisu/Kconfig"
+source "board/renesas/falcon/Kconfig"
+source "board/renesas/salvator-x/Kconfig"
+source "board/renesas/ulcb/Kconfig"
+source "board/beacon/beacon-rzg2m/Kconfig"
+source "board/hoperun/hihope-rzg2/Kconfig"
+source "board/silinux/ek874/Kconfig"
+
+config MULTI_DTB_FIT_UNCOMPRESS_SZ
+	default 0x80000 if TARGET_BEACON_RZG2M
+	default 0x80000 if TARGET_HIHOPE_RZG2
+	default 0x80000 if TARGET_SALVATOR_X
+	default 0x80000 if TARGET_ULCB
+
+config MULTI_DTB_FIT_USER_DEF_ADDR
+	default 0x49000000 if TARGET_BEACON_RZG2M
+	default 0x49000000 if TARGET_HIHOPE_RZG2
+	default 0x49000000 if TARGET_SALVATOR_X
+	default 0x49000000 if TARGET_ULCB
+
+config DM_RESET
+	default y if RCAR_GEN3
+
+endif

arch/arm/mach-rmobile/Kconfig.rza1

@@ -19,9 +19,6 @@ config TARGET_GRPEACH
 
 endchoice
 
-config SYS_SOC
-	default "rmobile"
-
 # Renesas Supported Boards
 source "board/renesas/grpeach/Kconfig"
 

arch/arm/mach-rmobile/cpu_info-rcar.c

@@ -14,11 +14,10 @@
 
 static u32 rmobile_get_prr(void)
 {
-#ifdef CONFIG_RCAR_GEN3
+	if (IS_ENABLED(CONFIG_RCAR_GEN3))
-	return readl(0xFFF00044);
+		return readl(0xFFF00044);
-#else
+
 	return readl(0xFF000044);
-#endif
 }
 
 u32 rmobile_get_cpu_type(void)

board/renesas/falcon/falcon.c

@@ -14,6 +14,7 @@
 #include <asm/mach-types.h>
 #include <asm/processor.h>
 #include <linux/errno.h>
+#include <asm/system.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -69,7 +70,8 @@ static void init_gic_v3(void)
 
 void s_init(void)
 {
-	init_generic_timer();
+	if (current_el() == 3)
+		init_generic_timer();
 }
 
 int board_early_init_f(void)
@@ -81,20 +83,27 @@ int board_early_init_f(void)
 	return 0;
 }
 
+#define RST_BASE	0xE6160000 /* Domain0 */
+#define RST_SRESCR0	(RST_BASE + 0x18)
+#define RST_SPRES	0x5AA58000
+#define RST_WDTRSTCR	(RST_BASE + 0x10)
+#define RST_RWDT	0xA55A8002
+
 int board_init(void)
 {
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_TEXT_BASE + 0x50000;
 
-	init_gic_v3();
+	if (current_el() == 3) {
+		init_gic_v3();
+
+		/* Enable RWDT reset */
+		writel(RST_RWDT, RST_WDTRSTCR);
+	}
 
 	return 0;
 }
 
-#define RST_BASE	0xE6160000 /* Domain0 */
-#define RST_SRESCR0	(RST_BASE + 0x18)
-#define RST_SPRES	0x5AA58000
-
 void reset_cpu(void)
 {
 	writel(RST_SPRES, RST_SRESCR0);

board/renesas/rcar-common/common.c

@@ -73,9 +73,9 @@ static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node)
 			if (curr_mem_res.start >= first_mem_res.end)
 				continue;
 
-			printf("Overlap found: 0x%llx..0x%llx / 0x%llx..0x%llx\n",
+			log_debug("Overlap found: 0x%llx..0x%llx / 0x%llx..0x%llx\n",
-				first_mem_res.start, first_mem_res.end,
+				  first_mem_res.start, first_mem_res.end,
-				curr_mem_res.start, curr_mem_res.end);
+				  curr_mem_res.start, curr_mem_res.end);
 
 			return 1;
 		}

configs/r8a77970_eagle_defconfig

@@ -37,7 +37,6 @@ CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -82,9 +81,4 @@ CONFIG_DM_SPI=y
 CONFIG_RENESAS_RPC_SPI=y
 CONFIG_TEE=y
 CONFIG_OPTEE=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT_OVERLAY=y

configs/r8a77980_condor_defconfig

@@ -39,7 +39,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -91,9 +90,4 @@ CONFIG_RENESAS_RPC_SPI=y
 CONFIG_SYSINFO=y
 CONFIG_TEE=y
 CONFIG_OPTEE=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT_OVERLAY=y

drivers/clk/renesas/clk-rcar-gen3.c

@@ -55,6 +55,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
 			       struct cpg_mssr_info *info, struct clk *parent)
 {
 	const struct cpg_core_clk *core;
+	u8 shift;
 	int ret;
 
 	if (!renesas_clk_is_mod(clk)) {
@@ -63,8 +64,9 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
 			return ret;
 
 		if (core->type == CLK_TYPE_GEN3_MDSEL) {
+			shift = priv->cpg_mode & BIT(core->offset) ? 16 : 0;
 			parent->dev = clk->dev;
-			parent->id = core->parent >> (priv->sscg ? 16 : 0);
+			parent->id = core->parent >> shift;
 			parent->id &= 0xffff;
 			return 0;
 		}
@@ -183,6 +185,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
 					priv->cpg_pll_config;
 	u32 value, div;
 	u64 rate = 0;
+	u8 shift;
 	int ret;
 
 	debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
@@ -277,11 +280,11 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
 						"FIXED");
 
 	case CLK_TYPE_GEN3_MDSEL:
-		div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
+		shift = priv->cpg_mode & BIT(core->offset) ? 16 : 0;
+		div = (core->div >> shift) & 0xffff;
 		rate = gen3_clk_get_rate64(&parent) / div;
 		debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
-		      __func__, __LINE__,
+		      __func__, __LINE__, (core->parent >> shift) & 0xffff,
-		      (core->parent >> (priv->sscg ? 16 : 0)) & 0xffff,
 		      div, rate);
 		return rate;
 
@@ -407,7 +410,6 @@ static int gen3_clk_probe(struct udevice *dev)
 	struct cpg_mssr_info *info =
 		(struct cpg_mssr_info *)dev_get_driver_data(dev);
 	fdt_addr_t rst_base;
-	u32 cpg_mode;
 	int ret;
 
 	priv->base = dev_read_addr_ptr(dev);
@@ -423,15 +425,13 @@ static int gen3_clk_probe(struct udevice *dev)
 	if (rst_base == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	cpg_mode = readl(rst_base + info->reset_modemr_offset);
+	priv->cpg_mode = readl(rst_base + info->reset_modemr_offset);
 
 	priv->cpg_pll_config =
-		(struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
+		(struct rcar_gen3_cpg_pll_config *)info->get_pll_config(priv->cpg_mode);
 	if (!priv->cpg_pll_config->extal_div)
 		return -EINVAL;
 
-	priv->sscg = !(cpg_mode & BIT(12));
-
 	if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
 		priv->info->status_regs = mstpsr;
 		priv->info->control_regs = smstpcr;

drivers/clk/renesas/rcar-gen3-cpg.h

@@ -132,7 +132,7 @@ struct gen3_clk_priv {
 	struct cpg_mssr_info	*info;
 	struct clk		clk_extal;
 	struct clk		clk_extalr;
-	bool			sscg;
+	u32			cpg_mode;
 	const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
 };
 

drivers/gpio/sh_pfc.c

@@ -568,10 +568,10 @@ static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
 
 	if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
 		return -1;
-#if defined(CONFIG_RCAR_GEN3)
+
-	if ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_INPUT)
+	if (IS_ENABLED(CONFIG_RCAR_GEN3) &&
+	    ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_INPUT))
 		offset += 4;
-#endif
 
 	return gpio_read_bit(dr, offset, bit);
 }

drivers/i2c/Kconfig

@@ -496,13 +496,13 @@ config SYS_I2C_OMAP24XX
 
 config SYS_I2C_RCAR_I2C
 	bool "Renesas RCar I2C driver"
-	depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
+	depends on (RCAR_GEN2 || RCAR_GEN3) && DM_I2C
 	help
 	  Support for Renesas RCar I2C controller.
 
 config SYS_I2C_RCAR_IIC
 	bool "Renesas RCar Gen3 IIC driver"
-	depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
+	depends on (RCAR_GEN2 || RCAR_GEN3) && DM_I2C
 	help
 	  Support for Renesas RCar Gen3 IIC controller.
 

drivers/net/ravb.c

@@ -310,7 +310,7 @@ static int ravb_phy_config(struct udevice *dev)
 	struct ravb_priv *eth = dev_get_priv(dev);
 	struct eth_pdata *pdata = dev_get_plat(dev);
 	struct phy_device *phydev;
-	int mask = 0xffffffff, reg;
+	int reg;
 
 	if (dm_gpio_is_valid(&eth->reset_gpio)) {
 		dm_gpio_set_value(&eth->reset_gpio, 1);
@@ -319,12 +319,10 @@ static int ravb_phy_config(struct udevice *dev)
 		mdelay(1);
 	}
 
-	phydev = phy_find_by_mask(eth->bus, mask);
+	phydev = phy_connect(eth->bus, -1, dev, pdata->phy_interface);
 	if (!phydev)
 		return -ENODEV;
 
-	phy_connect_dev(phydev, dev, pdata->phy_interface);
-
 	eth->phydev = phydev;
 
 	phydev->supported &= SUPPORTED_100baseT_Full |

drivers/serial/Kconfig

@@ -415,6 +415,14 @@ config DEBUG_UART_SEMIHOSTING
 	  start up driver model. The driver will be available until the real
 	  driver model serial is running.
 
+config DEBUG_UART_SCIF
+	bool "Renesas SCIF UART"
+	depends on SH || ARCH_RMOBILE
+	help
+	  Select this to enable a debug UART using the serial_sh driver. You
+	  will need to provide parameters to make this work. The driver will
+	  be available until the real driver-model serial is running.
+
 config DEBUG_UART_SIFIVE
 	bool "SiFive UART"
 	depends on SIFIVE_SERIAL

drivers/serial/serial_sh.c

@@ -249,9 +249,40 @@ U_BOOT_DRIVER(serial_sh) = {
 #endif
 	.priv_auto	= sizeof(struct uart_port),
 };
+#endif
 
-#else /* CONFIG_DM_SERIAL */
+#if !CONFIG_IS_ENABLED(DM_SERIAL) || IS_ENABLED(CONFIG_DEBUG_UART_SCIF)
 
+#if defined(CFG_SCIF_A)
+	#define SCIF_BASE_PORT	PORT_SCIFA
+#elif defined(CFG_SCI)
+	#define SCIF_BASE_PORT  PORT_SCI
+#else
+	#define SCIF_BASE_PORT	PORT_SCIF
+#endif
+
+static void sh_serial_init_nodm(struct uart_port *port)
+{
+	sh_serial_init_generic(port);
+	serial_setbrg();
+}
+
+static void sh_serial_putc_nondm(struct uart_port *port, const char c)
+{
+	if (c == '\n') {
+		while (1) {
+			if  (serial_raw_putc(port, '\r') != -EAGAIN)
+				break;
+		}
+	}
+	while (1) {
+		if  (serial_raw_putc(port, c) != -EAGAIN)
+			break;
+	}
+}
+#endif
+
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
 #if defined(CONFIG_CONS_SCIF0)
 # define SCIF_BASE	SCIF0_BASE
 #elif defined(CONFIG_CONS_SCIF1)
@@ -274,19 +305,11 @@ U_BOOT_DRIVER(serial_sh) = {
 # error "Default SCIF doesn't set....."
 #endif
 
-#if defined(CFG_SCIF_A)
-	#define SCIF_BASE_PORT	PORT_SCIFA
-#elif defined(CONFIG_SCI)
-	#define SCIF_BASE_PORT  PORT_SCI
-#else
-	#define SCIF_BASE_PORT	PORT_SCIF
-#endif
-
 static struct uart_port sh_sci = {
 	.membase	= (unsigned char *)SCIF_BASE,
 	.mapbase	= SCIF_BASE,
 	.type		= SCIF_BASE_PORT,
-#ifdef CONFIG_SCIF_USE_EXT_CLK
+#ifdef CFG_SCIF_USE_EXT_CLK
 	.clk_mode =	EXT_CLK,
 #endif
 };
@@ -301,28 +324,14 @@ static void sh_serial_setbrg(void)
 
 static int sh_serial_init(void)
 {
-	struct uart_port *port = &sh_sci;
+	sh_serial_init_nodm(&sh_sci);
-
-	sh_serial_init_generic(port);
-	serial_setbrg();
 
 	return 0;
 }
 
 static void sh_serial_putc(const char c)
 {
-	struct uart_port *port = &sh_sci;
+	sh_serial_putc_nondm(&sh_sci, c);
-
-	if (c == '\n') {
-		while (1) {
-			if  (serial_raw_putc(port, '\r') != -EAGAIN)
-				break;
-		}
-	}
-	while (1) {
-		if  (serial_raw_putc(port, c) != -EAGAIN)
-			break;
-	}
 }
 
 static int sh_serial_tstc(void)
@@ -367,3 +376,29 @@ __weak struct serial_device *default_serial_console(void)
 	return &sh_serial_drv;
 }
 #endif /* CONFIG_DM_SERIAL */
+
+#ifdef CONFIG_DEBUG_UART_SCIF
+#include <debug_uart.h>
+
+static struct uart_port debug_uart_sci = {
+	.membase	= (unsigned char *)CONFIG_DEBUG_UART_BASE,
+	.mapbase	= CONFIG_DEBUG_UART_BASE,
+	.type		= SCIF_BASE_PORT,
+#ifdef CFG_SCIF_USE_EXT_CLK
+	.clk_mode =	EXT_CLK,
+#endif
+};
+
+static inline void _debug_uart_init(void)
+{
+	sh_serial_init_nodm(&debug_uart_sci);
+}
+
+static inline void _debug_uart_putc(int c)
+{
+	sh_serial_putc_nondm(&debug_uart_sci, c);
+}
+
+DEBUG_UART_FUNCS
+
+#endif

drivers/serial/serial_sh.h

@@ -406,13 +406,13 @@ SCIF_FNS(SCSPTR,			0,  0, 0x24, 16)
 SCIF_FNS(SCLSR,				0,  0, 0x28, 16)
 #else
 
-SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
+SCIF_FNS(SCFDR,			     0x0e, 16, 0x1C, 16)
 #if defined(CONFIG_CPU_SH7722)
-SCIF_FNS(SCSPTR,                        0,  0, 0, 0)
+SCIF_FNS(SCSPTR,			0,  0, 0, 0)
 #else
-SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
+SCIF_FNS(SCSPTR,			0,  0, 0x20, 16)
 #endif
-SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
+SCIF_FNS(SCLSR,				0,  0, 0x24, 16)
 #endif
 SCIF_FNS(DL,				0,  0, 0x0,  0) /* dummy */
 #endif