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sh: add support for sh7752evb board
The R0P7752C00000RZ board has SH7752, 512MB DDR3-SDRAM, SPI ROM, Gigabit Ethernet, and eMMC. This patch supports the following functions: - 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Yoshihiro Shimoda
committed by
Nobuhiro Iwamatsu
Nobuhiro Iwamatsu
parent
095728803e
commit
1a2621bab8
@@ -48,6 +48,8 @@
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# include <asm/cpu_sh7724.h>
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#elif defined (CONFIG_CPU_SH7734)
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# include <asm/cpu_sh7734.h>
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#elif defined (CONFIG_CPU_SH7752)
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# include <asm/cpu_sh7752.h>
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#elif defined (CONFIG_CPU_SH7757)
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# include <asm/cpu_sh7757.h>
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#elif defined (CONFIG_CPU_SH7763)
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211
arch/sh/include/asm/cpu_sh7752.h
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211
arch/sh/include/asm/cpu_sh7752.h
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@@ -0,0 +1,211 @@
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/*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef _ASM_CPU_SH7752_H_
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#define _ASM_CPU_SH7752_H_
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#define CCR 0xFF00001C
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#define WTCNT 0xFFCC0000
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#define CCR_CACHE_INIT 0x0000090b
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#define CACHE_OC_NUM_WAYS 1
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#ifndef __ASSEMBLY__ /* put C only stuff in this section */
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/* MMU */
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struct mmu_regs {
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unsigned int reserved[4];
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unsigned int mmucr;
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};
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#define MMU_BASE ((struct mmu_regs *)0xff000000)
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/* Watchdog */
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#define WTCSR0 0xffcc0002
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#define WRSTCSR_R 0xffcc0003
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#define WRSTCSR_W 0xffcc0002
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#define WTCSR_PREFIX 0xa500
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#define WRSTCSR_PREFIX 0x6900
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#define WRSTCSR_WOVF_PREFIX 0x9600
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/* SCIF */
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#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
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#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
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#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
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/* TMU0 */
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#define TMU_BASE 0xFE430000
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/* ETHER, GETHER MAC address */
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struct ether_mac_regs {
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unsigned int reserved[114];
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unsigned int mahr;
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unsigned int reserved2;
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unsigned int malr;
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};
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#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
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#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
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#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
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#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
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/* GETHER */
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struct gether_control_regs {
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unsigned int gbecont;
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};
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#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
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#define GBECONT_RMII1 0x00020000
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#define GBECONT_RMII0 0x00010000
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/* SerMux */
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struct sermux_regs {
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unsigned char smr0;
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unsigned char smr1;
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unsigned char smr2;
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unsigned char smr3;
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unsigned char smr4;
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unsigned char smr5;
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};
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#define SERMUX_BASE ((struct sermux_regs *)0xfe470000)
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/* USB0/1 */
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struct usb_common_regs {
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unsigned short reserved[129];
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unsigned short suspmode;
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};
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#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
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#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
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struct usb0_phy_regs {
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unsigned short reset;
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unsigned short reserved[4];
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unsigned short portsel;
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};
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#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
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struct usb1_port_regs {
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unsigned int port1sel;
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unsigned int reserved;
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unsigned int usb1intsts;
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};
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#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
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struct usb1_alignment_regs {
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unsigned int ehcidatac; /* 0xfe4fe018 */
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unsigned int reserved[63];
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unsigned int ohcidatac;
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};
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#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
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/* GPIO */
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struct gpio_regs {
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unsigned short pacr;
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unsigned short pbcr;
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unsigned short pccr;
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unsigned short pdcr;
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unsigned short pecr;
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unsigned short pfcr;
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unsigned short pgcr;
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unsigned short phcr;
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unsigned short picr;
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unsigned short pjcr;
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unsigned short pkcr;
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unsigned short plcr;
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unsigned short pmcr;
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unsigned short pncr;
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unsigned short pocr;
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unsigned short reserved;
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unsigned short pqcr;
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unsigned short prcr;
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unsigned short pscr;
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unsigned short ptcr;
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unsigned short pucr;
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unsigned short pvcr;
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unsigned short pwcr;
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unsigned short pxcr;
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unsigned short pycr;
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unsigned short pzcr;
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unsigned char padr;
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unsigned char reserved_a;
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unsigned char pbdr;
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unsigned char reserved_b;
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unsigned char pcdr;
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unsigned char reserved_c;
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unsigned char pddr;
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unsigned char reserved_d;
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unsigned char pedr;
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unsigned char reserved_e;
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unsigned char pfdr;
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unsigned char reserved_f;
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unsigned char pgdr;
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unsigned char reserved_g;
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unsigned char phdr;
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unsigned char reserved_h;
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unsigned char pidr;
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unsigned char reserved_i;
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unsigned char pjdr;
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unsigned char reserved_j;
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unsigned char pkdr;
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unsigned char reserved_k;
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unsigned char pldr;
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unsigned char reserved_l;
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unsigned char pmdr;
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unsigned char reserved_m;
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unsigned char pndr;
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unsigned char reserved_n;
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unsigned char podr;
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unsigned char reserved_o;
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unsigned char ppdr;
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unsigned char reserved_p;
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unsigned char pqdr;
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unsigned char reserved_q;
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unsigned char prdr;
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unsigned char reserved_r;
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unsigned char psdr;
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unsigned char reserved_s;
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unsigned char ptdr;
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unsigned char reserved_t;
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unsigned char pudr;
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unsigned char reserved_u;
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unsigned char pvdr;
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unsigned char reserved_v;
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unsigned char pwdr;
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unsigned char reserved_w;
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unsigned char pxdr;
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unsigned char reserved_x;
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unsigned char pydr;
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unsigned char reserved_y;
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unsigned char pzdr;
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unsigned char reserved_z;
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unsigned short ncer;
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unsigned short ncmcr;
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unsigned short nccsr;
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unsigned char reserved2[2];
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unsigned short psel0; /* +0x70 */
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unsigned short psel1;
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unsigned short psel2;
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unsigned short psel3;
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unsigned short psel4;
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unsigned short psel5;
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unsigned short psel6;
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unsigned short reserved3[2];
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unsigned short psel7;
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};
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#define GPIO_BASE ((struct gpio_regs *)0xffec0000)
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#endif /* ifndef __ASSEMBLY__ */
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#endif /* _ASM_CPU_SH7752_H_ */
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