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ARC: Cache: Move I$ entire operation to a separate function
Move instruction cache entire operation to a separate function because we are planing to use it in other places like sync_icache_dcache_all(). Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
committed by
Alexey Brodkin
parent
71621525c3
commit
16aeee81d9
@@ -315,20 +315,27 @@ void icache_disable(void)
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IC_CTRL_CACHE_DISABLE);
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IC_CTRL_CACHE_DISABLE);
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}
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}
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/* IC supports only invalidation */
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static inline void __ic_entire_invalidate(void)
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{
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if (!icache_status())
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return;
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/* Any write to IC_IVIC register triggers invalidation of entire I$ */
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write_aux_reg(ARC_AUX_IC_IVIC, 1);
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/*
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* As per ARC HS databook (see chapter 5.3.3.2)
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* it is required to add 3 NOPs after each write to IC_IVIC.
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*/
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__builtin_arc_nop();
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__builtin_arc_nop();
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__builtin_arc_nop();
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read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
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}
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void invalidate_icache_all(void)
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void invalidate_icache_all(void)
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{
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{
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/* Any write to IC_IVIC register triggers invalidation of entire I$ */
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__ic_entire_invalidate();
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if (icache_status()) {
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write_aux_reg(ARC_AUX_IC_IVIC, 1);
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/*
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* As per ARC HS databook (see chapter 5.3.3.2)
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* it is required to add 3 NOPs after each write to IC_IVIC.
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*/
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__builtin_arc_nop();
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__builtin_arc_nop();
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__builtin_arc_nop();
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read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
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}
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#ifdef CONFIG_ISA_ARCV2
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#ifdef CONFIG_ISA_ARCV2
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if (slc_exists)
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if (slc_exists)
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