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mpc85xx: Add support for SBC8548 (updated)
Add support for Wind River's SBC8548 reference board. Signed-off by: Joe Hamman <joe.hamman@embeddedspecialties.com> Signed-off by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Joe Hamman
committed by
Andrew Fleming-AFLEMING
Andrew Fleming-AFLEMING
parent
64d4bcb087
commit
11c45ebd46
@@ -190,6 +190,7 @@ Howard Gray <mvsensor@matrix-vision.de>
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Joe Hamman <joe.hamman@embeddedspecialties.com>
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sbc8548 MPC8548
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sbc8641d MPC8641D
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Klaus Heydeck <heydeck@kieback-peter.de>
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1
MAKEALL
1
MAKEALL
@@ -335,6 +335,7 @@ LIST_85xx=" \
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PM854 \
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PM856 \
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sbc8540 \
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sbc8548 \
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sbc8560 \
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stxgp3 \
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stxssa \
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3
Makefile
3
Makefile
@@ -2025,6 +2025,9 @@ sbc8540_66_config: unconfig
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fi
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@$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560
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sbc8548_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc85xx sbc8548
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sbc8560_config \
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sbc8560_33_config \
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sbc8560_66_config: unconfig
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55
board/sbc8548/Makefile
Normal file
55
board/sbc8548/Makefile
Normal file
@@ -0,0 +1,55 @@
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#
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# (C) Copyright 2004-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
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# Added support for Wind River SBC8560 board
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o
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SOBJS := init.o
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#SOBJS :=
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(OBJS) $(SOBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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32
board/sbc8548/config.mk
Normal file
32
board/sbc8548/config.mk
Normal file
@@ -0,0 +1,32 @@
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#
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# Copyright 2004, 2007 Freescale Semiconductor.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# sbc8548 board
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#
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ifndef TEXT_BASE
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TEXT_BASE = 0xfff80000
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endif
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PLATFORM_CPPFLAGS += -DCONFIG_E500=1
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PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
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PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
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241
board/sbc8548/init.S
Normal file
241
board/sbc8548/init.S
Normal file
@@ -0,0 +1,241 @@
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/*
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* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
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* Copyright 2007 Embedded Specialties, Inc.
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*
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* Copyright 2004 Freescale Semiconductor.
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* Copyright 2002,2003, Motorola Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <config.h>
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#include <mpc85xx.h>
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/*
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* TLB0 and TLB1 Entries
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*
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* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
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* However, CCSRBAR is then relocated to CFG_CCSRBAR right after
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* these TLB entries are established.
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*
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* The TLB entries for DDR are dynamically setup in spd_sdram()
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* and use TLB1 Entries 8 through 15 as needed according to the
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* size of DDR memory.
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*
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* MAS0: tlbsel, esel, nv
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* MAS1: valid, iprot, tid, ts, tsize
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* MAS2: epn, x0, x1, w, i, m, g, e
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* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
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*/
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#define entry_start \
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mflr r1 ; \
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bl 0f ;
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#define entry_end \
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0: mflr r0 ; \
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mtlr r1 ; \
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blr ;
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.section .bootpg, "ax"
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.globl tlb1_entry
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tlb1_entry:
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entry_start
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/*
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* Number of TLB0 and TLB1 entries in the following table
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*/
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.long 13
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#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
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/*
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* TLB0 4K Non-cacheable, guarded
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* 0xff700000 4K Initial CCSRBAR mapping
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*
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* This ends up at a TLB0 Index==0 entry, and must not collide
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* with other TLB0 Entries.
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*/
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.long FSL_BOOKE_MAS0(0, 0, 0)
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
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.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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#else
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#error("Update the number of table entries in tlb1_entry")
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#endif
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/*
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* TLB0 16K Cacheable, non-guarded
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* 0xe4010000 16K Temporary Global data for initialization
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*
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* Use four 4K TLB0 entries. These entries must be cacheable
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* as they provide the bootstrap memory before the memory
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* controler and real memory have been configured.
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*
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* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
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* and must not collide with other TLB0 entries.
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*/
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.long FSL_BOOKE_MAS0(0, 0, 0)
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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.long FSL_BOOKE_MAS0(0, 0, 0)
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0,
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(MAS3_SX|MAS3_SW|MAS3_SR))
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.long FSL_BOOKE_MAS0(0, 0, 0)
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0,
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(MAS3_SX|MAS3_SW|MAS3_SR))
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.long FSL_BOOKE_MAS0(0, 0, 0)
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0,
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(MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 0: 16M Non-cacheable, guarded
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* 0xff800000 16M TLB for 8MB FLASH
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* Out of reset this entry is only 4K.
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*/
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.long FSL_BOOKE_MAS0(1, 0, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
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.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 1: 256M Non-cacheable, guarded
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* 0x80000000 256M PCI1 MEM First half
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*/
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.long FSL_BOOKE_MAS0(1, 1, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 2: 256M Non-cacheable, guarded
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* 0x90000000 256M PCI1 MEM Second half
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*/
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.long FSL_BOOKE_MAS0(1, 2, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0,
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(MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 3: 256M Cacheable, non-guarded
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* 0x0 256M DDR SDRAM
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*/
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#if !defined(CONFIG_SPD_EEPROM)
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.long FSL_BOOKE_MAS0(1, 3, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
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.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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#endif
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/*
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* TLB 4: 64M Non-cacheable, guarded
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* 0xe0000000 1M CCSRBAR
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* 0xe2000000 16M PCI1 IO
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*/
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.long FSL_BOOKE_MAS0(1, 4, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
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.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 5: 64M Cacheable, non-guarded
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* 0xf0000000 64M LBC SDRAM
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*/
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.long FSL_BOOKE_MAS0(1, 5, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
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.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
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.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 6: 16M Cacheable, non-guarded
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* 0xf8000000 1M 7-segment LED display
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* 0xf8100000 1M User switches
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* 0xf8300000 1M Board revision
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* 0xf8b00000 1M EEPROM
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*/
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.long FSL_BOOKE_MAS0(1, 6, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
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.long FSL_BOOKE_MAS2(CFG_EPLD_BASE, 0)
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.long FSL_BOOKE_MAS3(CFG_EPLD_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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entry_end
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/*
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x0fff_ffff DDR 256M
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xe000_0000 0xe000_ffff CCSR 1M
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* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
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* 0xf000_0000 0xf7ff_ffff SDRAM 128M
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* 0xf8b0_0000 0xf80f_ffff EEPROM 1M
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* 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M
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* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
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*
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* Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*
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* The defines below are 1-off of the actual LAWAR0 usage.
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* So LAWAR3 define uses the LAWAR4 register in the ECM.
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*/
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#if !defined(CONFIG_SPD_EEPROM)
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#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
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#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#else
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#define LAWBAR0 0
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#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) & ~LAWAR_EN)
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#endif
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#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#define LAWBAR2 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
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/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
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#define LAWBAR3 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
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.section .bootpg, "ax"
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.globl law_entry
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law_entry:
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entry_start
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.long 4
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.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
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entry_end
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569
board/sbc8548/sbc8548.c
Normal file
569
board/sbc8548/sbc8548.c
Normal file
@@ -0,0 +1,569 @@
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/*
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* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
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* Copyright 2007 Embedded Specialties, Inc.
|
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*
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* Copyright 2004, 2007 Freescale Semiconductor.
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/immap_fsl_pci.h>
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#include <spd.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
|
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||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
extern void ddr_enable_ecc(unsigned int dram_size);
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern long int spd_sdram(void);
|
||||
|
||||
void local_bus_init(void);
|
||||
void sdram_init(void);
|
||||
long int fixed_sdram (void);
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||
volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
|
||||
|
||||
printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
|
||||
(volatile)(*(u_char *)CFG_BD_REV) >> 4);
|
||||
|
||||
/*
|
||||
* Initialize local bus.
|
||||
*/
|
||||
local_bus_init ();
|
||||
|
||||
/*
|
||||
* Fix CPU2 errata: A core hang possible while executing a
|
||||
* msync instruction and a snoopable transaction from an I/O
|
||||
* master tagged to make quick forward progress is present.
|
||||
*/
|
||||
ecm->eebpcr |= (1 << 16);
|
||||
|
||||
/*
|
||||
* Hack TSEC 3 and 4 IO voltages.
|
||||
*/
|
||||
gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
|
||||
|
||||
ecm->eedr = 0xffffffff; /* clear ecm errors */
|
||||
ecm->eeer = 0xffffffff; /* enable ecm errors */
|
||||
return 0;
|
||||
}
|
||||
|
||||
long int
|
||||
initdram(int board_type)
|
||||
{
|
||||
long dram_size = 0;
|
||||
|
||||
puts("Initializing\n");
|
||||
|
||||
#if defined(CONFIG_DDR_DLL)
|
||||
{
|
||||
/*
|
||||
* Work around to stabilize DDR DLL MSYNC_IN.
|
||||
* Errata DDR9 seems to have been fixed.
|
||||
* This is now the workaround for Errata DDR11:
|
||||
* Override DLL = 1, Course Adj = 1, Tap Select = 0
|
||||
*/
|
||||
|
||||
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||
|
||||
gur->ddrdllcr = 0x81000000;
|
||||
asm("sync;isync;msync");
|
||||
udelay(200);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
dram_size = spd_sdram ();
|
||||
#else
|
||||
dram_size = fixed_sdram ();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
/*
|
||||
* Initialize and enable DDR ECC.
|
||||
*/
|
||||
ddr_enable_ecc(dram_size);
|
||||
#endif
|
||||
/*
|
||||
* SDRAM Initialization
|
||||
*/
|
||||
sdram_init();
|
||||
|
||||
puts(" DDR: ");
|
||||
return dram_size;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize Local Bus
|
||||
*/
|
||||
void
|
||||
local_bus_init(void)
|
||||
{
|
||||
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||
|
||||
uint clkdiv;
|
||||
uint lbc_hz;
|
||||
sys_info_t sysinfo;
|
||||
|
||||
get_sys_info(&sysinfo);
|
||||
clkdiv = (lbc->lcrr & 0x0f) * 2;
|
||||
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
|
||||
|
||||
gur->lbiuiplldcr1 = 0x00078080;
|
||||
if (clkdiv == 16) {
|
||||
gur->lbiuiplldcr0 = 0x7c0f1bf0;
|
||||
} else if (clkdiv == 8) {
|
||||
gur->lbiuiplldcr0 = 0x6c0f1bf0;
|
||||
} else if (clkdiv == 4) {
|
||||
gur->lbiuiplldcr0 = 0x5c0f1bf0;
|
||||
}
|
||||
|
||||
lbc->lcrr |= 0x00030000;
|
||||
|
||||
asm("sync;isync;msync");
|
||||
|
||||
lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
|
||||
lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize SDRAM memory on the Local Bus.
|
||||
*/
|
||||
void
|
||||
sdram_init(void)
|
||||
{
|
||||
#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
|
||||
|
||||
uint idx;
|
||||
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
|
||||
uint lsdmr_common;
|
||||
|
||||
puts(" SDRAM: ");
|
||||
|
||||
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
|
||||
|
||||
/*
|
||||
* Setup SDRAM Base and Option Registers
|
||||
*/
|
||||
lbc->or3 = CFG_OR3_PRELIM;
|
||||
asm("msync");
|
||||
|
||||
lbc->br3 = CFG_BR3_PRELIM;
|
||||
asm("msync");
|
||||
|
||||
lbc->lbcr = CFG_LBC_LBCR;
|
||||
asm("msync");
|
||||
|
||||
|
||||
lbc->lsrt = CFG_LBC_LSRT;
|
||||
lbc->mrtpr = CFG_LBC_MRTPR;
|
||||
asm("msync");
|
||||
|
||||
/*
|
||||
* MPC8548 uses "new" 15-16 style addressing.
|
||||
*/
|
||||
lsdmr_common = CFG_LBC_LSDMR_COMMON;
|
||||
lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
|
||||
|
||||
/*
|
||||
* Issue PRECHARGE ALL command.
|
||||
*/
|
||||
lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
|
||||
asm("sync;msync");
|
||||
*sdram_addr = 0xff;
|
||||
ppcDcbf((unsigned long) sdram_addr);
|
||||
udelay(100);
|
||||
|
||||
/*
|
||||
* Issue 8 AUTO REFRESH commands.
|
||||
*/
|
||||
for (idx = 0; idx < 8; idx++) {
|
||||
lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
|
||||
asm("sync;msync");
|
||||
*sdram_addr = 0xff;
|
||||
ppcDcbf((unsigned long) sdram_addr);
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
/*
|
||||
* Issue 8 MODE-set command.
|
||||
*/
|
||||
lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
|
||||
asm("sync;msync");
|
||||
*sdram_addr = 0xff;
|
||||
ppcDcbf((unsigned long) sdram_addr);
|
||||
udelay(100);
|
||||
|
||||
/*
|
||||
* Issue NORMAL OP command.
|
||||
*/
|
||||
lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
|
||||
asm("sync;msync");
|
||||
*sdram_addr = 0xff;
|
||||
ppcDcbf((unsigned long) sdram_addr);
|
||||
udelay(200); /* Overkill. Must wait > 200 bus cycles */
|
||||
|
||||
#endif /* enable SDRAM init */
|
||||
}
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int
|
||||
testdram(void)
|
||||
{
|
||||
uint *pstart = (uint *) CFG_MEMTEST_START;
|
||||
uint *pend = (uint *) CFG_MEMTEST_END;
|
||||
uint *p;
|
||||
|
||||
printf("Testing DRAM from 0x%08x to 0x%08x\n",
|
||||
CFG_MEMTEST_START,
|
||||
CFG_MEMTEST_END);
|
||||
|
||||
printf("DRAM test phase 1:\n");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0xaaaaaaaa;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0xaaaaaaaa) {
|
||||
printf ("DRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
printf("DRAM test phase 2:\n");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0x55555555;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0x55555555) {
|
||||
printf ("DRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
printf("DRAM test passed.\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
/*************************************************************************
|
||||
* fixed_sdram init -- doesn't use serial presence detect.
|
||||
* assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
|
||||
************************************************************************/
|
||||
long int fixed_sdram (void)
|
||||
{
|
||||
#define CFG_DDR_CONTROL 0xc300c000
|
||||
|
||||
volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
|
||||
|
||||
ddr->cs0_bnds = 0x0000007f;
|
||||
ddr->cs1_bnds = 0x008000ff;
|
||||
ddr->cs2_bnds = 0x00000000;
|
||||
ddr->cs3_bnds = 0x00000000;
|
||||
ddr->cs0_config = 0x80010101;
|
||||
ddr->cs1_config = 0x80010101;
|
||||
ddr->cs2_config = 0x00000000;
|
||||
ddr->cs3_config = 0x00000000;
|
||||
ddr->ext_refrec = 0x00000000;
|
||||
ddr->timing_cfg_0 = 0x00220802;
|
||||
ddr->timing_cfg_1 = 0x38377322;
|
||||
ddr->timing_cfg_2 = 0x0fa044C7;
|
||||
ddr->sdram_cfg = 0x4300C000;
|
||||
ddr->sdram_cfg_2 = 0x24401000;
|
||||
ddr->sdram_mode = 0x23C00542;
|
||||
ddr->sdram_mode_2 = 0x00000000;
|
||||
ddr->sdram_interval = 0x05080100;
|
||||
ddr->sdram_md_cntl = 0x00000000;
|
||||
ddr->sdram_data_init = 0x00000000;
|
||||
ddr->sdram_clk_cntl = 0x03800000;
|
||||
asm("sync;isync;msync");
|
||||
udelay(500);
|
||||
|
||||
#if defined (CONFIG_DDR_ECC)
|
||||
/* Enable ECC checking */
|
||||
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
|
||||
#else
|
||||
ddr->sdram_cfg = CFG_DDR_CONTROL;
|
||||
#endif
|
||||
|
||||
return CFG_SDRAM_SIZE * 1024 * 1024;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
|
||||
/* For some reason the Tundra PCI bridge shows up on itself as a
|
||||
* different device. Work around that by refusing to configure it.
|
||||
*/
|
||||
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
|
||||
|
||||
static struct pci_config_table pci_sbc8548_config_table[] = {
|
||||
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
|
||||
{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
|
||||
{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
|
||||
mpc85xx_config_via_usbide, {0,0,0}},
|
||||
{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
|
||||
mpc85xx_config_via_usb, {0,0,0}},
|
||||
{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
|
||||
mpc85xx_config_via_usb2, {0,0,0}},
|
||||
{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
|
||||
mpc85xx_config_via_power, {0,0,0}},
|
||||
{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
|
||||
mpc85xx_config_via_ac97, {0,0,0}},
|
||||
{},
|
||||
};
|
||||
|
||||
static struct pci_controller pci1_hose = {
|
||||
config_table: pci_sbc8548_config_table};
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#ifdef CONFIG_PCI2
|
||||
static struct pci_controller pci2_hose;
|
||||
#endif /* CONFIG_PCI2 */
|
||||
|
||||
#ifdef CONFIG_PCIE1
|
||||
static struct pci_controller pcie1_hose;
|
||||
#endif /* CONFIG_PCIE1 */
|
||||
|
||||
int first_free_busno=0;
|
||||
|
||||
void
|
||||
pci_init_board(void)
|
||||
{
|
||||
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||
|
||||
#ifdef CONFIG_PCI1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pci1_hose;
|
||||
struct pci_config_table *table;
|
||||
|
||||
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
|
||||
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
|
||||
uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
|
||||
|
||||
uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
|
||||
|
||||
uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
|
||||
|
||||
if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
|
||||
printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
|
||||
(pci_32) ? 32 : 64,
|
||||
(pci_speed == 33333000) ? "33" :
|
||||
(pci_speed == 66666000) ? "66" : "unknown",
|
||||
pci_clk_sel ? "sync" : "async",
|
||||
pci_agent ? "agent" : "host",
|
||||
pci_arb ? "arbiter" : "external-arbiter"
|
||||
);
|
||||
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCI_MEMORY_BUS,
|
||||
CFG_PCI_MEMORY_PHYS,
|
||||
CFG_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
CFG_PCI1_MEM_BASE,
|
||||
CFG_PCI1_MEM_PHYS,
|
||||
CFG_PCI1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
CFG_PCI1_IO_BASE,
|
||||
CFG_PCI1_IO_PHYS,
|
||||
CFG_PCI1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
hose->region_count = 3;
|
||||
|
||||
/* relocate config table pointers */
|
||||
hose->config_table = \
|
||||
(struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
|
||||
for (table = hose->config_table; table && table->vendor; table++)
|
||||
table->config_device += gd->reloc_off;
|
||||
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
||||
fsl_pci_init(hose);
|
||||
first_free_busno=hose->last_busno+1;
|
||||
printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
|
||||
#ifdef CONFIG_PCIX_CHECK
|
||||
if (!(gur->pordevsr & PORDEVSR_PCI)) {
|
||||
/* PCI-X init */
|
||||
if (CONFIG_SYS_CLK_FREQ < 66000000)
|
||||
printf("PCI-X will only work at 66 MHz\n");
|
||||
|
||||
reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
|
||||
| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
|
||||
pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
|
||||
}
|
||||
#endif
|
||||
} else {
|
||||
printf (" PCI: disabled\n");
|
||||
}
|
||||
}
|
||||
#else
|
||||
gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI2
|
||||
{
|
||||
uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
|
||||
uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
|
||||
if (pci_dual) {
|
||||
printf (" PCI2: 32 bit, 66 MHz, %s\n",
|
||||
pci2_clk_sel ? "sync" : "async");
|
||||
} else {
|
||||
printf (" PCI2: disabled\n");
|
||||
}
|
||||
}
|
||||
#else
|
||||
gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
|
||||
#endif /* CONFIG_PCI2 */
|
||||
|
||||
#ifdef CONFIG_PCIE1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie1_hose;
|
||||
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
|
||||
|
||||
int pcie_configured = io_sel >= 1;
|
||||
|
||||
if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
printf ("\n PCIE connected to slot as %s (base address %x)",
|
||||
pcie_ep ? "End Point" : "Root Complex",
|
||||
(uint)pci);
|
||||
|
||||
if (pci->pme_msg_det) {
|
||||
pci->pme_msg_det = 0xffffffff;
|
||||
debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
|
||||
}
|
||||
printf ("\n");
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCI_MEMORY_BUS,
|
||||
CFG_PCI_MEMORY_PHYS,
|
||||
CFG_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
CFG_PCIE1_MEM_BASE,
|
||||
CFG_PCIE1_MEM_PHYS,
|
||||
CFG_PCIE1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
CFG_PCIE1_IO_BASE,
|
||||
CFG_PCIE1_IO_PHYS,
|
||||
CFG_PCIE1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
||||
fsl_pci_init(hose);
|
||||
printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
|
||||
|
||||
first_free_busno=hose->last_busno+1;
|
||||
|
||||
} else {
|
||||
printf (" PCIE: disabled\n");
|
||||
}
|
||||
}
|
||||
#else
|
||||
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
int last_stage_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int node, tmp[2];
|
||||
const char *path;
|
||||
|
||||
node = fdt_path_offset(blob, "/aliases");
|
||||
tmp[0] = 0;
|
||||
if (node >= 0) {
|
||||
#ifdef CONFIG_PCI1
|
||||
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE1
|
||||
path = fdt_getprop(blob, node, "pci1", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user