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https://xff.cz/git/u-boot/
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Merge git://git.denx.de/u-boot-marvell
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Tom Rini
@@ -1,86 +0,0 @@
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/*
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* (C) Copyright 2011
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Lei Wen <leiwen@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* This file should be included in board config header file.
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*
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* It supports common definitions for Armada XP platforms
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*/
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#ifndef _ARMADA_XP_CONFIG_H
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#define _ARMADA_XP_CONFIG_H
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#include <asm/arch/soc.h>
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#define MV88F78X60 /* for the DDR training bin_hdr code */
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#define CONFIG_SYS_CACHELINE_SIZE 32
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/*
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* By default kwbimage.cfg from board specific folder is used
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* If for some board, different configuration file need to be used,
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* CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
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*/
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#ifndef CONFIG_SYS_KWD_CONFIG
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#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
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#endif /* CONFIG_SYS_KWD_CONFIG */
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/* Add target to build it automatically upon "make" */
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#ifdef CONFIG_SPL
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#define CONFIG_BUILD_TARGET "u-boot-spl.kwb"
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#else
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#define CONFIG_BUILD_TARGET "u-boot.kwb"
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#endif
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/* end of 16M scrubbed by training in bootrom */
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#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000
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#define CONFIG_NR_DRAM_BANKS_MAX 2
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#define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE
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/*
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* SPI Flash configuration
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*/
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#ifdef CONFIG_CMD_SF
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#define CONFIG_HARD_SPI 1
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#define CONFIG_KIRKWOOD_SPI 1
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#ifndef CONFIG_ENV_SPI_BUS
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# define CONFIG_ENV_SPI_BUS 0
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#endif
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#ifndef CONFIG_ENV_SPI_CS
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# define CONFIG_ENV_SPI_CS 0
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#endif
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#ifndef CONFIG_ENV_SPI_MAX_HZ
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# define CONFIG_ENV_SPI_MAX_HZ 50000000
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#endif
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#endif
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/*
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* Ethernet Driver configuration
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*/
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#ifdef CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_MII /* expose smi ove miiphy interface */
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#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */
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#define CONFIG_PHYLIB
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#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
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#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */
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#endif /* CONFIG_CMD_NET */
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/*
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* I2C related stuff
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*/
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#ifdef CONFIG_CMD_I2C
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#ifndef CONFIG_SYS_I2C_SOFT
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#define CONFIG_I2C_MVTWSI
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#endif
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#define CONFIG_SYS_I2C_SLAVE 0x0
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#define CONFIG_SYS_I2C_SPEED 100000
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#endif
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#endif /* _ARMADA_XP_CONFIG_H */
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@@ -1,123 +0,0 @@
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ARMADA_XP_CPU_H
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#define _ARMADA_XP_CPU_H
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#include <asm/system.h>
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#ifndef __ASSEMBLY__
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#define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00)
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#define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08)
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enum memory_bank {
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BANK0,
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BANK1,
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BANK2,
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BANK3
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};
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enum cpu_winen {
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CPU_WIN_DISABLE,
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CPU_WIN_ENABLE
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};
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enum cpu_target {
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CPU_TARGET_DRAM = 0x0,
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CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
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CPU_TARGET_ETH23 = 0x3,
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CPU_TARGET_PCIE02 = 0x4,
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CPU_TARGET_ETH01 = 0x7,
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CPU_TARGET_PCIE13 = 0x8,
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CPU_TARGET_SASRAM = 0x9,
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CPU_TARGET_NAND = 0xd,
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};
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enum cpu_attrib {
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CPU_ATTR_SASRAM = 0x01,
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CPU_ATTR_DRAM_CS0 = 0x0e,
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CPU_ATTR_DRAM_CS1 = 0x0d,
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CPU_ATTR_DRAM_CS2 = 0x0b,
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CPU_ATTR_DRAM_CS3 = 0x07,
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CPU_ATTR_NANDFLASH = 0x2f,
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CPU_ATTR_SPIFLASH = 0x1e,
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CPU_ATTR_BOOTROM = 0x1d,
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CPU_ATTR_PCIE_IO = 0xe0,
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CPU_ATTR_PCIE_MEM = 0xe8,
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CPU_ATTR_DEV_CS0 = 0x3e,
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CPU_ATTR_DEV_CS1 = 0x3d,
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CPU_ATTR_DEV_CS2 = 0x3b,
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CPU_ATTR_DEV_CS3 = 0x37,
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};
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/*
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* Default Device Address MAP BAR values
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*/
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#define DEFADR_PCI_MEM 0x90000000
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#define DEFADR_PCI_IO 0xC0000000
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#define DEFADR_SPIF 0xF4000000
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#define DEFADR_BOOTROM 0xF8000000
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struct mbus_win {
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u32 base;
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u32 size;
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u8 target;
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u8 attr;
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};
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/*
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* System registers
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* Ref: Datasheet sec:A.28
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*/
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struct mvebu_system_registers {
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u8 pad1[0x60];
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u32 rstoutn_mask; /* 0x60 */
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u32 sys_soft_rst; /* 0x64 */
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};
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/*
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* GPIO Registers
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* Ref: Datasheet sec:A.19
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*/
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struct kwgpio_registers {
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u32 dout;
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u32 oe;
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u32 blink_en;
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u32 din_pol;
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u32 din;
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u32 irq_cause;
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u32 irq_mask;
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u32 irq_level;
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};
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/* Needed for dynamic (board-specific) mbus configuration */
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extern struct mvebu_mbus_state mbus_state;
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/*
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* functions
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*/
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unsigned int mvebu_sdram_bar(enum memory_bank bank);
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unsigned int mvebu_sdram_bs(enum memory_bank bank);
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void mvebu_sdram_size_adjust(enum memory_bank bank);
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int mvebu_mbus_probe(struct mbus_win windows[], int count);
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/*
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* Highspeed SERDES PHY config init, ported from bin_hdr
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* to mainline U-Boot
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*/
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int serdes_phy_config(void);
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/*
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* DDR3 init / training code ported from Marvell bin_hdr. Now
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* available in mainline U-Boot in:
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* drivers/ddr/mvebu/
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*/
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int ddr3_init(void);
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#endif /* __ASSEMBLY__ */
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#endif /* _ARMADA_XP_CPU_H */
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@@ -1,57 +0,0 @@
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* Header file for the Marvell's Feroceon CPU core.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_ARMADA_XP_H
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#define _ASM_ARCH_ARMADA_XP_H
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#define SOC_MV78460_ID 0x7846
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/* TCLK Core Clock definition */
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#ifndef CONFIG_SYS_TCLK
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#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
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#endif
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/* SOC specific definations */
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#define INTREG_BASE 0xd0000000
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#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
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#define SOC_REGS_PHY_BASE 0xf1000000
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#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
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#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
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#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600))
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#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
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#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))
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#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100))
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#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
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#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
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#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
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#define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180))
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#define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200))
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#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
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#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
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#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
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#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000))
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#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000))
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#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
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#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000))
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#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
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#define SDRAM_MAX_CS 4
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#define SDRAM_ADDR_MASK 0xFF000000
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/* Armada XP GbE controller has 4 ports */
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#define MAX_MVNETA_DEVS 4
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/* Kirkwood CPU memory windows */
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#define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA
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#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
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#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
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#endif /* _ASM_ARCH_ARMADA_XP_H */
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