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mirror of https://xff.cz/git/u-boot/ synced 2025-09-02 01:02:19 +02:00

Merge branch 'master' of git://git.denx.de/u-boot-mips

This commit is contained in:
Tom Rini
2017-05-10 15:50:21 -04:00
87 changed files with 3737 additions and 37 deletions

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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_CLOCK_BCM63268_H
#define __DT_BINDINGS_CLOCK_BCM63268_H
#define BCM63268_CLK_GLESS 0
#define BCM63268_CLK_VDSL_QPROC 1
#define BCM63268_CLK_VDSL_AFE 2
#define BCM63268_CLK_VDSL 3
#define BCM63268_CLK_MIPS 4
#define BCM63268_CLK_WLAN_OCP 5
#define BCM63268_CLK_DECT 6
#define BCM63268_CLK_FAP0 7
#define BCM63268_CLK_FAP1 8
#define BCM63268_CLK_SAR 9
#define BCM63268_CLK_ROBOSW 10
#define BCM63268_CLK_PCM 11
#define BCM63268_CLK_USBD 12
#define BCM63268_CLK_USBH 13
#define BCM63268_CLK_IPSEC 14
#define BCM63268_CLK_SPI 15
#define BCM63268_CLK_HSSPI 16
#define BCM63268_CLK_PCIE 17
#define BCM63268_CLK_PHYMIPS 18
#define BCM63268_CLK_GMAC 19
#define BCM63268_CLK_NAND 20
#define BCM63268_CLK_TBUS 27
#define BCM63268_CLK_ROBOSW250 31
#define BCM63268_TCLK_EPHY1 0
#define BCM63268_TCLK_EPHY2 1
#define BCM63268_TCLK_EPHY3 2
#define BCM63268_TCLK_GPHY 3
#define BCM63268_TCLK_DSL 4
#define BCM63268_TCLK_WO_EPHY 5
#define BCM63268_TCLK_WO_DSL 6
#define BCM63268_TCLK_FAP1 11
#define BCM63268_TCLK_FAP2 15
#define BCM63268_TCLK_UTO_50 16
#define BCM63268_TCLK_UTO_EXT 17
#define BCM63268_TCLK_USB_REF 18
#define BCM63268_TCLK_SW_RST 29
#define BCM63268_TCLK_HW_RST 30
#define BCM63268_TCLK_POR_RST 31
#endif /* __DT_BINDINGS_CLOCK_BCM63268_H */

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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_CLOCK_BCM6328_H
#define __DT_BINDINGS_CLOCK_BCM6328_H
#define BCM6328_CLK_PHYMIPS 0
#define BCM6328_CLK_ADSL_QPROC 1
#define BCM6328_CLK_ADSL_AFE 2
#define BCM6328_CLK_ADSL 3
#define BCM6328_CLK_MIPS 4
#define BCM6328_CLK_SAR 5
#define BCM6328_CLK_PCM 6
#define BCM6328_CLK_USBD 7
#define BCM6328_CLK_USBH 8
#define BCM6328_CLK_HSSPI 9
#define BCM6328_CLK_PCIE 10
#define BCM6328_CLK_ROBOSW 11
#endif /* __DT_BINDINGS_CLOCK_BCM6328_H */

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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_CLOCK_BCM6358_H
#define __DT_BINDINGS_CLOCK_BCM6358_H
#define BCM6358_CLK_ENET 4
#define BCM6358_CLK_ADSL 5
#define BCM6358_CLK_PCM 8
#define BCM6358_CLK_SPI 9
#define BCM6358_CLK_USBS 10
#define BCM6358_CLK_SAR 11
#define BCM6358_CLK_EMUSB 17
#define BCM6358_CLK_ENET0 18
#define BCM6358_CLK_ENET1 19
#define BCM6358_CLK_USBSU 20
#define BCM6358_CLK_EPHY 21
#endif /* __DT_BINDINGS_CLOCK_BCM6358_H */

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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM63268_H
#define __DT_BINDINGS_POWER_DOMAIN_BCM63268_H
#define BCM63268_PWR_SAR 0
#define BCM63268_PWR_IPSEC 1
#define BCM63268_PWR_MIPS 2
#define BCM63268_PWR_DECT 3
#define BCM63268_PWR_USBH 4
#define BCM63268_PWR_USBD 5
#define BCM63268_PWR_ROBOSW 6
#define BCM63268_PWR_PCM 7
#define BCM63268_PWR_PERIPH 8
#define BCM63268_PWR_VDSL_PHY 9
#define BCM63268_PWR_VDSL_MIPS 10
#define BCM63268_PWR_FAP 11
#define BCM63268_PWR_PCIE 12
#define BCM63268_PWR_WLAN_PADS 13
#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM63268_H */

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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6328_H
#define __DT_BINDINGS_POWER_DOMAIN_BCM6328_H
#define BCM6328_PWR_ADSL2_MIPS 0
#define BCM6328_PWR_ADSL2_PHY 1
#define BCM6328_PWR_ADSL2_AFE 2
#define BCM6328_PWR_SAR 3
#define BCM6328_PWR_PCM 4
#define BCM6328_PWR_USBD 5
#define BCM6328_PWR_USBH 6
#define BCM6328_PWR_PCIE 7
#define BCM6328_PWR_ROBOSW 8
#define BCM6328_PWR_EPHY 9
#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6328_H */

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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_RESET_BCM63268_H
#define __DT_BINDINGS_RESET_BCM63268_H
#define BCM63268_RST_SPI 0
#define BCM63268_RST_IPSEC 1
#define BCM63268_RST_EPHY 2
#define BCM63268_RST_SAR 3
#define BCM63268_RST_ENETSW 4
#define BCM63268_RST_USBS 5
#define BCM63268_RST_USBH 6
#define BCM63268_RST_PCM 7
#define BCM63268_RST_PCIE_CORE 8
#define BCM63268_RST_PCIE 9
#define BCM63268_RST_PCIE_EXT 10
#define BCM63268_RST_WLAN_SHIM 11
#define BCM63268_RST_DDR_PHY 12
#define BCM63268_RST_FAP0 13
#define BCM63268_RST_WLAN_UBUS 14
#define BCM63268_RST_DECT 15
#define BCM63268_RST_FAP1 16
#define BCM63268_RST_PCIE_HARD 17
#define BCM63268_RST_GPHY 18
#endif /* __DT_BINDINGS_RESET_BCM63268_H */

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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_RESET_BCM6328_H
#define __DT_BINDINGS_RESET_BCM6328_H
#define BCM6328_RST_SPI 0
#define BCM6328_RST_EPHY 1
#define BCM6328_RST_SAR 2
#define BCM6328_RST_ENETSW 3
#define BCM6328_RST_USBS 4
#define BCM6328_RST_USBH 5
#define BCM6328_RST_PCM 6
#define BCM6328_RST_PCIE_CORE 7
#define BCM6328_RST_PCIE 8
#define BCM6328_RST_PCIE_EXT 9
#define BCM6328_RST_PCIE_HARD 10
#endif /* __DT_BINDINGS_RESET_BCM6328_H */

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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_RESET_BCM6358_H
#define __DT_BINDINGS_RESET_BCM6358_H
#define BCM6358_RST_SPI 0
#define BCM6358_RST_ENET 2
#define BCM6358_RST_MPI 3
#define BCM6358_RST_EPHY 6
#define BCM6358_RST_SAR 7
#define BCM6358_RST_USBH 12
#define BCM6358_RST_PCM 13
#define BCM6358_RST_ADSL 14
#endif /* __DT_BINDINGS_RESET_BCM6358_H */