From 9340d8fe8bebf24441f15529b1a32d062158c65f Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 27 May 2019 01:45:11 +0100 Subject: [PATCH 01/13] sunxi: move CONFIG_SPL_TEXT_BASE from *_defconfig to Kconfig The choice of the SPL_TEXT_BASE is not really a decision that should be specified by each board's defconfig, as this setting is actually dictated by the SoC's memory map and the BootROM behaviour. To make this obvious and reduce the clutter in the defconfig files, let's specify the SoC constraints in the Kconfig stanza. This allows us to remove these lines from the defconfig files again. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Reviewed-by: Jagan Teki --- common/spl/Kconfig | 3 +++ configs/A10-OLinuXino-Lime_defconfig | 1 - configs/A10s-OLinuXino-M_defconfig | 1 - configs/A13-OLinuXinoM_defconfig | 1 - configs/A13-OLinuXino_defconfig | 1 - configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 - configs/A20-OLinuXino-Lime2_defconfig | 1 - configs/A20-OLinuXino-Lime_defconfig | 1 - configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 - configs/A20-OLinuXino_MICRO_defconfig | 1 - configs/A20-Olimex-SOM-EVB_defconfig | 1 - configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 - configs/A20-Olimex-SOM204-EVB_defconfig | 1 - configs/A33-OLinuXino_defconfig | 1 - configs/Ainol_AW1_defconfig | 1 - configs/Ampe_A76_defconfig | 1 - configs/Auxtek-T003_defconfig | 1 - configs/Auxtek-T004_defconfig | 1 - configs/Bananapi_M2_Ultra_defconfig | 1 - configs/Bananapi_defconfig | 1 - configs/Bananapi_m2m_defconfig | 1 - configs/Bananapro_defconfig | 1 - configs/CHIP_defconfig | 1 - configs/CHIP_pro_defconfig | 1 - configs/CSQ_CS908_defconfig | 1 - configs/Chuwi_V7_CW0825_defconfig | 1 - configs/Colombus_defconfig | 1 - configs/Cubieboard2_defconfig | 1 - configs/Cubieboard4_defconfig | 1 - configs/Cubieboard_defconfig | 1 - configs/Cubietruck_defconfig | 1 - configs/Cubietruck_plus_defconfig | 1 - configs/Empire_electronix_d709_defconfig | 1 - configs/Empire_electronix_m712_defconfig | 1 - configs/Hummingbird_A31_defconfig | 1 - configs/Hyundai_A7HD_defconfig | 1 - configs/Itead_Ibox_A20_defconfig | 1 - configs/Lamobo_R1_defconfig | 1 - configs/LicheePi_Zero_defconfig | 1 - configs/Linksprite_pcDuino3_Nano_defconfig | 1 - configs/Linksprite_pcDuino3_defconfig | 1 - configs/Linksprite_pcDuino_defconfig | 1 - configs/MK808C_defconfig | 1 - configs/MSI_Primo73_defconfig | 1 - configs/MSI_Primo81_defconfig | 1 - configs/Marsboard_A10_defconfig | 1 - configs/Mele_A1000G_quad_defconfig | 1 - configs/Mele_A1000_defconfig | 1 - configs/Mele_I7_defconfig | 1 - configs/Mele_M3_defconfig | 1 - configs/Mele_M5_defconfig | 1 - configs/Mele_M9_defconfig | 1 - configs/Merrii_A80_Optimus_defconfig | 1 - configs/Mini-X_defconfig | 1 - configs/Nintendo_NES_Classic_Edition_defconfig | 1 - configs/Orangepi_defconfig | 1 - configs/Orangepi_mini_defconfig | 1 - configs/Sinlinx_SinA31s_defconfig | 1 - configs/Sinlinx_SinA33_defconfig | 1 - configs/Sinovoip_BPI_M2_defconfig | 1 - configs/Sinovoip_BPI_M3_defconfig | 1 - configs/Sunchip_CX-A99_defconfig | 1 - configs/UTOO_P66_defconfig | 1 - configs/Wexler_TAB7200_defconfig | 1 - configs/Wits_Pro_A20_DKT_defconfig | 1 - configs/Wobo_i5_defconfig | 1 - configs/Yones_Toptech_BD1078_defconfig | 1 - configs/Yones_Toptech_BS1078_V2_defconfig | 1 - configs/a64-olinuxino_defconfig | 1 - configs/amarula_a64_relic_defconfig | 1 - configs/ba10_tv_box_defconfig | 1 - configs/bananapi_m1_plus_defconfig | 1 - configs/bananapi_m2_berry_defconfig | 1 - configs/bananapi_m2_plus_h3_defconfig | 1 - configs/bananapi_m2_plus_h5_defconfig | 1 - configs/bananapi_m2_zero_defconfig | 1 - configs/bananapi_m64_defconfig | 1 - configs/beelink_gs1_defconfig | 1 - configs/colorfly_e708_q1_defconfig | 1 - configs/difrnce_dit4350_defconfig | 1 - configs/dserve_dsrv9703c_defconfig | 1 - configs/emlid_neutis_n5_devboard_defconfig | 1 - configs/ga10h_v1_1_defconfig | 1 - configs/gt90h_v4_defconfig | 1 - configs/h8_homlet_v2_defconfig | 1 - configs/i12-tvbox_defconfig | 1 - configs/iNet_3F_defconfig | 1 - configs/iNet_3W_defconfig | 1 - configs/iNet_86VS_defconfig | 1 - configs/iNet_D978_rev2_defconfig | 1 - configs/icnova-a20-swac_defconfig | 1 - configs/inet1_defconfig | 1 - configs/inet86dz_defconfig | 1 - configs/inet97fv2_defconfig | 1 - configs/inet98v_rev2_defconfig | 1 - configs/inet9f_rev03_defconfig | 1 - configs/inet_q972_defconfig | 1 - configs/jesurun_q5_defconfig | 1 - configs/libretech_all_h3_cc_h2_plus_defconfig | 1 - configs/libretech_all_h3_cc_h3_defconfig | 1 - configs/libretech_all_h3_cc_h5_defconfig | 1 - configs/mixtile_loftq_defconfig | 1 - configs/mk802_a10s_defconfig | 1 - configs/mk802_defconfig | 1 - configs/mk802ii_defconfig | 1 - configs/nanopi_a64_defconfig | 1 - configs/nanopi_m1_defconfig | 1 - configs/nanopi_m1_plus_defconfig | 1 - configs/nanopi_neo2_defconfig | 1 - configs/nanopi_neo_air_defconfig | 1 - configs/nanopi_neo_defconfig | 1 - configs/nanopi_neo_plus2_defconfig | 1 - configs/oceanic_5205_5inmfd_defconfig | 1 - configs/orangepi_2_defconfig | 1 - configs/orangepi_lite2_defconfig | 1 - configs/orangepi_lite_defconfig | 1 - configs/orangepi_one_defconfig | 1 - configs/orangepi_one_plus_defconfig | 1 - configs/orangepi_pc2_defconfig | 1 - configs/orangepi_pc_defconfig | 1 - configs/orangepi_pc_plus_defconfig | 1 - configs/orangepi_plus2e_defconfig | 1 - configs/orangepi_plus_defconfig | 1 - configs/orangepi_prime_defconfig | 1 - configs/orangepi_r1_defconfig | 1 - configs/orangepi_win_defconfig | 1 - configs/orangepi_zero_defconfig | 1 - configs/orangepi_zero_plus2_defconfig | 1 - configs/orangepi_zero_plus_defconfig | 1 - configs/parrot_r16_defconfig | 1 - configs/pine64-lts_defconfig | 1 - configs/pine64_plus_defconfig | 1 - configs/pine_h64_defconfig | 1 - configs/pinebook_defconfig | 1 - configs/polaroid_mid2407pxe03_defconfig | 1 - configs/polaroid_mid2809pxe04_defconfig | 1 - configs/pov_protab2_ips9_defconfig | 1 - configs/q8_a13_tablet_defconfig | 1 - configs/q8_a23_tablet_800x480_defconfig | 1 - configs/q8_a33_tablet_1024x600_defconfig | 1 - configs/q8_a33_tablet_800x480_defconfig | 1 - configs/r7-tv-dongle_defconfig | 1 - configs/sopine_baseboard_defconfig | 1 - configs/sun8i_a23_evb_defconfig | 1 - configs/sunxi_Gemei_G9_defconfig | 1 - configs/tbs_a711_defconfig | 1 - configs/teres_i_defconfig | 1 - 147 files changed, 3 insertions(+), 146 deletions(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 126931baceb..7122c069b2d 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -116,6 +116,9 @@ config SPL_LDSCRIPT config SPL_TEXT_BASE hex "SPL Text Base" default ISW_ENTRY_ADDR if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE + default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I + default 0x20060 if MACH_SUN50I_H6 + default 0x00060 if ARCH_SUNXI default 0x0 help The address in memory that SPL will be running from. diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index 61b38b65d1f..a986bf880ef 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -11,7 +11,6 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index 7cc8b83013a..26c927ffde6 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -9,7 +9,6 @@ CONFIG_MMC1_CD_PIN="PG13" CONFIG_MMC_SUNXI_SLOT_EXTRA=1 CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index 1f8023ed9fa..1d48214aa43 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="PB10" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index 0010d095462..63c8a2a8952 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig index ed270f02db7..b00fcf34fde 100644 --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig @@ -13,7 +13,6 @@ CONFIG_SATAPWR="PC3" CONFIG_SPL_SPI_SUNXI=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index ec702ce6095..db1c25c6f8f 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -11,7 +11,6 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index 87badd6c3e8..e1e72ed3a3c 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -9,7 +9,6 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig index 39d3d7ff0df..62d878f4044 100644 --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig @@ -11,7 +11,6 @@ CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index 396730393c1..29efaf6bc48 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -12,7 +12,6 @@ CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index bad691112b7..59dfdcc4078 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -13,7 +13,6 @@ CONFIG_USB0_VBUS_DET="PH5" CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig index f343bb6e898..c41e4356a46 100644 --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig @@ -13,7 +13,6 @@ CONFIG_SATAPWR="PC3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig index 8f9d350faaa..38cc65bd5c0 100644 --- a/configs/A20-Olimex-SOM204-EVB_defconfig +++ b/configs/A20-Olimex-SOM204-EVB_defconfig @@ -12,7 +12,6 @@ CONFIG_SATAPWR="PC3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig index 893a5f2e339..4389856987f 100644 --- a/configs/A33-OLinuXino_defconfig +++ b/configs/A33-OLinuXino_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PB2" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig index f2db7077483..c44050f8995 100644 --- a/configs/Ainol_AW1_defconfig +++ b/configs/Ainol_AW1_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index f1c3b2e0d0d..0a2774761e8 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig index 5d55ccf5127..c0fb54749e6 100644 --- a/configs/Auxtek-T003_defconfig +++ b/configs/Auxtek-T003_defconfig @@ -8,7 +8,6 @@ CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig index be2a94a2de3..ae320b70336 100644 --- a/configs/Auxtek-T004_defconfig +++ b/configs/Auxtek-T004_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index 278e54fa14c..384820d939b 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -9,7 +9,6 @@ CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra" diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 5be660a6eed..86cc3a2f044 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -9,7 +9,6 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig index 7daaaa05664..87e2d34e4dd 100644 --- a/configs/Bananapi_m2m_defconfig +++ b/configs/Bananapi_m2m_defconfig @@ -10,7 +10,6 @@ CONFIG_MMC0_CD_PIN="PB4" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PH8" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index 5de48ae38d3..8636eab2387 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -11,7 +11,6 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig index f94de1f8ff5..95c564c407a 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index 5fd79985f7f..6cd500f3be9 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTDPARTS=y diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig index d5e9ae52540..d1ba5c87b7e 100644 --- a/configs/CSQ_CS908_defconfig +++ b/configs/CSQ_CS908_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index efe45c1f137..acd931c9103 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index 64c7f81b8b1..5e52388e7e8 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -17,7 +17,6 @@ CONFIG_VIDEO_LCD_PANEL_I2C_SDA="PA23" CONFIG_VIDEO_LCD_PANEL_I2C_SCL="PA24" CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig index c9bc1a8aeda..d1ff8fd1167 100644 --- a/configs/Cubieboard2_defconfig +++ b/configs/Cubieboard2_defconfig @@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig index 2abbd3366b2..013482094f5 100644 --- a/configs/Cubieboard4_defconfig +++ b/configs/Cubieboard4_defconfig @@ -12,7 +12,6 @@ CONFIG_USB0_ID_DET="PH16" CONFIG_USB1_VBUS_PIN="PH14" CONFIG_USB3_VBUS_PIN="PH15" CONFIG_AXP_GPIO=y -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig index 36b1a89e00b..1ff72708dde 100644 --- a/configs/Cubieboard_defconfig +++ b/configs/Cubieboard_defconfig @@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index 60885493310..ed8fbe9f2ae 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -13,7 +13,6 @@ CONFIG_SATAPWR="PH12" CONFIG_GMAC_TX_DELAY=1 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig index ef6a9d5d370..0573c1f2fa2 100644 --- a/configs/Cubietruck_plus_defconfig +++ b/configs/Cubietruck_plus_defconfig @@ -16,7 +16,6 @@ CONFIG_I2C0_ENABLE=y CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig index 07f32e24b7e..f5dd96d6e8c 100644 --- a/configs/Empire_electronix_d709_defconfig +++ b/configs/Empire_electronix_d709_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig index 82a4a063b24..b8c3c56a91c 100644 --- a/configs/Empire_electronix_m712_defconfig +++ b/configs/Empire_electronix_m712_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig index 6d8a9a39c1c..f7a7b736b2a 100644 --- a/configs/Hummingbird_A31_defconfig +++ b/configs/Hummingbird_A31_defconfig @@ -9,7 +9,6 @@ CONFIG_USB2_VBUS_PIN="" CONFIG_VIDEO_VGA_VIA_LCD=y CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index 89ae2414938..2b1b1ccfbba 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig index a5c7d62082f..f44fc9e935d 100644 --- a/configs/Itead_Ibox_A20_defconfig +++ b/configs/Itead_Ibox_A20_defconfig @@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig index da8a8350b04..0ce8c1110a9 100644 --- a/configs/Lamobo_R1_defconfig +++ b/configs/Lamobo_R1_defconfig @@ -10,7 +10,6 @@ CONFIG_SATAPWR="PB3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig index e71f06bc32f..760cb1b0680 100644 --- a/configs/LicheePi_Zero_defconfig +++ b/configs/LicheePi_Zero_defconfig @@ -4,7 +4,6 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_V3S=y CONFIG_DRAM_CLK=360 -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig index 5fce2b124e4..3277461b92e 100644 --- a/configs/Linksprite_pcDuino3_Nano_defconfig +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -10,7 +10,6 @@ CONFIG_SATAPWR="PH2" CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index 12082370140..ce07a8c7ec3 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -8,7 +8,6 @@ CONFIG_DRAM_ZQ=122 CONFIG_SATAPWR="PH2" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig index 7b73413ead1..9685757e305 100644 --- a/configs/Linksprite_pcDuino_defconfig +++ b/configs/Linksprite_pcDuino_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN4I=y CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig index 23da4da9b26..2da7a857a26 100644 --- a/configs/MK808C_defconfig +++ b/configs/MK808C_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig index e48e1a13c19..746e5686ab6 100644 --- a/configs/MSI_Primo73_defconfig +++ b/configs/MSI_Primo73_defconfig @@ -10,7 +10,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig index 1396784ff41..5eaf24aa89d 100644 --- a/configs/MSI_Primo81_defconfig +++ b/configs/MSI_Primo81_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig index b0d0c35edc5..2666f1b6013 100644 --- a/configs/Marsboard_A10_defconfig +++ b/configs/Marsboard_A10_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig index d321e941748..4d900c1950d 100644 --- a/configs/Mele_A1000G_quad_defconfig +++ b/configs/Mele_A1000G_quad_defconfig @@ -8,7 +8,6 @@ CONFIG_INITIAL_USB_SCAN_DELAY=2000 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index 672f4fed04d..fe6c0fa165a 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -8,7 +8,6 @@ CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig index e1e628d21a7..10c151f4e01 100644 --- a/configs/Mele_I7_defconfig +++ b/configs/Mele_I7_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig index c400f1305e6..b3b38a52886 100644 --- a/configs/Mele_M3_defconfig +++ b/configs/Mele_M3_defconfig @@ -9,7 +9,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig index f565dbc9fab..57b25bac02e 100644 --- a/configs/Mele_M5_defconfig +++ b/configs/Mele_M5_defconfig @@ -9,7 +9,6 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_VIDEO_COMPOSITE=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig index 7202bfd3a1b..70facee3852 100644 --- a/configs/Mele_M9_defconfig +++ b/configs/Mele_M9_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig index cc09533dd8a..288b5e6be83 100644 --- a/configs/Merrii_A80_Optimus_defconfig +++ b/configs/Merrii_A80_Optimus_defconfig @@ -12,7 +12,6 @@ CONFIG_USB0_ID_DET="PH3" CONFIG_USB1_VBUS_PIN="PH4" CONFIG_USB3_VBUS_PIN="PH5" CONFIG_AXP_GPIO=y -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index 03fa81e4a15..6000e397f23 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN4I=y CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig index 099a2bdc2e9..d0a788987c5 100644 --- a/configs/Nintendo_NES_Classic_Edition_defconfig +++ b/configs/Nintendo_NES_Classic_Edition_defconfig @@ -9,7 +9,6 @@ CONFIG_DRAM_ODT_EN=y CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTDPARTS=y # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index b1a7cbd03a5..2a7bfffc959 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -12,7 +12,6 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index 35f1b34278d..9f41fabddb2 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig index 31aa768e3e4..07144304038 100644 --- a/configs/Sinlinx_SinA31s_defconfig +++ b/configs/Sinlinx_SinA31s_defconfig @@ -11,7 +11,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=3 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index 586be356f46..978e856d79a 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig index d1ee98bcb1b..46ef97d7eb8 100644 --- a/configs/Sinovoip_BPI_M2_defconfig +++ b/configs/Sinovoip_BPI_M2_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig index 5174e287230..914fc9d5063 100644 --- a/configs/Sinovoip_BPI_M3_defconfig +++ b/configs/Sinovoip_BPI_M3_defconfig @@ -17,7 +17,6 @@ CONFIG_AXP_GPIO=y CONFIG_SATAPWR="PD25" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig index 8a9a072f8f0..c884d8f955a 100644 --- a/configs/Sunchip_CX-A99_defconfig +++ b/configs/Sunchip_CX-A99_defconfig @@ -12,7 +12,6 @@ CONFIG_USB0_VBUS_PIN="PH15" CONFIG_USB1_VBUS_PIN="PL7" CONFIG_USB3_VBUS_PIN="PL8" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index 78cd62c9bb6..5be41f1880a 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -20,7 +20,6 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_TL059WV5C0=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig index f75606ec68f..b7211184186 100644 --- a/configs/Wexler_TAB7200_defconfig +++ b/configs/Wexler_TAB7200_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig index 4e37650814d..954a6b777bc 100644 --- a/configs/Wits_Pro_A20_DKT_defconfig +++ b/configs/Wits_Pro_A20_DKT_defconfig @@ -12,7 +12,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig index 92d851fb06b..3a2c2877a89 100644 --- a/configs/Wobo_i5_defconfig +++ b/configs/Wobo_i5_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=432 CONFIG_MMC0_CD_PIN="PB3" CONFIG_USB1_VBUS_PIN="PG12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig index 376fc2f7977..9a4743ff6a2 100644 --- a/configs/Yones_Toptech_BD1078_defconfig +++ b/configs/Yones_Toptech_BD1078_defconfig @@ -19,7 +19,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig index b8c923e42eb..cd2b6744b84 100644 --- a/configs/Yones_Toptech_BS1078_V2_defconfig +++ b/configs/Yones_Toptech_BS1078_V2_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig index afc8cff1b13..65430c32fc2 100644 --- a/configs/a64-olinuxino_defconfig +++ b/configs/a64-olinuxino_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig index 4d546afd51b..d41eb346916 100644 --- a/configs/amarula_a64_relic_defconfig +++ b/configs/amarula_a64_relic_defconfig @@ -7,7 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index 49aa22c6046..dc47292ce0d 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -9,7 +9,6 @@ CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB2_VBUS_PIN="PH12" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig index 96c30231766..c534a548d8a 100644 --- a/configs/bananapi_m1_plus_defconfig +++ b/configs/bananapi_m1_plus_defconfig @@ -9,7 +9,6 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig index 36a2fce0db9..27999555b60 100644 --- a/configs/bananapi_m2_berry_defconfig +++ b/configs/bananapi_m2_berry_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=576 CONFIG_MMC0_CD_PIN="PH13" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-v40-bananapi-m2-berry" diff --git a/configs/bananapi_m2_plus_h3_defconfig b/configs/bananapi_m2_plus_h3_defconfig index f45fd5edeb1..87fa0a9b452 100644 --- a/configs/bananapi_m2_plus_h3_defconfig +++ b/configs/bananapi_m2_plus_h3_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/bananapi_m2_plus_h5_defconfig b/configs/bananapi_m2_plus_h5_defconfig index f7e23d4d082..bff6f37e280 100644 --- a/configs/bananapi_m2_plus_h5_defconfig +++ b/configs/bananapi_m2_plus_h5_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/bananapi_m2_zero_defconfig b/configs/bananapi_m2_zero_defconfig index 93d48807d49..8546674b239 100644 --- a/configs/bananapi_m2_zero_defconfig +++ b/configs/bananapi_m2_zero_defconfig @@ -5,7 +5,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 CONFIG_MMC0_CD_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig index 06d90ddfd61..0f5d5311369 100644 --- a/configs/bananapi_m64_defconfig +++ b/configs/bananapi_m64_defconfig @@ -7,7 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig index f16d0fee22f..f5de850d08b 100644 --- a/configs/beelink_gs1_defconfig +++ b/configs/beelink_gs1_defconfig @@ -7,7 +7,6 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x20060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig index 7d6cd30bf8a..c9d5d4d510d 100644 --- a/configs/colorfly_e708_q1_defconfig +++ b/configs/colorfly_e708_q1_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig index 02d233e2da8..3600863eca3 100644 --- a/configs/difrnce_dit4350_defconfig +++ b/configs/difrnce_dit4350_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig index e4f9d41a824..0a192a090a3 100644 --- a/configs/dserve_dsrv9703c_defconfig +++ b/configs/dserve_dsrv9703c_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/emlid_neutis_n5_devboard_defconfig b/configs/emlid_neutis_n5_devboard_defconfig index 3eb1ded80cc..c1307aa1c56 100644 --- a/configs/emlid_neutis_n5_devboard_defconfig +++ b/configs/emlid_neutis_n5_devboard_defconfig @@ -8,7 +8,6 @@ CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig index ba86f489b97..d8eceac37a0 100644 --- a/configs/ga10h_v1_1_defconfig +++ b/configs/ga10h_v1_1_defconfig @@ -17,7 +17,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig index c440504b34d..1cbee126e71 100644 --- a/configs/gt90h_v4_defconfig +++ b/configs/gt90h_v4_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig index d60576dc5f2..c1144c40941 100644 --- a/configs/h8_homlet_v2_defconfig +++ b/configs/h8_homlet_v2_defconfig @@ -11,7 +11,6 @@ CONFIG_USB1_VBUS_PIN="PL6" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig index 259bf4e5bae..629aea90eb0 100644 --- a/configs/i12-tvbox_defconfig +++ b/configs/i12-tvbox_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=384 CONFIG_MACPWR="PH21" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig index 935a11e7b8f..f7b2e4ff0d4 100644 --- a/configs/iNet_3F_defconfig +++ b/configs/iNet_3F_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig index a8294012371..38d80482e95 100644 --- a/configs/iNet_3W_defconfig +++ b/configs/iNet_3W_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig index 93bdddc7fb7..71442226a3c 100644 --- a/configs/iNet_86VS_defconfig +++ b/configs/iNet_86VS_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig index 1a8ee6bfbb1..c3fc0b290c5 100644 --- a/configs/iNet_D978_rev2_defconfig +++ b/configs/iNet_D978_rev2_defconfig @@ -17,7 +17,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig index ed54700a959..b745dac7386 100644 --- a/configs/icnova-a20-swac_defconfig +++ b/configs/icnova-a20-swac_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo CONFIG_VIDEO_LCD_POWER="PH22" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_UNZIP=y # CONFIG_CMD_FLASH is not set diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig index 25a907bd922..831b5d00416 100644 --- a/configs/inet1_defconfig +++ b/configs/inet1_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig index c007af9379a..77da9295847 100644 --- a/configs/inet86dz_defconfig +++ b/configs/inet86dz_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig index bc89a76e51d..a5e4c6a9dba 100644 --- a/configs/inet97fv2_defconfig +++ b/configs/inet97fv2_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig index b39c5f3c6ce..d96250d23ff 100644 --- a/configs/inet98v_rev2_defconfig +++ b/configs/inet98v_rev2_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig index d46c99f76ef..c19c10fba7c 100644 --- a/configs/inet9f_rev03_defconfig +++ b/configs/inet9f_rev03_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig index 19a3c4cd1ef..66c7628a0db 100644 --- a/configs/inet_q972_defconfig +++ b/configs/inet_q972_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index 3bd4a185244..974e63c61df 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -8,7 +8,6 @@ CONFIG_MACPWR="PH19" CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/libretech_all_h3_cc_h2_plus_defconfig b/configs/libretech_all_h3_cc_h2_plus_defconfig index 7d7f542edf5..7d42356993e 100644 --- a/configs/libretech_all_h3_cc_h2_plus_defconfig +++ b/configs/libretech_all_h3_cc_h2_plus_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/libretech_all_h3_cc_h3_defconfig b/configs/libretech_all_h3_cc_h3_defconfig index be827210939..7ef0000cd5e 100644 --- a/configs/libretech_all_h3_cc_h3_defconfig +++ b/configs/libretech_all_h3_cc_h3_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/libretech_all_h3_cc_h5_defconfig b/configs/libretech_all_h3_cc_h5_defconfig index ed2c6d5307c..1e224690223 100644 --- a/configs/libretech_all_h3_cc_h5_defconfig +++ b/configs/libretech_all_h3_cc_h5_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig index 8d286a2b073..4dce096d696 100644 --- a/configs/mixtile_loftq_defconfig +++ b/configs/mixtile_loftq_defconfig @@ -9,7 +9,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PH24" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig index c9dfa042115..48659dbb09a 100644 --- a/configs/mk802_a10s_defconfig +++ b/configs/mk802_a10s_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=432 CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig index 6ecabce3615..58986e3d9ca 100644 --- a/configs/mk802_defconfig +++ b/configs/mk802_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_USB2_VBUS_PIN="PH12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig index 4474d03c96d..243a19500c1 100644 --- a/configs/mk802ii_defconfig +++ b/configs/mk802ii_defconfig @@ -4,7 +4,6 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/nanopi_a64_defconfig b/configs/nanopi_a64_defconfig index 0845a5cba19..eb031e661f4 100644 --- a/configs/nanopi_a64_defconfig +++ b/configs/nanopi_a64_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/nanopi_m1_defconfig b/configs/nanopi_m1_defconfig index 1dc25388f71..f021d87190b 100644 --- a/configs/nanopi_m1_defconfig +++ b/configs/nanopi_m1_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig index 90edbd9b063..c676579e54e 100644 --- a/configs/nanopi_m1_plus_defconfig +++ b/configs/nanopi_m1_plus_defconfig @@ -8,7 +8,6 @@ CONFIG_MACPWR="PD6" CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig index 953fe2354f4..984d9ddb842 100644 --- a/configs/nanopi_neo2_defconfig +++ b/configs/nanopi_neo2_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig index 5ad90ddd160..bba31fc1bc2 100644 --- a/configs/nanopi_neo_air_defconfig +++ b/configs/nanopi_neo_air_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=408 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig index e7d6ce48621..af36ad43af7 100644 --- a/configs/nanopi_neo_defconfig +++ b/configs/nanopi_neo_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=408 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig index 4096a619b7f..3aa9ceaa6a5 100644 --- a/configs/nanopi_neo_plus2_defconfig +++ b/configs/nanopi_neo_plus2_defconfig @@ -9,7 +9,6 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/oceanic_5205_5inmfd_defconfig b/configs/oceanic_5205_5inmfd_defconfig index 645e02a76b6..219de7ae502 100644 --- a/configs/oceanic_5205_5inmfd_defconfig +++ b/configs/oceanic_5205_5inmfd_defconfig @@ -10,7 +10,6 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC0_CD_PIN="" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig index 803c0613b6c..a561a117d44 100644 --- a/configs/orangepi_2_defconfig +++ b/configs/orangepi_2_defconfig @@ -7,7 +7,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig index e5c2846eaaf..f6d023eea71 100644 --- a/configs/orangepi_lite2_defconfig +++ b/configs/orangepi_lite2_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H6=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x20060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig index 8621ca3ccde..8b274e651b0 100644 --- a/configs/orangepi_lite_defconfig +++ b/configs/orangepi_lite_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig index d51491d4c06..b56588a42e9 100644 --- a/configs/orangepi_one_defconfig +++ b/configs/orangepi_one_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_one_plus_defconfig b/configs/orangepi_one_plus_defconfig index 65537c422f7..a9d560a9176 100644 --- a/configs/orangepi_one_plus_defconfig +++ b/configs/orangepi_one_plus_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H6=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x20060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index 1069cc7122e..15ad3af991a 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -9,7 +9,6 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index e4626f076f2..7fe516ecf62 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig index a9e00fc7150..8586bfc1888 100644 --- a/configs/orangepi_pc_plus_defconfig +++ b/configs/orangepi_pc_plus_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig index 592fb9dc2f8..59294bc09b8 100644 --- a/configs/orangepi_plus2e_defconfig +++ b/configs/orangepi_plus2e_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index 6433d0bfbe3..e63295495b3 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -9,7 +9,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PG13" CONFIG_SATAPWR="PG11" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig index d862674aa5f..8a8266935f7 100644 --- a/configs/orangepi_prime_defconfig +++ b/configs/orangepi_prime_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_r1_defconfig b/configs/orangepi_r1_defconfig index 2b2d6f2f8e1..d80d83a5dbf 100644 --- a/configs/orangepi_r1_defconfig +++ b/configs/orangepi_r1_defconfig @@ -8,7 +8,6 @@ CONFIG_DRAM_CLK=624 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-r1" CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index 59e9639c182..5b800b59bb6 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig index c354c8bcd3a..69471de36b4 100644 --- a/configs/orangepi_zero_defconfig +++ b/configs/orangepi_zero_defconfig @@ -8,7 +8,6 @@ CONFIG_DRAM_CLK=624 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero" CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig index 76101791432..ed417dc3067 100644 --- a/configs/orangepi_zero_plus2_defconfig +++ b/configs/orangepi_zero_plus2_defconfig @@ -9,7 +9,6 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_zero_plus_defconfig b/configs/orangepi_zero_plus_defconfig index 671d871b8f4..ad3a6b739f8 100644 --- a/configs/orangepi_zero_plus_defconfig +++ b/configs/orangepi_zero_plus_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=624 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig index 56b476b518a..50147457b12 100644 --- a/configs/parrot_r16_defconfig +++ b/configs/parrot_r16_defconfig @@ -12,7 +12,6 @@ CONFIG_USB0_ID_DET="PD10" CONFIG_USB1_VBUS_PIN="PD12" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig index 0ee1e05d029..0da6b70ea88 100644 --- a/configs/pine64-lts_defconfig +++ b/configs/pine64-lts_defconfig @@ -10,7 +10,6 @@ CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig index c112ea03a3e..65ea32d1ffc 100644 --- a/configs/pine64_plus_defconfig +++ b/configs/pine64_plus_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_PINE64_DT_SELECTION=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index 5ac89b462ca..5fa279f2e78 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -7,7 +7,6 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x20060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/pinebook_defconfig b/configs/pinebook_defconfig index 75cb0569043..2760f8cc398 100644 --- a/configs/pinebook_defconfig +++ b/configs/pinebook_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_R_I2C_ENABLE=y -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig index a2be5183ff5..0186a694249 100644 --- a/configs/polaroid_mid2407pxe03_defconfig +++ b/configs/polaroid_mid2407pxe03_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig index 6ab4e4e2daf..265e6b85f92 100644 --- a/configs/polaroid_mid2809pxe04_defconfig +++ b/configs/polaroid_mid2809pxe04_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig index d94b3169a20..80cdacfd4d4 100644 --- a/configs/pov_protab2_ips9_defconfig +++ b/configs/pov_protab2_ips9_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig index 6607a48161e..8f81b9a7bfe 100644 --- a/configs/q8_a13_tablet_defconfig +++ b/configs/q8_a13_tablet_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig index c2eb17f0a9b..04132688ef8 100644 --- a/configs/q8_a23_tablet_800x480_defconfig +++ b/configs/q8_a23_tablet_800x480_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig index 2ceda4eb0bd..7367306ecf8 100644 --- a/configs/q8_a33_tablet_1024x600_defconfig +++ b/configs/q8_a33_tablet_1024x600_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig index 3cd7f8f4d20..03006e382c1 100644 --- a/configs/q8_a33_tablet_800x480_defconfig +++ b/configs/q8_a33_tablet_800x480_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig index 7fbe54172cc..500d5e95e36 100644 --- a/configs/r7-tv-dongle_defconfig +++ b/configs/r7-tv-dongle_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=384 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index acd6dd686eb..e47218cb6a0 100644 --- a/configs/sopine_baseboard_defconfig +++ b/configs/sopine_baseboard_defconfig @@ -11,7 +11,6 @@ CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig index ef1bd21298b..3543e958837 100644 --- a/configs/sun8i_a23_evb_defconfig +++ b/configs/sun8i_a23_evb_defconfig @@ -9,7 +9,6 @@ CONFIG_USB0_VBUS_PIN="axp_drivebus" CONFIG_USB0_VBUS_DET="axp_vbus_detect" CONFIG_USB1_VBUS_PIN="PH7" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig index 4bd60992cd0..62b6838a954 100644 --- a/configs/sunxi_Gemei_G9_defconfig +++ b/configs/sunxi_Gemei_G9_defconfig @@ -11,7 +11,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig index 5d6ffab975c..d56bf684686 100644 --- a/configs/tbs_a711_defconfig +++ b/configs/tbs_a711_defconfig @@ -13,7 +13,6 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH11" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_TEXT_BASE=0x60 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig index 1b57a487121..421a8d3d408 100644 --- a/configs/teres_i_defconfig +++ b/configs/teres_i_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PL7" CONFIG_I2C0_ENABLE=y -CONFIG_SPL_TEXT_BASE=0x10060 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set From a9e19b8ff783644f13dbf12d302c588e33da09a5 Mon Sep 17 00:00:00 2001 From: Marcus Cooper Date: Sun, 2 Jun 2019 08:38:40 +0200 Subject: [PATCH 02/13] sun8i: h3: Add support for the Beelink-x2 STB The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot, 2 USB ports( 1 * USB-2 Host, 1 USB OTG), a 10/100M ethernet port using the SoC's integrated PHY, Wifi via an sdio wifi chip, HDMI, an IR receiver, a dual colour LED and an optical S/PDIF connector. Linux commit details about the sun8i-h3-beelink-x2.dts sync: "ARM: dts: sun8i: h3: Add ethernet0 alias to Beelink X2" (sha1: cc4bddade114b696ab27c1a77cfc7040151306da) Signed-off-by: Marcus Cooper Reviewed-by: Jagan Teki --- arch/arm/dts/Makefile | 1 + arch/arm/dts/sun8i-h3-beelink-x2.dts | 216 +++++++++++++++++++++++++++ board/sunxi/MAINTAINERS | 6 + configs/beelink_x2_defconfig | 16 ++ 4 files changed, 239 insertions(+) create mode 100644 arch/arm/dts/sun8i-h3-beelink-x2.dts create mode 100644 configs/beelink_x2_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 39cf4c3b3d3..f5535078c72 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -482,6 +482,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h2-plus-orangepi-r1.dtb \ sun8i-h2-plus-orangepi-zero.dtb \ sun8i-h3-bananapi-m2-plus.dtb \ + sun8i-h3-beelink-x2.dtb \ sun8i-h3-libretech-all-h3-cc.dtb \ sun8i-h3-nanopi-m1.dtb \ sun8i-h3-nanopi-m1-plus.dtb \ diff --git a/arch/arm/dts/sun8i-h3-beelink-x2.dts b/arch/arm/dts/sun8i-h3-beelink-x2.dts new file mode 100644 index 00000000000..25540b7694d --- /dev/null +++ b/arch/arm/dts/sun8i-h3-beelink-x2.dts @@ -0,0 +1,216 @@ +/* + * Copyright (C) 2017 Marcus Cooper + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Beelink X2"; + compatible = "roofull,beelink-x2", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + ethernet0 = &emac; + ethernet1 = &sdiowifi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "beelink-x2:blue:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + + red { + label = "beelink-x2:red:standby"; + gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + }; + + sound_spdif { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + sdiowifi: sdio_wifi@1 { + reg = <1>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +®_usb0_vbus { + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pins_a>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on except for the OTG port */ + status = "okay"; + usb0_id_det-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA07 */ + usb0_vbus-supply = <®_usb0_vbus>; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index bdd1854197a..c7e9d3eda08 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -172,6 +172,12 @@ S: Maintained F: configs/beelink_gs1_defconfig F: arch/arm/dts/sun50i-h6-beelink-gs1.dts +BEELINK X2 BOARD +M: Marcus Cooper +S: Maintained +F: configs/beelink_x2_defconfig +F: arch/arm/dts/sun8i-h3-beelink-x2.dts + COLOMBUS BOARD M: Maxime Ripard S: Maintained diff --git a/configs/beelink_x2_defconfig b/configs/beelink_x2_defconfig new file mode 100644 index 00000000000..be946956faf --- /dev/null +++ b/configs/beelink_x2_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=567 +CONFIG_DRAM_ZQ=3881979 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-beelink-x2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CONSOLE_MUX=y +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y From 1a1d1df384579e1323c72e8ba888ce45bfc4e781 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 15 Jul 2019 02:27:04 +0100 Subject: [PATCH 03/13] sunxi: H6: DRAM: avoid memcpy() on MMIO registers Using memcpy() is, however tempting, not a good idea: It depends on the specific implementation of memcpy, also lacks barriers. In this particular case the first registers were written using 64-bit writes, and the last register using four separate single-byte writes. Replace the memcpy with a proper loop using the writel() accessor. Signed-off-by: Andre Przywara Tested-by: Jernej Skrabec Reviewed-by: Jernej Skrabec Reviewed-by: Jagan Teki --- arch/arm/mach-sunxi/dram_sun50i_h6.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index 5da90a2835d..e2f141eb9b4 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -182,6 +182,7 @@ static void mctl_set_timing_lpddr3(struct dram_para *para) (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; struct sunxi_mctl_phy_reg * const mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; + int i; u8 tccd = 2; u8 tfaw = max(ns_to_t(50), 4); @@ -237,8 +238,9 @@ static void mctl_set_timing_lpddr3(struct dram_para *para) u8 twr2rd = tcwl + 4 + 1 + twtr; u8 trd2wr = tcl + 4 + (tcksrea >> 1) - tcwl + 1; - /* set mode register */ - memcpy(mctl_phy->mr, mr_lpddr3, sizeof(mr_lpddr3)); + /* set mode registers */ + for (i = 0; i < ARRAY_SIZE(mr_lpddr3); i++) + writel(mr_lpddr3[i], &mctl_phy->mr[i]); /* set DRAM timing */ writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, From 65f80f58049a820e7d1ed7b0b0d233885ce6ebb2 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 15 Jul 2019 02:27:05 +0100 Subject: [PATCH 04/13] sunxi: H6: DRAM: follow recommended PHY init algorithm The DRAM controller manual suggests to first program the PHY initialisation parameters to the PHY_PIR register, and then set bit 0 to trigger the initialisation. This is also used in boot0. Follow this recommendation by setting bit 0 in a separate step. Signed-off-by: Andre Przywara Tested-by: Jernej Skrabec Reviewed-by: Jernej Skrabec Reviewed-by: Jagan Teki --- arch/arm/mach-sunxi/dram_sun50i_h6.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index e2f141eb9b4..7a8b724f081 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -75,12 +75,14 @@ static void mctl_core_init(struct dram_para *para) mctl_channel_init(para); } +/* PHY initialisation */ static void mctl_phy_pir_init(u32 val) { struct sunxi_mctl_phy_reg * const mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; - writel(val | BIT(0), &mctl_phy->pir); + writel(val, &mctl_phy->pir); + writel(val | BIT(0), &mctl_phy->pir); /* Start initialisation. */ mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0)); } From 770b85a4180e5173c57c3297a4e28647e041f63a Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 15 Jul 2019 02:27:06 +0100 Subject: [PATCH 05/13] sunxi: H6: move LPDDR3 timing definition into separate file Currently the H6 DRAM driver only supports one kind of LPDDR3 DRAM. Split the timing parameters for this LPDDR3 configuration into a separate file, to allow selecting an alternative later at compile time (as the sunxi-dw driver does). Signed-off-by: Andre Przywara Tested-by: Jernej Skrabec Reviewed-by: Jernej Skrabec Reviewed-by: Jagan Teki --- .../include/asm/arch-sunxi/dram_sun50i_h6.h | 27 ++++ arch/arm/mach-sunxi/Kconfig | 10 +- arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/dram_sun50i_h6.c | 150 +----------------- arch/arm/mach-sunxi/dram_timings/Makefile | 1 + arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c | 132 +++++++++++++++ configs/beelink_gs1_defconfig | 1 + configs/orangepi_lite2_defconfig | 1 + configs/orangepi_one_plus_defconfig | 1 + configs/pine_h64_defconfig | 1 + 10 files changed, 177 insertions(+), 148 deletions(-) create mode 100644 arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h index eeb4da5c3f3..54c47555566 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h @@ -287,6 +287,31 @@ check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0); #define DCR_DDR4 (4 << 0) #define DCR_DDR8BANK BIT(3) +/* + * The delay parameters allow to allegedly specify delay times of some + * unknown unit for each individual bit trace in each of the four data bytes + * the 32-bit wide access consists of. Also three control signals can be + * adjusted individually. + */ +#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) +/* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */ +#define WR_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 4) +/* + * The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN, + * Termination and Power down + */ +#define RD_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 6) +struct dram_para { + u32 clk; + enum sunxi_dram_type type; + u8 cols; + u8 rows; + u8 ranks; + const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; + const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; +}; + + static inline int ns_to_t(int nanoseconds) { const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; @@ -294,4 +319,6 @@ static inline int ns_to_t(int nanoseconds) return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); } +void mctl_set_timing_params(struct dram_para *para); + #endif /* _SUNXI_DRAM_SUN50I_H6_H */ diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 1669e62a6d2..d588936850d 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -340,7 +340,7 @@ config ARM_BOOT_HOOK_RMR This allows both the SPL and the U-Boot proper to be entered in either mode and switch to AArch64 if needed. -if SUNXI_DRAM_DW +if SUNXI_DRAM_DW || DRAM_SUN50I_H6 config SUNXI_DRAM_DDR3 bool @@ -370,6 +370,14 @@ config SUNXI_DRAM_LPDDR3_STOCK This option is the LPDDR3 timing used by the stock boot0 by Allwinner. +config SUNXI_DRAM_H6_LPDDR3 + bool "LPDDR3 DRAM chips on the H6 DRAM controller" + select SUNXI_DRAM_LPDDR3 + depends on DRAM_SUN50I_H6 + ---help--- + This option is the LPDDR3 timing used by the stock boot0 by + Allwinner. + config SUNXI_DRAM_DDR2_V3S bool "DDR2 found in V3s chip" select SUNXI_DRAM_DDR2 diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 43a93e30857..d129f334798 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -39,4 +39,5 @@ obj-$(CONFIG_SPL_SPI_SUNXI) += spl_spi_sunxi.o obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/ obj-$(CONFIG_DRAM_SUN50I_H6) += dram_sun50i_h6.o +obj-$(CONFIG_DRAM_SUN50I_H6) += dram_timings/ endif diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index 7a8b724f081..697b8af4ce8 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -32,33 +32,8 @@ * similar PHY is ZynqMP. */ -/* - * The delay parameters below allow to allegedly specify delay times of some - * unknown unit for each individual bit trace in each of the four data bytes - * the 32-bit wide access consists of. Also three control signals can be - * adjusted individually. - */ -#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) -/* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */ -#define WR_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 4) -/* - * The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN, - * Termination and Power down - */ -#define RD_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 6) -struct dram_para { - u32 clk; - enum sunxi_dram_type type; - u8 cols; - u8 rows; - u8 ranks; - const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; - const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; -}; - static void mctl_sys_init(struct dram_para *para); static void mctl_com_init(struct dram_para *para); -static void mctl_set_timing_lpddr3(struct dram_para *para); static void mctl_channel_init(struct dram_para *para); static void mctl_core_init(struct dram_para *para) @@ -67,7 +42,7 @@ static void mctl_core_init(struct dram_para *para) mctl_com_init(para); switch (para->type) { case SUNXI_DRAM_TYPE_LPDDR3: - mctl_set_timing_lpddr3(para); + mctl_set_timing_params(para); break; default: panic("Unsupported DRAM type!"); @@ -171,127 +146,6 @@ static void mctl_set_master_priority(void) MBUS_CONF(HDCP2, true, HIGH, 2, 100, 64, 32); } -static u32 mr_lpddr3[12] = { - 0x00000000, 0x00000043, 0x0000001a, 0x00000001, - 0x00000000, 0x00000000, 0x00000048, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000003, -}; - -/* TODO: flexible timing */ -static void mctl_set_timing_lpddr3(struct dram_para *para) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - struct sunxi_mctl_phy_reg * const mctl_phy = - (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; - int i; - - u8 tccd = 2; - u8 tfaw = max(ns_to_t(50), 4); - u8 trrd = max(ns_to_t(10), 2); - u8 trcd = max(ns_to_t(24), 2); - u8 trc = ns_to_t(70); - u8 txp = max(ns_to_t(8), 2); - u8 twtr = max(ns_to_t(8), 2); - u8 trtp = max(ns_to_t(8), 2); - u8 twr = max(ns_to_t(15), 2); - u8 trp = ns_to_t(18); - u8 tras = ns_to_t(42); - u8 twtr_sa = ns_to_t(5); - u8 tcksrea = ns_to_t(11); - u16 trefi = ns_to_t(3900) / 32; - u16 trfc = ns_to_t(210); - u16 txsr = ns_to_t(220); - - if (CONFIG_DRAM_CLK % 400 == 0) { - /* Round up these parameters */ - twtr_sa++; - tcksrea++; - } - - u8 tmrw = 5; - u8 tmrd = 5; - u8 tmod = 12; - u8 tcke = 3; - u8 tcksrx = 5; - u8 tcksre = 5; - u8 tckesr = 5; - u8 trasmax = CONFIG_DRAM_CLK / 60; - u8 txs = 4; - u8 txsdll = 4; - u8 txsabort = 4; - u8 txsfast = 4; - - u8 tcl = 5; /* CL 10 */ - u8 tcwl = 3; /* CWL 6 */ - u8 t_rdata_en = twtr_sa + 8; - - u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ - u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */ - u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */ - u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ - - u8 twtp = tcwl + 4 + twr + 1; - /* - * The code below for twr2rd and trd2wr follows the IP core's - * document from ZynqMP and i.MX7. The BSP has both number - * substracted by 2. - */ - u8 twr2rd = tcwl + 4 + 1 + twtr; - u8 trd2wr = tcl + 4 + (tcksrea >> 1) - tcwl + 1; - - /* set mode registers */ - for (i = 0; i < ARRAY_SIZE(mr_lpddr3); i++) - writel(mr_lpddr3[i], &mctl_phy->mr[i]); - - /* set DRAM timing */ - writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, - &mctl_ctl->dramtmg[0]); - writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]); - writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, - &mctl_ctl->dramtmg[2]); - writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]); - writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, - &mctl_ctl->dramtmg[4]); - writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, - &mctl_ctl->dramtmg[5]); - /* Value suggested by ZynqMP manual and used by libdram */ - writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]); - writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs, - &mctl_ctl->dramtmg[8]); - writel(txsr, &mctl_ctl->dramtmg[14]); - - clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30)); - writel(0, &mctl_ctl->dfimisc); - clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); - - /* - * Set timing registers of the PHY. - * Note: the PHY is clocked 2x from the DRAM frequency. - */ - writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1), - &mctl_phy->dtpr[0]); - writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]); - writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]); - writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8), - &mctl_phy->dtpr[3]); - writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]); - writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]); - writel(0x0505, &mctl_phy->dtpr[6]); - - /* Configure DFI timing */ - writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000, - &mctl_ctl->dfitmg0); - writel(0x040201, &mctl_ctl->dfitmg1); - - /* Configure PHY timing */ - writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]); - writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]); - - /* set refresh timing */ - writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg); -} - static void mctl_sys_init(struct dram_para *para) { struct sunxi_ccm_reg * const ccm = @@ -735,12 +589,14 @@ unsigned long sunxi_dram_init(void) (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; struct dram_para para = { .clk = CONFIG_DRAM_CLK, +#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3 .type = SUNXI_DRAM_TYPE_LPDDR3, .ranks = 2, .cols = 11, .rows = 14, .dx_read_delays = SUN50I_H6_DX_READ_DELAYS, .dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS, +#endif }; unsigned long size; diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile index 278a8a14cc2..0886a95968b 100644 --- a/arch/arm/mach-sunxi/dram_timings/Makefile +++ b/arch/arm/mach-sunxi/dram_timings/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o +obj-$(CONFIG_SUNXI_DRAM_H6_LPDDR3) += h6_lpddr3.o diff --git a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c new file mode 100644 index 00000000000..10008601134 --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c @@ -0,0 +1,132 @@ +/* + * sun50i H6 LPDDR3 timings + * + * (C) Copyright 2017 Icenowy Zheng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static u32 mr_lpddr3[12] = { + 0x00000000, 0x00000043, 0x0000001a, 0x00000001, + 0x00000000, 0x00000000, 0x00000048, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000003, +}; + +/* TODO: flexible timing */ +void mctl_set_timing_params(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + struct sunxi_mctl_phy_reg * const mctl_phy = + (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; + int i; + + u8 tccd = 2; + u8 tfaw = max(ns_to_t(50), 4); + u8 trrd = max(ns_to_t(10), 2); + u8 trcd = max(ns_to_t(24), 2); + u8 trc = ns_to_t(70); + u8 txp = max(ns_to_t(8), 2); + u8 twtr = max(ns_to_t(8), 2); + u8 trtp = max(ns_to_t(8), 2); + u8 twr = max(ns_to_t(15), 2); + u8 trp = ns_to_t(18); + u8 tras = ns_to_t(42); + u8 twtr_sa = ns_to_t(5); + u8 tcksrea = ns_to_t(11); + u16 trefi = ns_to_t(3900) / 32; + u16 trfc = ns_to_t(210); + u16 txsr = ns_to_t(220); + + if (CONFIG_DRAM_CLK % 400 == 0) { + /* Round up these parameters */ + twtr_sa++; + tcksrea++; + } + + u8 tmrw = 5; + u8 tmrd = 5; + u8 tmod = 12; + u8 tcke = 3; + u8 tcksrx = 5; + u8 tcksre = 5; + u8 tckesr = 5; + u8 trasmax = CONFIG_DRAM_CLK / 60; + u8 txs = 4; + u8 txsdll = 4; + u8 txsabort = 4; + u8 txsfast = 4; + + u8 tcl = 5; /* CL 10 */ + u8 tcwl = 3; /* CWL 6 */ + u8 t_rdata_en = twtr_sa + 8; + + u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ + u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */ + u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */ + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ + + u8 twtp = tcwl + 4 + twr + 1; + /* + * The code below for twr2rd and trd2wr follows the IP core's + * document from ZynqMP and i.MX7. The BSP has both number + * substracted by 2. + */ + u8 twr2rd = tcwl + 4 + 1 + twtr; + u8 trd2wr = tcl + 4 + (tcksrea >> 1) - tcwl + 1; + + /* set mode registers */ + for (i = 0; i < ARRAY_SIZE(mr_lpddr3); i++) + writel(mr_lpddr3[i], &mctl_phy->mr[i]); + + /* set DRAM timing */ + writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, + &mctl_ctl->dramtmg[0]); + writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]); + writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, + &mctl_ctl->dramtmg[2]); + writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]); + writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, + &mctl_ctl->dramtmg[4]); + writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, + &mctl_ctl->dramtmg[5]); + /* Value suggested by ZynqMP manual and used by libdram */ + writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]); + writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs, + &mctl_ctl->dramtmg[8]); + writel(txsr, &mctl_ctl->dramtmg[14]); + + clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30)); + writel(0, &mctl_ctl->dfimisc); + clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); + + /* + * Set timing registers of the PHY. + * Note: the PHY is clocked 2x from the DRAM frequency. + */ + writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1), + &mctl_phy->dtpr[0]); + writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]); + writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]); + writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8), + &mctl_phy->dtpr[3]); + writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]); + writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]); + writel(0x0505, &mctl_phy->dtpr[6]); + + /* Configure DFI timing */ + writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000, + &mctl_ctl->dfitmg0); + writel(0x040201, &mctl_ctl->dfitmg1); + + /* Configure PHY timing */ + writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]); + writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]); + + /* set refresh timing */ + writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg); +} diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig index f5de850d08b..eec4edd4c2d 100644 --- a/configs/beelink_gs1_defconfig +++ b/configs/beelink_gs1_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y +CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set diff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig index f6d023eea71..2d74fc4053d 100644 --- a/configs/orangepi_lite2_defconfig +++ b/configs/orangepi_lite2_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y +CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/orangepi_one_plus_defconfig b/configs/orangepi_one_plus_defconfig index a9d560a9176..3737ecd3789 100644 --- a/configs/orangepi_one_plus_defconfig +++ b/configs/orangepi_one_plus_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y +CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index 5fa279f2e78..a49bd6618fc 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y +CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set From 75a8a641f313f019c406433856a6793def53dc4d Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 15 Jul 2019 02:27:07 +0100 Subject: [PATCH 06/13] sunxi: H6: Add DDR3 support to DRAM controller driver At the moment the H6 DRAM driver only supports LPDDR3 DRAM. Extend the driver to cover DDR3 DRAM as well. The changes are partly motivated by looking at the ZynqMP register documentation, partly by looking at register dumps after boot0/libdram has initialised the controller. Many thanks to Jernej for contributing some fixes! Signed-off-by: Andre Przywara Tested-by: Jernej Skrabec Reviewed-by: Jernej Skrabec Reviewed-by: Jagan Teki --- .../include/asm/arch-sunxi/dram_sun50i_h6.h | 8 ++ arch/arm/mach-sunxi/dram_sun50i_h6.c | 82 ++++++++++++------- 2 files changed, 62 insertions(+), 28 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h index 54c47555566..0a1da023760 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h @@ -9,6 +9,8 @@ #ifndef _SUNXI_DRAM_SUN50I_H6_H #define _SUNXI_DRAM_SUN50I_H6_H +#include + enum sunxi_dram_type { SUNXI_DRAM_TYPE_DDR3 = 3, SUNXI_DRAM_TYPE_DDR4, @@ -16,6 +18,11 @@ enum sunxi_dram_type { SUNXI_DRAM_TYPE_LPDDR3, }; +static inline bool sunxi_dram_is_lpddr(int type) +{ + return type >= SUNXI_DRAM_TYPE_LPDDR2; +} + /* * The following information is mainly retrieved by disassembly and some FPGA * test code of sun50iw3 platform. @@ -286,6 +293,7 @@ check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0); #define DCR_DDR3 (3 << 0) #define DCR_DDR4 (4 << 0) #define DCR_DDR8BANK BIT(3) +#define DCR_DDR2T BIT(28) /* * The delay parameters allow to allegedly specify delay times of some diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index 697b8af4ce8..17649ffbf9c 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -42,6 +42,7 @@ static void mctl_core_init(struct dram_para *para) mctl_com_init(para); switch (para->type) { case SUNXI_DRAM_TYPE_LPDDR3: + case SUNXI_DRAM_TYPE_DDR3: mctl_set_timing_params(para); break; default: @@ -284,14 +285,11 @@ static void mctl_com_init(struct dram_para *para) mctl_set_addrmap(para); setbits_le32(&mctl_com->cr, BIT(31)); - /* - * This address is magic; it's in SID memory area, but there's no - * known definition of it. - * On my Pine H64 board it has content 7. - */ - if (readl(0x03006100) == 7) + + /* The bonding ID seems to be always 7. */ + if (readl(SUNXI_SIDC_BASE + 0x100) == 7) /* bonding ID */ clrbits_le32(&mctl_com->cr, BIT(27)); - else if (readl(0x03006100) == 3) + else if (readl(SUNXI_SIDC_BASE + 0x100) == 3) setbits_le32(&mctl_com->cr, BIT(27)); if (para->clk > 408) @@ -302,22 +300,37 @@ static void mctl_com_init(struct dram_para *para) reg_val = 0x3f00; clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val); - /* TODO: half DQ, non-LPDDR3 types */ - writel(MSTR_DEVICETYPE_LPDDR3 | MSTR_BUSWIDTH_FULL | - MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks) | - 0x80000000, &mctl_ctl->mstr); - writel(DCR_LPDDR3 | DCR_DDR8BANK | 0x400, &mctl_phy->dcr); + /* TODO: half DQ, DDR4 */ + reg_val = MSTR_BUSWIDTH_FULL | MSTR_BURST_LENGTH(8) | + MSTR_ACTIVE_RANKS(para->ranks); + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + reg_val |= MSTR_DEVICETYPE_LPDDR3; + if (para->type == SUNXI_DRAM_TYPE_DDR3) + reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE; + writel(reg_val | BIT(31), &mctl_ctl->mstr); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + reg_val = DCR_LPDDR3 | DCR_DDR8BANK; + if (para->type == SUNXI_DRAM_TYPE_DDR3) + reg_val = DCR_DDR3 | DCR_DDR8BANK | DCR_DDR2T; + writel(reg_val | 0x400, &mctl_phy->dcr); if (para->ranks == 2) writel(0x0303, &mctl_ctl->odtmap); else writel(0x0201, &mctl_ctl->odtmap); - /* TODO: non-LPDDR3 types */ - tmp = para->clk * 7 / 2000; - reg_val = 0x0400; - reg_val |= (tmp + 7) << 24; - reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16; + /* TODO: DDR4 */ + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) { + tmp = para->clk * 7 / 2000; + reg_val = 0x0400; + reg_val |= (tmp + 7) << 24; + reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16; + } else if (para->type == SUNXI_DRAM_TYPE_DDR3) { + reg_val = 0x06000400; /* TODO?: Use CL - CWL value in [7:0] */ + } else { + panic("Only (LP)DDR3 supported (type = %d)\n", para->type); + } writel(reg_val, &mctl_ctl->odtcfg); /* TODO: half DQ */ @@ -372,6 +385,9 @@ static void mctl_bit_delay_set(struct dram_para *para) setbits_le32(&mctl_phy->pgcr[0], BIT(26)); udelay(1); + if (para->type != SUNXI_DRAM_TYPE_LPDDR3) + return; + for (i = 1; i < 14; i++) { val = readl(&mctl_phy->acbdlr[i]); val += 0x0a0a0a0a; @@ -419,7 +435,8 @@ static void mctl_channel_init(struct dram_para *para) else clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000); - clrbits_le32(&mctl_phy->dtcr[1], BIT(1)); + if (sunxi_dram_is_lpddr(para->type)) + clrbits_le32(&mctl_phy->dtcr[1], BIT(1)); if (para->ranks == 2) { writel(0x00010001, &mctl_phy->rankidr); writel(0x20000, &mctl_phy->odtcr); @@ -428,8 +445,11 @@ static void mctl_channel_init(struct dram_para *para) writel(0x10000, &mctl_phy->odtcr); } - /* TODO: non-LPDDR3 types */ - clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040); + /* set bits [3:0] to 1? 0 not valid in ZynqMP d/s */ + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040); + else + clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000000); if (para->clk <= 792) { if (para->clk <= 672) { if (para->clk <= 600) @@ -459,12 +479,13 @@ static void mctl_channel_init(struct dram_para *para) writel(0x06060606, &mctl_phy->acbdlr[i]); } - /* TODO: non-LPDDR3 types */ - mctl_phy_pir_init(PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT | - PIR_QSGATE | PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE | - PIR_WREYE); + val = PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT | PIR_QSGATE | + PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE | PIR_WREYE; + if (para->type == SUNXI_DRAM_TYPE_DDR3) + val |= PIR_DRAMRST | PIR_WL; + mctl_phy_pir_init(val); - /* TODO: non-LPDDR3 types */ + /* TODO: DDR4 types ? */ for (i = 0; i < 4; i++) writel(0x00000909, &mctl_phy->dx[i].gcr[5]); @@ -520,7 +541,8 @@ static void mctl_channel_init(struct dram_para *para) panic("Error while initializing DRAM PHY!\n"); } - clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40); + if (sunxi_dram_is_lpddr(para->type)) + clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40); clrbits_le32(&mctl_phy->pgcr[1], 0x40); clrbits_le32(&mctl_ctl->dfimisc, BIT(0)); writel(1, &mctl_ctl->swctl); @@ -589,11 +611,15 @@ unsigned long sunxi_dram_init(void) (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; struct dram_para para = { .clk = CONFIG_DRAM_CLK, -#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3 - .type = SUNXI_DRAM_TYPE_LPDDR3, .ranks = 2, .cols = 11, .rows = 14, +#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3 + .type = SUNXI_DRAM_TYPE_LPDDR3, + .dx_read_delays = SUN50I_H6_DX_READ_DELAYS, + .dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS, +#elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333) + .type = SUNXI_DRAM_TYPE_DDR3, .dx_read_delays = SUN50I_H6_DX_READ_DELAYS, .dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS, #endif From 7656d3982a39127f38d5be4ab4e3f61500739ba7 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 15 Jul 2019 02:27:08 +0100 Subject: [PATCH 07/13] sunxi: H6: Add DDR3-1333 timings Add a routine to program the timing parameters for DDR3-1333 DRAM chips connected to the H6 DRAM controller. The values were gathered from doing back-calculations from a register dump, trying to match them up with the official JEDEC DDDR3 spec. If in doubt, the register dump values were taken for now, but the JEDEC recommendation were added as a comment. Many thanks to Jernej for contributing fixes! Signed-off-by: Andre Przywara Tested-by: Jernej Skrabec Reviewed-by: Jernej Skrabec Reviewed-by: Jagan Teki --- arch/arm/mach-sunxi/Kconfig | 8 + arch/arm/mach-sunxi/dram_timings/Makefile | 1 + .../mach-sunxi/dram_timings/h6_ddr3_1333.c | 144 ++++++++++++++++++ 3 files changed, 153 insertions(+) create mode 100644 arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index d588936850d..d4e7d89e9e3 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -378,6 +378,14 @@ config SUNXI_DRAM_H6_LPDDR3 This option is the LPDDR3 timing used by the stock boot0 by Allwinner. +config SUNXI_DRAM_H6_DDR3_1333 + bool "DDR3-1333 boot0 timings on the H6 DRAM controller" + select SUNXI_DRAM_DDR3 + depends on DRAM_SUN50I_H6 + ---help--- + This option is the DDR3 timing used by the boot0 on H6 TV boxes + which use a DDR3-1333 timing. + config SUNXI_DRAM_DDR2_V3S bool "DDR2 found in V3s chip" select SUNXI_DRAM_DDR2 diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile index 0886a95968b..0deb9911fd7 100644 --- a/arch/arm/mach-sunxi/dram_timings/Makefile +++ b/arch/arm/mach-sunxi/dram_timings/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o obj-$(CONFIG_SUNXI_DRAM_H6_LPDDR3) += h6_lpddr3.o +obj-$(CONFIG_SUNXI_DRAM_H6_DDR3_1333) += h6_ddr3_1333.o diff --git a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c new file mode 100644 index 00000000000..611eaa3024c --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c @@ -0,0 +1,144 @@ +/* + * sun50i H6 DDR3-1333 timings, as programmed by Allwinner's boot0 + * for some TV boxes with the H6 and DDR3 memory. + * + * The chips are probably able to be driven by a faster clock, but boot0 + * uses a more conservative timing (as usual). + * + * (C) Copyright 2018,2019 Arm Ltd. + * based on previous work by: + * (C) Copyright 2017 Icenowy Zheng + * + * References used: + * - JEDEC DDR3 SDRAM standard: JESD79-3F.pdf + * - Samsung K4B2G0446D datasheet + * - ZynqMP UG1087 register DDRC/PHY documentation + * + * Many thanks to Jernej Skrabec for contributing some fixes! + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* + * Only the first four are used for DDR3(?) + * MR0: BL8, seq. read burst, no test, fast exit (DLL on), no DLL reset, + * CAS latency (CL): 11, write recovery (WR): 12 + * MR1: DLL enabled, output strength RZQ/6, Rtt_norm RZQ/2, + * write levelling disabled, TDQS disabled, output buffer enabled + * MR2: manual full array self refresh, dynamic ODT off, + * CAS write latency (CWL): 8 + */ +static u32 mr_ddr3[7] = { + 0x00001c70, 0x00000040, 0x00000018, 0x00000000, + 0x00000000, 0x00000400, 0x00000848, +}; + +/* TODO: flexible timing */ +void mctl_set_timing_params(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + struct sunxi_mctl_phy_reg * const mctl_phy = + (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; + int i; + + u8 tccd = 2; /* JEDEC: 4nCK */ + u8 tfaw = ns_to_t(50); /* JEDEC: 30 ns w/ 1K pages */ + u8 trrd = max(ns_to_t(6), 4); /* JEDEC: max(6 ns, 4nCK) */ + u8 trcd = ns_to_t(15); /* JEDEC: 13.5 ns */ + u8 trc = ns_to_t(53); /* JEDEC: 49.5 ns */ + u8 txp = max(ns_to_t(6), 3); /* JEDEC: max(6 ns, 3nCK) */ + u8 twtr = max(ns_to_t(8), 2); /* JEDEC: max(7.5 ns, 4nCK) */ + u8 trtp = max(ns_to_t(8), 2); /* JEDEC: max(7.5 ns, 4nCK) */ + u8 twr = ns_to_t(15); /* JEDEC: 15 ns */ + u8 trp = ns_to_t(15); /* JEDEC: >= 13.75 ns */ + u8 tras = ns_to_t(38); /* JEDEC >= 36 ns, <= 9*trefi */ + u8 twtr_sa = 2; /* ? */ + u8 tcksrea = 4; /* ? */ + u16 trefi = ns_to_t(7800) / 32; /* JEDEC: 7.8us@Tcase <= 85C */ + u16 trfc = ns_to_t(350); /* JEDEC: 160 ns for 2Gb */ + u16 txsr = 4; /* ? */ + + u8 tmrw = 0; /* ? */ + u8 tmrd = 4; /* JEDEC: 4nCK */ + u8 tmod = max(ns_to_t(15), 12); /* JEDEC: max(15 ns, 12nCK) */ + u8 tcke = max(ns_to_t(6), 3); /* JEDEC: max(5.625 ns, 3nCK) */ + u8 tcksrx = max(ns_to_t(10), 5); /* JEDEC: max(10 ns, 5nCK) */ + u8 tcksre = max(ns_to_t(10), 5); /* JEDEC: max(10 ns, 5nCK) */ + u8 tckesr = tcke + 1; /* JEDEC: tCKE(min) + 1nCK */ + u8 trasmax = 24; /* JEDEC: tREFI * 9 */ + u8 txs = ns_to_t(360) / 32; /* JEDEC: max(5nCK,tRFC+10ns) */ + u8 txsdll = 4; /* JEDEC: 512 nCK */ + u8 txsabort = 4; /* ? */ + u8 txsfast = 4; /* ? */ + u8 tcl = 6; /* JEDEC: CL / 2 => 6 */ + u8 tcwl = 4; /* JEDEC: 8 */ + u8 t_rdata_en = 7; /* ? */ + + u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ + u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; + u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ + + u8 twtp = tcwl + 2 + twr; /* (WL + BL / 2 + tWR) / 2 */ + u8 twr2rd = tcwl + 2 + twtr; /* (WL + BL / 2 + tWTR) / 2 */ + u8 trd2wr = 5; /* (RL + BL / 2 + 2 - WL) / 2 */ + + if (tcl + 1 >= trtp + trp) + trtp = tcl + 2 - trp; + + /* set mode registers */ + for (i = 0; i < ARRAY_SIZE(mr_ddr3); i++) + writel(mr_ddr3[i], &mctl_phy->mr[i]); + + /* set DRAM timing */ + writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, + &mctl_ctl->dramtmg[0]); + writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]); + writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, + &mctl_ctl->dramtmg[2]); + writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]); + writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, + &mctl_ctl->dramtmg[4]); + writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, + &mctl_ctl->dramtmg[5]); + /* Value suggested by ZynqMP manual and used by libdram */ + writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]); + writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs, + &mctl_ctl->dramtmg[8]); + writel(txsr, &mctl_ctl->dramtmg[14]); + + clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30)); + writel(0, &mctl_ctl->dfimisc); + clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); + + /* + * Set timing registers of the PHY. + * Note: the PHY is clocked 2x from the DRAM frequency. + */ + writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1), + &mctl_phy->dtpr[0]); + writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]); + writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]); + writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8), + &mctl_phy->dtpr[3]); + writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]); + writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]); + writel(0x0505, &mctl_phy->dtpr[6]); + + /* Configure DFI timing */ + writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000, + &mctl_ctl->dfitmg0); + writel(0x040201, &mctl_ctl->dfitmg1); + + /* Configure PHY timing. Zynq uses different registers. */ + writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]); + writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]); + + /* set refresh timing */ + writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg); +} From 0824384bfb392898b0e8edf2b9fc6555a8dd6702 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 15 Jul 2019 02:27:09 +0100 Subject: [PATCH 08/13] sunxi: H6: Add DDR3 DRAM delay values Add some basic line delay values to be used with DDR3 DRAM chips on some H6 TV boxes. Taken from a register dump after boot0 initialised the DRAM. Put them as the default delay values for DDR3 DRAM until we know better. Signed-off-by: Jernej Skrabec Signed-off-by: Andre Przywara Reviewed-by: Jagan Teki --- arch/arm/mach-sunxi/dram_sun50i_h6.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index 17649ffbf9c..2a8275da3a6 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -594,17 +594,28 @@ unsigned long mctl_calc_size(struct dram_para *para) return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks; } -#define SUN50I_H6_DX_WRITE_DELAYS \ +#define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \ {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 0 }, \ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }} -#define SUN50I_H6_DX_READ_DELAYS \ +#define SUN50I_H6_LPDDR3_DX_READ_DELAYS \ {{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \ { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \ { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \ { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }} +#define SUN50I_H6_DDR3_DX_WRITE_DELAYS \ + {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }} +#define SUN50I_H6_DDR3_DX_READ_DELAYS \ + {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ + { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }} + unsigned long sunxi_dram_init(void) { struct sunxi_mctl_com_reg * const mctl_com = @@ -616,12 +627,12 @@ unsigned long sunxi_dram_init(void) .rows = 14, #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3 .type = SUNXI_DRAM_TYPE_LPDDR3, - .dx_read_delays = SUN50I_H6_DX_READ_DELAYS, - .dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS, + .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS, + .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS, #elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333) .type = SUNXI_DRAM_TYPE_DDR3, - .dx_read_delays = SUN50I_H6_DX_READ_DELAYS, - .dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS, + .dx_read_delays = SUN50I_H6_DDR3_DX_READ_DELAYS, + .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS, #endif }; From 10cfbaabc159e475861229d9b5e95b3d96168215 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sun, 23 Jun 2019 15:09:46 +0100 Subject: [PATCH 09/13] sunxi: move SUNXI_GPIO to Kconfig Probably for no particular reason SUNXI_GPIO was still defined the "old way", in header files only. Introduce SUNXI_GPIO to the Kconfig file in drivers/gpio to remove another line from our dreadful config_whitelist.txt. Signed-off-by: Andre Przywara Tested-by: Corentin Labbe # Pine-H64 Reviewed-by: Jagan Teki --- arch/arm/Kconfig | 1 + drivers/gpio/Kconfig | 6 ++++++ include/configs/sunxi-common.h | 3 --- scripts/config_whitelist.txt | 1 - 4 files changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 87541977259..60c4a07a328 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -936,6 +936,7 @@ config ARCH_SUNXI select SPL_STACK_R if SPL select SPL_SYS_MALLOC_SIMPLE if SPL select SPL_SYS_THUMB_BUILD if !ARM64 + select SUNXI_GPIO select SYS_NS16550 select SYS_THUMB_BUILD if !ARM64 select USB if DISTRO_DEFAULTS diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index fa1c99700f7..4532ed32110 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -215,6 +215,12 @@ config SANDBOX_GPIO_COUNT of 'anonymous' GPIOs that do not belong to any device or bank. Select a suitable value depending on your needs. +config SUNXI_GPIO + bool "Allwinner GPIO driver" + depends on ARCH_SUNXI + help + Support the GPIO device in Allwinner SoCs. + config XILINX_GPIO bool "Xilinx GPIO driver" depends on DM_GPIO diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index fceb812448f..7be94ee7d14 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -257,9 +257,6 @@ extern int soft_i2c_gpio_scl; #endif #endif /* ifdef CONFIG_REQUIRE_SERIAL_CONSOLE */ -/* GPIO */ -#define CONFIG_SUNXI_GPIO - #ifdef CONFIG_VIDEO_SUNXI /* * The amount of RAM to keep free at the top of RAM when relocating u-boot, diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 2c9cfb450d0..62bd882411e 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1832,7 +1832,6 @@ CONFIG_STV0991 CONFIG_STV0991_HZ CONFIG_STV0991_HZ_CLOCK CONFIG_ST_SMI -CONFIG_SUNXI_GPIO CONFIG_SUNXI_MAX_FB_SIZE CONFIG_SUVD3 CONFIG_SXNI855T From 0d3c77f5c3527090019eaff0ddbfc8d25b4c2959 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sun, 23 Jun 2019 15:09:47 +0100 Subject: [PATCH 10/13] sunxi: gpio: Enable support for H6 pin controller The Allwinner H6 pin controller is not really special, at least not when it comes to normal GPIO operation. Add the H6 compatible strings to the list of recognised strings, to make GPIOs work for H6 boards. Signed-off-by: Andre Przywara Tested-by: Corentin Labbe # Pine-H64 Reviewed-by: Jagan Teki --- drivers/gpio/sunxi_gpio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index cbed8d42b77..719efc2cef0 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -354,12 +354,14 @@ static const struct udevice_id sunxi_gpio_ids[] = { ID("allwinner,sun8i-v3s-pinctrl", a_all), ID("allwinner,sun9i-a80-pinctrl", a_all), ID("allwinner,sun50i-a64-pinctrl", a_all), + ID("allwinner,sun50i-h6-pinctrl", a_all), ID("allwinner,sun6i-a31-r-pinctrl", l_2), ID("allwinner,sun8i-a23-r-pinctrl", l_1), ID("allwinner,sun8i-a83t-r-pinctrl", l_1), ID("allwinner,sun8i-h3-r-pinctrl", l_1), ID("allwinner,sun9i-a80-r-pinctrl", l_3), ID("allwinner,sun50i-a64-r-pinctrl", l_1), + ID("allwinner,sun50i-h6-r-pinctrl", l_2), { } }; From 106c1300a5a54c61d9368e5afdb5282e7e4ef3d8 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sun, 23 Jun 2019 15:09:48 +0100 Subject: [PATCH 11/13] sunxi: clocks: Add H6 USB clock gates and resets To enable USB support in U-Boot, add the required clock and reset gates to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will pick them up from there automatically. Signed-off-by: Andre Przywara Tested-by: Corentin Labbe # Pine-H64 Reviewed-by: Jagan Teki --- drivers/clk/sunxi/clk_h6.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index 0bb00f449ac..105c15d8694 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -28,6 +28,22 @@ static struct ccu_clk_gate h6_gates[] = { [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)), [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)), + + [CLK_USB_PHY0] = GATE(0xa70, BIT(29)), + [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)), + + [CLK_USB_PHY1] = GATE(0xa74, BIT(29)), + + [CLK_USB_HSIC] = GATE(0xa7c, BIT(26)), + [CLK_USB_HSIC_12M] = GATE(0xa7c, BIT(27)), + [CLK_USB_PHY3] = GATE(0xa7c, BIT(29)), + [CLK_USB_OHCI3] = GATE(0xa7c, BIT(31)), + + [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)), + [CLK_BUS_OHCI3] = GATE(0xa8c, BIT(3)), + [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)), + [CLK_BUS_EHCI3] = GATE(0xa8c, BIT(7)), + [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)), }; static struct ccu_reset h6_resets[] = { @@ -43,6 +59,19 @@ static struct ccu_reset h6_resets[] = { [RST_BUS_SPI1] = RESET(0x96c, BIT(17)), [RST_BUS_EMAC] = RESET(0x97c, BIT(16)), + + [RST_USB_PHY0] = RESET(0xa70, BIT(30)), + + [RST_USB_PHY1] = RESET(0xa74, BIT(30)), + + [RST_USB_HSIC] = RESET(0xa7c, BIT(28)), + [RST_USB_PHY3] = RESET(0xa7c, BIT(30)), + + [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)), + [RST_BUS_OHCI3] = RESET(0xa8c, BIT(19)), + [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)), + [RST_BUS_EHCI3] = RESET(0xa8c, BIT(23)), + [RST_BUS_OTG] = RESET(0xa8c, BIT(24)), }; static const struct ccu_desc h6_ccu_desc = { From 35fa673e0e5f9e947f0bae9d170bd9c8b449a751 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sun, 23 Jun 2019 15:09:49 +0100 Subject: [PATCH 12/13] sunxi: phy: Add USB PHY support for Allwinner H6 The USB PHY used in the Allwinner H6 SoC has some pecularities (as usual), which require a small addition to the USB PHY driver: In this case the second PHY is PHY3, not PHY1, so we need to skip number 1 and 2 in the code. Just use the respective code from Linux for that. Signed-off-by: Andre Przywara Tested-by: Corentin Labbe # Pine-H64 Reviewed-by: Jagan Teki --- drivers/phy/allwinner/phy-sun4i-usb.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index f206fa3f5d4..5e8f87717f8 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -75,6 +75,7 @@ enum sun4i_usb_phy_type { sun8i_h3_phy, sun8i_v3s_phy, sun50i_a64_phy, + sun50i_h6_phy, }; struct sun4i_usb_phy_cfg { @@ -85,6 +86,7 @@ struct sun4i_usb_phy_cfg { bool dedicated_clocks; bool enable_pmu_unk1; bool phy0_dual_route; + int missing_phys; }; struct sun4i_usb_phy_info { @@ -349,6 +351,9 @@ static int sun4i_usb_phy_xlate(struct phy *phy, if (args->args_count >= data->cfg->num_phys) return -EINVAL; + if (data->cfg->missing_phys & BIT(args->args[0])) + return -ENODEV; + if (args->args_count) phy->id = args->args[0]; else @@ -429,6 +434,9 @@ static int sun4i_usb_phy_probe(struct udevice *dev) struct sun4i_usb_phy_info *info = &phy_info[i]; char name[16]; + if (data->cfg->missing_phys & BIT(i)) + continue; + phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus); if (phy->gpio_vbus >= 0) { ret = gpio_request(phy->gpio_vbus, "usb_vbus"); @@ -583,6 +591,17 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = { .phy0_dual_route = true, }; +static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = { + .num_phys = 4, + .type = sun50i_h6_phy, + .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, + .enable_pmu_unk1 = true, + .phy0_dual_route = true, + .missing_phys = BIT(1) | BIT(2), +}; + static const struct udevice_id sun4i_usb_phy_ids[] = { { .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg }, { .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg }, @@ -594,6 +613,7 @@ static const struct udevice_id sun4i_usb_phy_ids[] = { { .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg }, { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg }, { .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg}, + { .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg}, { } }; From f96238e253661b43168352010a2628957940bd4b Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sun, 23 Jun 2019 15:09:50 +0100 Subject: [PATCH 13/13] sunxi: H6: Enable USB for existing boards So far USB was not enabled for the Allwinner H6 boards, as the PHY driver was not ready and the clock gates were missing. Since this is now fixed, let's add the PHY and the OHCI/EHCI drivers to the build, for all existing H6 boards. Signed-off-by: Andre Przywara Tested-by: Corentin Labbe # Pine-H64 Reviewed-by: Jagan Teki --- arch/arm/mach-sunxi/Kconfig | 1 + configs/beelink_gs1_defconfig | 2 ++ configs/orangepi_lite2_defconfig | 2 ++ configs/orangepi_one_plus_defconfig | 2 ++ configs/pine_h64_defconfig | 3 +++ 5 files changed, 10 insertions(+) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index d4e7d89e9e3..ffdf09f29e4 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -300,6 +300,7 @@ config MACH_SUN50I_H6 select ARM64 select SUPPORT_SPL select FIT + select PHY_SUN4I_USB select SPL_LOAD_FIT select DRAM_SUN50I_H6 diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig index eec4edd4c2d..f142cde779f 100644 --- a/configs/beelink_gs1_defconfig +++ b/configs/beelink_gs1_defconfig @@ -14,3 +14,5 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-beelink-gs1" CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig index 2d74fc4053d..74c11d83551 100644 --- a/configs/orangepi_lite2_defconfig +++ b/configs/orangepi_lite2_defconfig @@ -11,3 +11,5 @@ CONFIG_MMC0_CD_PIN="PF6" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-lite2" +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_one_plus_defconfig b/configs/orangepi_one_plus_defconfig index 3737ecd3789..f86bb29e34b 100644 --- a/configs/orangepi_one_plus_defconfig +++ b/configs/orangepi_one_plus_defconfig @@ -11,3 +11,5 @@ CONFIG_MMC0_CD_PIN="PF6" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-one-plus" +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index a49bd6618fc..dd1368af39c 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -12,3 +12,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64" +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB3_VBUS_PIN="PL5"