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arm: mvebu: Add Marvell's integrated CPUs

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Marvell's switch chips with integrated CPUs (collectively referred to as
MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
(e.g. xor) are located at different addresses and DFX server exists as a
separate target on the MBUS (on Armada-38x it's just part of the core
complex registers).

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Chris Packham
2019-04-11 22:22:50 +12:00
committed by Stefan Roese
parent 237b629e4c
commit 0d0df46ee7
8 changed files with 80 additions and 4 deletions
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4
drivers/ddr/marvell/axp/xor_regs.h
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@@ -13,7 +13,11 @@
#define XOR_UNIT(chan) ((chan) >> 1)
#define XOR_CHAN(chan) ((chan) & 1)
#ifdef CONFIG_ARMADA_MSYS
#define MV_XOR_REGS_OFFSET(unit) (0xF0800)
#else
#define MV_XOR_REGS_OFFSET(unit) (0x60900)
#endif
#define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit))
/* XOR Engine Control Register Map */