From 9a3eddd263eeed29dadf0d6bd21ee84bd8e6209d Mon Sep 17 00:00:00 2001 From: Kursad Oney Date: Wed, 14 Aug 2019 15:18:32 +0200 Subject: [PATCH 01/31] spi: hsspi: allow to be used on bcm6858 and bcm63158 This IP exists in both MIPS and ARM cores, so we also allow to use this driver on bcm6858 and bcm63158. Signed-off-by: Kursad Oney Reviewed-by: Philippe Reynes Reviewed-by: Daniel Schwierzeck --- drivers/spi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8dd3213d485..b8ca2bdedd5 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -67,7 +67,7 @@ config ATMEL_SPI config BCM63XX_HSSPI bool "BCM63XX HSSPI driver" - depends on ARCH_BMIPS + depends on (ARCH_BMIPS || ARCH_BCM6858 || ARCH_BCM63158) help Enable the BCM6328 HSSPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Broadcom From c50d670c56109c001875cd72930810b2ddfb29e6 Mon Sep 17 00:00:00 2001 From: Kursad Oney Date: Wed, 14 Aug 2019 15:18:33 +0200 Subject: [PATCH 02/31] waitbit: Add the generic wait_for_bit macros for 16 and 32 bits. wait_for_bit_le32 and wait_for_bit_le16 use the raw I/O functions which would default to big-endian on BE systems. Create the generic equivalents to use the native endianness. Signed-off-by: Kursad Oney Reviewed-by: Philippe Reynes Reviewed-by: Daniel Schwierzeck --- include/wait_bit.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/wait_bit.h b/include/wait_bit.h index 82e09da5ca3..79da0811fe2 100644 --- a/include/wait_bit.h +++ b/include/wait_bit.h @@ -72,10 +72,12 @@ static inline int wait_for_bit_##sfx(const void *reg, \ BUILD_WAIT_FOR_BIT(8, u8, readb) BUILD_WAIT_FOR_BIT(le16, u16, readw) +BUILD_WAIT_FOR_BIT(16, u16, readw) #ifdef readw_be BUILD_WAIT_FOR_BIT(be16, u16, readw_be) #endif BUILD_WAIT_FOR_BIT(le32, u32, readl) +BUILD_WAIT_FOR_BIT(32, u32, readl) #ifdef readl_be BUILD_WAIT_FOR_BIT(be32, u32, readl_be) #endif From 3ae64e8f256c864c546913730f82e2ffbcadc06e Mon Sep 17 00:00:00 2001 From: Kursad Oney Date: Wed, 14 Aug 2019 15:18:34 +0200 Subject: [PATCH 03/31] spi: bcm63xx_hsspi: switch to raw I/O functions. Make the driver compatible with both big and little endian SOCs. Replace big-endian calls with their raw equivalents, expect for writing the command to FIFO. That still has to be in big-endian format. Signed-off-by: Kursad Oney Reviewed-by: Philippe Reynes Reviewed-by: Daniel Schwierzeck --- drivers/spi/bcm63xx_hsspi.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index 4f527fa74aa..730653118c1 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -120,9 +120,9 @@ static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode) /* clock polarity */ if (mode & SPI_CPOL) - setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); + setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); else - clrbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); + clrbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); return 0; } @@ -146,7 +146,7 @@ static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv, set = DIV_ROUND_UP(2048, set); set &= SPI_PFL_CLK_FREQ_MASK; set |= SPI_PFL_CLK_RSTLOOP_MASK; - writel_be(set, priv->regs + SPI_PFL_CLK_REG(plat->cs)); + writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs)); /* profile signal */ set = 0; @@ -164,7 +164,7 @@ static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv, if (priv->speed > SPI_MAX_SYNC_CLOCK) set |= SPI_PFL_SIG_ASYNCIN_MASK; - clrsetbits_be32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); + clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); /* global control */ set = 0; @@ -182,13 +182,13 @@ static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv, else set |= BIT(!plat->cs); - clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set); + clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set); } static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv) { /* restore cs polarities */ - clrsetbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK, + clrsetbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK, priv->cs_pols); } @@ -247,7 +247,7 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, SPI_PFL_MODE_MDWRSZ_MASK; if (plat->mode & SPI_3WIRE) val |= SPI_PFL_MODE_3WIRE_MASK; - writel_be(val, priv->regs + SPI_PFL_MODE_REG(plat->cs)); + writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs)); /* transfer loop */ while (data_bytes > 0) { @@ -262,7 +262,7 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, } /* set fifo operation */ - writew_be(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK), + writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)), priv->regs + HSSPI_FIFO_OP_REG); /* issue the transfer */ @@ -271,10 +271,10 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, SPI_CMD_PFL_MASK; val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK; - writel_be(val, priv->regs + SPI_CMD_REG); + writel(val, priv->regs + SPI_CMD_REG); /* wait for completion */ - ret = wait_for_bit_be32(priv->regs + SPI_STAT_REG, + ret = wait_for_bit_32(priv->regs + SPI_STAT_REG, SPI_STAT_SRCBUSY_MASK, false, 1000, false); if (ret) { @@ -381,16 +381,16 @@ static int bcm63xx_hsspi_probe(struct udevice *dev) return ret; /* initialize hardware */ - writel_be(0, priv->regs + SPI_IR_MASK_REG); + writel(0, priv->regs + SPI_IR_MASK_REG); /* clear pending interrupts */ - writel_be(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG); + writel(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG); /* enable clk gate */ - setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK); + setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK); /* read default cs polarities */ - priv->cs_pols = readl_be(priv->regs + SPI_CTL_REG) & + priv->cs_pols = readl(priv->regs + SPI_CTL_REG) & SPI_CTL_CS_POL_MASK; return 0; From b47f4891e5dded550f1eaee7daaac55b8c0bd76e Mon Sep 17 00:00:00 2001 From: Kursad Oney Date: Wed, 14 Aug 2019 15:18:35 +0200 Subject: [PATCH 04/31] spi: bcm63xx_hsspi: Continue init when using no reset and fixed-clock. The Broadcom ARM implementations do not yet have a clock framework so one can use a fixed clock as the root clock of the hsspi block. The fixed clock does not have an "enable" routine, since it's always enabled. So when we hit this issue, getting an ENOSYS return, do not bail but continue initialization. Similarly the block might already have been out of reset, say, when we are booting from a SPI device. So if the reset signal is not configured in the device tree, do not bail out and instead skip deasserting the reset. Signed-off-by: Kursad Oney Reviewed-by: Philippe Reynes --- drivers/spi/bcm63xx_hsspi.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index 730653118c1..e82b80c107c 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -349,32 +349,31 @@ static int bcm63xx_hsspi_probe(struct udevice *dev) return ret; ret = clk_enable(&clk); - if (ret < 0) + if (ret < 0 && ret != -ENOSYS) return ret; ret = clk_free(&clk); - if (ret < 0) + if (ret < 0 && ret != -ENOSYS) return ret; /* get clock rate */ ret = clk_get_by_name(dev, "pll", &clk); - if (ret < 0) + if (ret < 0 && ret != -ENOSYS) return ret; priv->clk_rate = clk_get_rate(&clk); ret = clk_free(&clk); - if (ret < 0) + if (ret < 0 && ret != -ENOSYS) return ret; /* perform reset */ ret = reset_get_by_index(dev, 0, &rst_ctl); - if (ret < 0) - return ret; - - ret = reset_deassert(&rst_ctl); - if (ret < 0) - return ret; + if (ret >= 0) { + ret = reset_deassert(&rst_ctl); + if (ret < 0) + return ret; + } ret = reset_free(&rst_ctl); if (ret < 0) From b2983d1f6dcec4c9d06596f2ab7e489c98304421 Mon Sep 17 00:00:00 2001 From: Kursad Oney Date: Wed, 14 Aug 2019 15:18:36 +0200 Subject: [PATCH 05/31] dt: bcm63158: Add hsspi controller This change adds the hsspi controller to the 63158 dtsi. Signed-off-by: Kursad Oney Reviewed-by: Philippe Reynes --- arch/arm/dts/bcm63158.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi index 175af380182..7dd28584384 100644 --- a/arch/arm/dts/bcm63158.dtsi +++ b/arch/arm/dts/bcm63158.dtsi @@ -10,6 +10,10 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + spi0 = &hsspi; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -67,6 +71,14 @@ u-boot,dm-pre-reloc; }; + hsspi_pll: hsspi-pll { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_osc>; + clock-mult = <2>; + clock-div = <1>; + }; + refclk50mhz: refclk50mhz { compatible = "fixed-clock"; #clock-cells = <0>; @@ -192,6 +204,19 @@ status = "disabled"; }; + hsspi: spi-controller@ff801000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xff801000 0x0 0x600>; + clocks = <&hsspi_pll>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + spi-max-frequency = <100000000>; + num-cs = <8>; + + status = "disabled"; + }; + nand: nand-controller@ff801800 { compatible = "brcm,nand-bcm63158", "brcm,brcmnand-v5.0", From ce9e2eedda269227f74ae8982a3d833a87e8f40c Mon Sep 17 00:00:00 2001 From: Kursad Oney Date: Wed, 14 Aug 2019 15:18:37 +0200 Subject: [PATCH 06/31] dt: bcm963158: add a spi-nor device This change adds a spi nor flash device to the bcm963158 board. Signed-off-by: Kursad Oney Reviewed-by: Philippe Reynes --- arch/arm/dts/bcm963158.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/dts/bcm963158.dts b/arch/arm/dts/bcm963158.dts index 85659440dae..c2bdd332745 100644 --- a/arch/arm/dts/bcm963158.dts +++ b/arch/arm/dts/bcm963158.dts @@ -125,3 +125,15 @@ label = "green:aggregate_link"; }; }; + +&hsspi { + status = "okay"; + + flash: mt25@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <25000000>; + }; +}; From 2a6abc61979b1da90da7ad211130c1f1841b3aa5 Mon Sep 17 00:00:00 2001 From: Kursad Oney Date: Wed, 14 Aug 2019 15:18:38 +0200 Subject: [PATCH 07/31] configs: Add hsspi/spi support to bcm963158. This commit enable the support of the spi-nor for the broadcom reference board bcm963158. Signed-off-by: Kursad Oney Reviewed-by: Philippe Reynes --- configs/bcm963158_ram_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig index 1d8a81e5e21..74557deec65 100644 --- a/configs/bcm963158_ram_defconfig +++ b/configs/bcm963158_ram_defconfig @@ -20,6 +20,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_GPIO=y CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y CONFIG_CMD_CACHE=y CONFIG_DOS_PARTITION=y CONFIG_ISO_PARTITION=y @@ -38,11 +39,17 @@ CONFIG_MTD=y CONFIG_NAND=y CONFIG_NAND_BRCMNAND=y CONFIG_NAND_BRCMNAND_63158=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_CONS_INDEX=0 CONFIG_DM_SERIAL=y CONFIG_SERIAL_SEARCH_ALL=y CONFIG_PL01X_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_BCM63XX_HSSPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_WDT_BCM6345=y From 906af4a72bb33d0f6b1169b47a1f5e28894c3a11 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Wed, 14 Aug 2019 15:18:39 +0200 Subject: [PATCH 08/31] dt: bcm6858: add hsspi controller This commit add a hsspi controller in the bcm6858 device tree. Signed-off-by: Philippe Reynes Reviewed-by: Kursad Oney --- arch/arm/dts/bcm6858.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi index 91f7787eb9b..02225621710 100644 --- a/arch/arm/dts/bcm6858.dtsi +++ b/arch/arm/dts/bcm6858.dtsi @@ -10,6 +10,10 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + spi0 = &hsspi; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -67,6 +71,14 @@ u-boot,dm-pre-reloc; }; + hsspi_pll: hsspi-pll { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_osc>; + clock-mult = <2>; + clock-div = <1>; + }; + refclk50mhz: refclk50mhz { compatible = "fixed-clock"; #clock-cells = <0>; @@ -192,6 +204,19 @@ status = "disabled"; }; + hsspi: spi-controller@ff801000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xff801000 0x0 0x600>; + clocks = <&hsspi_pll>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + spi-max-frequency = <100000000>; + num-cs = <8>; + + status = "disabled"; + }; + nand: nand-controller@ff801800 { compatible = "brcm,nand-bcm6858", "brcm,brcmnand-v5.0", From 05e93b3a134ebb17ac0c02014dc740581ea49545 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Wed, 14 Aug 2019 15:18:40 +0200 Subject: [PATCH 09/31] dt: bcm968580xref: add a spi-nor device This commit add a spi-nor device in the bcm96850xref device tree. Signed-off-by: Philippe Reynes Reviewed-by: Kursad Oney --- arch/arm/dts/bcm968580xref.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/dts/bcm968580xref.dts b/arch/arm/dts/bcm968580xref.dts index 861e9891a78..a034e38318b 100644 --- a/arch/arm/dts/bcm968580xref.dts +++ b/arch/arm/dts/bcm968580xref.dts @@ -124,3 +124,15 @@ label = "green:wps"; }; }; + +&hsspi { + status = "okay"; + + flash: mt25@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <25000000>; + }; +}; From 84a527bd0907ec66e5cccd81ce641d24a726a5f0 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Wed, 14 Aug 2019 15:18:41 +0200 Subject: [PATCH 10/31] bcm968580xref: enable spi-nor support This commit enable the support of the spi-nor for the broadcom reference board bcm968580xref. Signed-off-by: Philippe Reynes Reviewed-by: Kursad Oney --- configs/bcm968580xref_ram_defconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/configs/bcm968580xref_ram_defconfig b/configs/bcm968580xref_ram_defconfig index 62f9077a5cb..6c6f57d3ad6 100644 --- a/configs/bcm968580xref_ram_defconfig +++ b/configs/bcm968580xref_ram_defconfig @@ -16,6 +16,8 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y CONFIG_CMD_PART=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y CONFIG_DOS_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y @@ -33,11 +35,18 @@ CONFIG_MTD=y CONFIG_NAND=y CONFIG_NAND_BRCMNAND=y CONFIG_NAND_BRCMNAND_6858=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_CONS_INDEX=0 CONFIG_DM_SERIAL=y CONFIG_SERIAL_SEARCH_ALL=y CONFIG_BCM6345_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_BCM63XX_HSSPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_WDT_BCM6345=y From a9a3aadaddb4b968eb7133132a73646fc12ca39f Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Thu, 19 Sep 2019 16:18:39 +0200 Subject: [PATCH 11/31] spl: add a generic function board_init_f This commit add a generic function board_init_f that only initialize some device (for example serial). It avoid to define a board function only to launch the serial configuration. Signed-off-by: Philippe Reynes --- common/spl/Kconfig | 9 +++++++++ common/spl/spl.c | 18 ++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 92de9cd7443..282d246ea38 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -25,6 +25,15 @@ config SPL_FRAMEWORK supports MMC, NAND and YMODEM and other methods loading of U-Boot and the Linux Kernel. If unsure, say Y. +config SPL_FRAMEWORK_BOARD_INIT_F + bool "Define a generic function board_init_f" + depends on SPL_FRAMEWORK + help + Define a generic function board_init_f that: + - initialize the spl (spl_early_init) + - initialize the serial (preloader_console_init) + Unless you want to provide your own board_init_f, you should say Y. + config SPL_SIZE_LIMIT hex "Maximum size of SPL image" depends on SPL diff --git a/common/spl/spl.c b/common/spl/spl.c index 5fdd6d0d032..a9d3e847af5 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -555,6 +555,24 @@ static int boot_from_devices(struct spl_image_info *spl_image, return -ENODEV; } +#if defined(CONFIG_SPL_FRAMEWORK_BOARD_INIT_F) +void board_init_f(ulong dummy) +{ + if (CONFIG_IS_ENABLED(OF_CONTROL)) { + int ret; + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + } + + if (CONFIG_IS_ENABLED(SERIAL_SUPPORT)) + preloader_console_init(); +} +#endif + void board_init_r(gd_t *dummy1, ulong dummy2) { u32 spl_boot_list[] = { From 42d37450e50b3a763d95fe1ff46499b9e564596e Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Thu, 22 Aug 2019 12:26:49 +0200 Subject: [PATCH 12/31] pci: mediatek: add PCIe controller support for MT7623 This adds PCIe controller support for MT7623. This is adapted from the Linux version. Tested-by: Frank Wunderlich Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- drivers/pci/Kconfig | 8 ++ drivers/pci/Makefile | 1 + drivers/pci/pcie_mediatek.c | 279 ++++++++++++++++++++++++++++++++++++ 3 files changed, 288 insertions(+) create mode 100644 drivers/pci/pcie_mediatek.c diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index bdfc0c17963..19e7b50046a 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -151,4 +151,12 @@ config PCI_KEYSTONE help Say Y here if you want to enable PCI controller support on AM654 SoC. +config PCIE_MEDIATEK + bool "MediaTek PCIe Gen2 controller" + depends on DM_PCI + depends on ARCH_MEDIATEK + help + Say Y here if you want to enable Gen2 PCIe controller, + which could be found on MT7623 SoC family. + endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index e54a98b8c9c..b1d3dc8610b 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -39,3 +39,4 @@ obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \ obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o +obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c new file mode 100644 index 00000000000..a0dcb258b02 --- /dev/null +++ b/drivers/pci/pcie_mediatek.c @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek PCIe host controller driver. + * + * Copyright (c) 2017-2019 MediaTek Inc. + * Author: Ryder Lee + * Honghui Zhang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PCIe shared registers */ +#define PCIE_SYS_CFG 0x00 +#define PCIE_INT_ENABLE 0x0c +#define PCIE_CFG_ADDR 0x20 +#define PCIE_CFG_DATA 0x24 + +/* PCIe per port registers */ +#define PCIE_BAR0_SETUP 0x10 +#define PCIE_CLASS 0x34 +#define PCIE_LINK_STATUS 0x50 + +#define PCIE_PORT_INT_EN(x) BIT(20 + (x)) +#define PCIE_PORT_PERST(x) BIT(1 + (x)) +#define PCIE_PORT_LINKUP BIT(0) +#define PCIE_BAR_MAP_MAX GENMASK(31, 16) + +#define PCIE_BAR_ENABLE BIT(0) +#define PCIE_REVISION_ID BIT(0) +#define PCIE_CLASS_CODE (0x60400 << 8) +#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \ + ((((regn) >> 8) & GENMASK(3, 0)) << 24)) +#define PCIE_CONF_ADDR(regn, bdf) \ + (PCIE_CONF_REG(regn) | (bdf)) + +/* MediaTek specific configuration registers */ +#define PCIE_FTS_NUM 0x70c +#define PCIE_FTS_NUM_MASK GENMASK(15, 8) +#define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8) + +#define PCIE_FC_CREDIT 0x73c +#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16)) +#define PCIE_FC_CREDIT_VAL(x) ((x) << 16) + +struct mtk_pcie_port { + void __iomem *base; + struct list_head list; + struct mtk_pcie *pcie; + struct reset_ctl reset; + struct clk sys_ck; + struct phy phy; + u32 slot; +}; + +struct mtk_pcie { + void __iomem *base; + struct clk free_ck; + struct list_head ports; +}; + +static int mtk_pcie_config_address(struct udevice *udev, pci_dev_t bdf, + uint offset, void **paddress) +{ + struct mtk_pcie *pcie = dev_get_priv(udev); + + writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR); + *paddress = pcie->base + PCIE_CFG_DATA + (offset & 3); + + return 0; +} + +static int mtk_pcie_read_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + return pci_generic_mmap_read_config(bus, mtk_pcie_config_address, + bdf, offset, valuep, size); +} + +static int mtk_pcie_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + return pci_generic_mmap_write_config(bus, mtk_pcie_config_address, + bdf, offset, value, size); +} + +static const struct dm_pci_ops mtk_pcie_ops = { + .read_config = mtk_pcie_read_config, + .write_config = mtk_pcie_write_config, +}; + +static void mtk_pcie_port_free(struct mtk_pcie_port *port) +{ + list_del(&port->list); + free(port); +} + +static int mtk_pcie_startup_port(struct mtk_pcie_port *port) +{ + struct mtk_pcie *pcie = port->pcie; + u32 slot = PCI_DEV(port->slot << 11); + u32 val; + int err; + + /* assert port PERST_N */ + setbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot)); + /* de-assert port PERST_N */ + clrbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot)); + + /* 100ms timeout value should be enough for Gen1/2 training */ + err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val, + !!(val & PCIE_PORT_LINKUP), 100000); + if (err) + return -ETIMEDOUT; + + /* disable interrupt */ + clrbits_le32(pcie->base + PCIE_INT_ENABLE, + PCIE_PORT_INT_EN(port->slot)); + + /* map to all DDR region. We need to set it before cfg operation. */ + writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, + port->base + PCIE_BAR0_SETUP); + + /* configure class code and revision ID */ + writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); + + /* configure FC credit */ + writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot), + pcie->base + PCIE_CFG_ADDR); + clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FC_CREDIT_MASK, + PCIE_FC_CREDIT_VAL(0x806c)); + + /* configure RC FTS number to 250 when it leaves L0s */ + writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR); + clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FTS_NUM_MASK, + PCIE_FTS_NUM_L0(0x50)); + + return 0; +} + +static void mtk_pcie_enable_port(struct mtk_pcie_port *port) +{ + int err; + + err = clk_enable(&port->sys_ck); + if (err) + goto exit; + + err = reset_assert(&port->reset); + if (err) + goto exit; + + err = reset_deassert(&port->reset); + if (err) + goto exit; + + err = generic_phy_init(&port->phy); + if (err) + goto exit; + + err = generic_phy_power_on(&port->phy); + if (err) + goto exit; + + if (!mtk_pcie_startup_port(port)) + return; + + pr_err("Port%d link down\n", port->slot); +exit: + mtk_pcie_port_free(port); +} + +static int mtk_pcie_parse_port(struct udevice *dev, u32 slot) +{ + struct mtk_pcie *pcie = dev_get_priv(dev); + struct mtk_pcie_port *port; + char name[10]; + int err; + + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + snprintf(name, sizeof(name), "port%d", slot); + port->base = dev_remap_addr_name(dev, name); + if (!port->base) + return -ENOENT; + + snprintf(name, sizeof(name), "sys_ck%d", slot); + err = clk_get_by_name(dev, name, &port->sys_ck); + if (err) + return err; + + err = reset_get_by_index(dev, slot, &port->reset); + if (err) + return err; + + err = generic_phy_get_by_index(dev, slot, &port->phy); + if (err) + return err; + + port->slot = slot; + port->pcie = pcie; + + INIT_LIST_HEAD(&port->list); + list_add_tail(&port->list, &pcie->ports); + + return 0; +} + +static int mtk_pcie_probe(struct udevice *dev) +{ + struct mtk_pcie *pcie = dev_get_priv(dev); + struct mtk_pcie_port *port, *tmp; + ofnode subnode; + int err; + + INIT_LIST_HEAD(&pcie->ports); + + pcie->base = dev_remap_addr_name(dev, "subsys"); + if (!pcie->base) + return -ENOENT; + + err = clk_get_by_name(dev, "free_ck", &pcie->free_ck); + if (err) + return err; + + /* enable top level clock */ + err = clk_enable(&pcie->free_ck); + if (err) + return err; + + dev_for_each_subnode(subnode, dev) { + struct fdt_pci_addr addr; + u32 slot = 0; + + if (!ofnode_is_available(subnode)) + continue; + + err = ofnode_read_pci_addr(subnode, 0, "reg", &addr); + if (err) + return err; + + slot = PCI_DEV(addr.phys_hi); + + err = mtk_pcie_parse_port(dev, slot); + if (err) + return err; + } + + /* enable each port, and then check link status */ + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + mtk_pcie_enable_port(port); + + return 0; +} + +static const struct udevice_id mtk_pcie_ids[] = { + { .compatible = "mediatek,mt7623-pcie", }, + { } +}; + +U_BOOT_DRIVER(pcie_mediatek) = { + .name = "pcie_mediatek", + .id = UCLASS_PCI, + .of_match = mtk_pcie_ids, + .ops = &mtk_pcie_ops, + .probe = mtk_pcie_probe, + .priv_auto_alloc_size = sizeof(struct mtk_pcie), +}; From 235bad02e57db3f66473c45677a30886ddd01541 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Thu, 22 Aug 2019 12:26:50 +0200 Subject: [PATCH 13/31] phy: mediatek: add MediaTek T-PHY support for PCIe The driver provides PHY for USB2, USB3.0, PCIe and SATA, and now we just enable PCIe. As for the other functionalities will be added gradually in upcoming days. This is adapted from the Linux version. Tested-by: Frank Wunderlich Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- drivers/phy/Kconfig | 11 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-mtk-tphy.c | 362 +++++++++++++++++++++++++++++++++++++ 3 files changed, 374 insertions(+) create mode 100644 drivers/phy/phy-mtk-tphy.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 02312273e27..e317373a5c2 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -205,4 +205,15 @@ config MT76X8_USB_PHY This PHY is found on MT76x8 devices supporting USB. +config PHY_MTK_TPHY + bool "MediaTek T-PHY Driver" + depends on PHY + depends on ARCH_MEDIATEK + help + MediaTek T-PHY driver supports usb2.0, usb3.0 ports, PCIe and + SATA, and meanwhile supports two version T-PHY which have + different banks layout, the T-PHY with shared banks between + multi-ports is first version, otherwise is second veriosn, + so you can easily distinguish them by banks layout. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 3157f1b7ee5..43ce62e08cd 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -23,3 +23,4 @@ obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o +obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c new file mode 100644 index 00000000000..37014812567 --- /dev/null +++ b/drivers/phy/phy-mtk-tphy.c @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015 - 2019 MediaTek Inc. + * Author: Chunfeng Yun + * Ryder Lee + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* version V1 sub-banks offset base address */ +/* banks shared by multiple phys */ +#define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */ +#define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */ +/* u3/pcie/sata phy banks */ +#define SSUSB_SIFSLV_V1_U3PHYD 0x000 +#define SSUSB_SIFSLV_V1_U3PHYA 0x200 + +#define U3P_U3_CHIP_GPIO_CTLD 0x0c +#define P3C_REG_IP_SW_RST BIT(31) +#define P3C_MCU_BUS_CK_GATE_EN BIT(30) +#define P3C_FORCE_IP_SW_RST BIT(29) + +#define U3P_U3_CHIP_GPIO_CTLE 0x10 +#define P3C_RG_SWRST_U3_PHYD BIT(25) +#define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24) + +#define U3P_U3_PHYA_REG0 0x000 +#define P3A_RG_CLKDRV_OFF GENMASK(3, 2) +#define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2) + +#define U3P_U3_PHYA_REG1 0x004 +#define P3A_RG_CLKDRV_AMP GENMASK(31, 29) +#define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29) + +#define U3P_U3_PHYA_DA_REG0 0x100 +#define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) +#define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16) +#define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) +#define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12) +#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) +#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) + +#define U3P_U3_PHYA_DA_REG4 0x108 +#define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) +#define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) +#define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6) + +#define U3P_U3_PHYA_DA_REG5 0x10c +#define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) +#define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28) +#define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) +#define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12) + +#define U3P_U3_PHYA_DA_REG6 0x110 +#define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) +#define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16) + +#define U3P_U3_PHYA_DA_REG7 0x114 +#define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) +#define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16) + +#define U3P_U3_PHYA_DA_REG20 0x13c +#define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) +#define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16) + +#define U3P_U3_PHYA_DA_REG25 0x148 +#define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) +#define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x)) + +#define U3P_U3_PHYD_RXDET1 0x128 +#define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) +#define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9) + +#define U3P_U3_PHYD_RXDET2 0x12c +#define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) +#define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x)) + +struct u3phy_banks { + void __iomem *spllc; + void __iomem *chip; + void __iomem *phyd; /* include u3phyd_bank2 */ + void __iomem *phya; /* include u3phya_da */ +}; + +struct mtk_phy_instance { + void __iomem *port_base; + const struct device_node *np; + + struct u3phy_banks u3_banks; + + /* reference clock of anolog phy */ + struct clk ref_clk; + u32 index; + u8 type; +}; + +struct mtk_tphy { + void __iomem *sif_base; + struct mtk_phy_instance **phys; + int nphys; +}; + +static void pcie_phy_instance_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u3phy_banks *u3_banks = &instance->u3_banks; + + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0, + P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, + P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | + P3A_RG_XTAL_EXT_PE2H_VAL(0x2)); + + /* ref clk drive */ + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, + P3A_RG_CLKDRV_AMP_VAL(0x4)); + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, + P3A_RG_CLKDRV_OFF_VAL(0x1)); + + /* SSC delta -5000ppm */ + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20, + P3A_RG_PLL_DELTA1_PE2H, + P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c)); + + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25, + P3A_RG_PLL_DELTA_PE2H, + P3A_RG_PLL_DELTA_PE2H_VAL(0x36)); + + /* change pll BW 0.6M */ + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5, + P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H, + P3A_RG_PLL_BR_PE2H_VAL(0x1) | + P3A_RG_PLL_IC_PE2H_VAL(0x1)); + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4, + P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H, + P3A_RG_PLL_BC_PE2H_VAL(0x3)); + + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6, + P3A_RG_PLL_IR_PE2H, P3A_RG_PLL_IR_PE2H_VAL(0x2)); + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7, + P3A_RG_PLL_BP_PE2H, P3A_RG_PLL_BP_PE2H_VAL(0xa)); + + /* Tx Detect Rx Timing: 10us -> 5us */ + clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1, + P3D_RG_RXDET_STB2_SET, + P3D_RG_RXDET_STB2_SET_VAL(0x10)); + clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2, + P3D_RG_RXDET_STB2_SET_P3, + P3D_RG_RXDET_STB2_SET_P3_VAL(0x10)); + + /* wait for PCIe subsys register to active */ + udelay(3000); +} + +static void pcie_phy_instance_power_on(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u3phy_banks *bank = &instance->u3_banks; + + clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD, + P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST); + clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE, + P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); +} + +static void pcie_phy_instance_power_off(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) + +{ + struct u3phy_banks *bank = &instance->u3_banks; + + setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD, + P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST); + setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE, + P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); +} + +static void phy_v1_banks_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u3phy_banks *u3_banks = &instance->u3_banks; + + switch (instance->type) { + case PHY_TYPE_PCIE: + u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; + u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP; + u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; + u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; + break; + default: + return; + } +} + +static int mtk_phy_init(struct phy *phy) +{ + struct mtk_tphy *tphy = dev_get_priv(phy->dev); + struct mtk_phy_instance *instance = tphy->phys[phy->id]; + int ret; + + /* we may use a fixed-clock here */ + ret = clk_enable(&instance->ref_clk); + if (ret && ret != -ENOSYS) + return ret; + + switch (instance->type) { + case PHY_TYPE_PCIE: + pcie_phy_instance_init(tphy, instance); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int mtk_phy_power_on(struct phy *phy) +{ + struct mtk_tphy *tphy = dev_get_priv(phy->dev); + struct mtk_phy_instance *instance = tphy->phys[phy->id]; + + pcie_phy_instance_power_on(tphy, instance); + + return 0; +} + +static int mtk_phy_power_off(struct phy *phy) +{ + struct mtk_tphy *tphy = dev_get_priv(phy->dev); + struct mtk_phy_instance *instance = tphy->phys[phy->id]; + + pcie_phy_instance_power_off(tphy, instance); + + return 0; +} + +static int mtk_phy_exit(struct phy *phy) +{ + struct mtk_tphy *tphy = dev_get_priv(phy->dev); + struct mtk_phy_instance *instance = tphy->phys[phy->id]; + + clk_disable(&instance->ref_clk); + + return 0; +} + +static int mtk_phy_xlate(struct phy *phy, + struct ofnode_phandle_args *args) +{ + struct mtk_tphy *tphy = dev_get_priv(phy->dev); + struct mtk_phy_instance *instance = NULL; + const struct device_node *phy_np = ofnode_to_np(args->node); + u32 index; + + if (!phy_np) { + dev_err(phy->dev, "null pointer phy node\n"); + return -EINVAL; + } + + if (args->args_count < 1) { + dev_err(phy->dev, "invalid number of cells in 'phy' property\n"); + return -EINVAL; + } + + for (index = 0; index < tphy->nphys; index++) + if (phy_np == tphy->phys[index]->np) { + instance = tphy->phys[index]; + break; + } + + if (!instance) { + dev_err(phy->dev, "failed to find appropriate phy\n"); + return -EINVAL; + } + + phy->id = index; + instance->type = args->args[1]; + if (!(instance->type == PHY_TYPE_USB2 || + instance->type == PHY_TYPE_USB3 || + instance->type == PHY_TYPE_PCIE || + instance->type == PHY_TYPE_SATA)) { + dev_err(phy->dev, "unsupported device type\n"); + return -EINVAL; + } + + phy_v1_banks_init(tphy, instance); + + return 0; +} + +static const struct phy_ops mtk_tphy_ops = { + .init = mtk_phy_init, + .exit = mtk_phy_exit, + .power_on = mtk_phy_power_on, + .power_off = mtk_phy_power_off, + .of_xlate = mtk_phy_xlate, +}; + +static int mtk_tphy_probe(struct udevice *dev) +{ + struct mtk_tphy *tphy = dev_get_priv(dev); + ofnode subnode; + int index = 0; + + dev_for_each_subnode(subnode, dev) + tphy->nphys++; + + tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys), + GFP_KERNEL); + if (!tphy->phys) + return -ENOMEM; + + tphy->sif_base = dev_read_addr_ptr(dev); + if (!tphy->sif_base) + return -ENOENT; + + dev_for_each_subnode(subnode, dev) { + struct mtk_phy_instance *instance; + fdt_addr_t addr; + int err; + + instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL); + if (!instance) + return -ENOMEM; + + addr = ofnode_get_addr(subnode); + if (addr == FDT_ADDR_T_NONE) + return -ENOMEM; + + instance->port_base = map_sysmem(addr, 0); + instance->index = index; + instance->np = ofnode_to_np(subnode); + tphy->phys[index] = instance; + index++; + + err = clk_get_by_index_nodev(subnode, 0, &instance->ref_clk); + if (err) + return err; + } + + return 0; +} + +static const struct udevice_id mtk_tphy_id_table[] = { + { .compatible = "mediatek,generic-tphy-v1", }, + { } +}; + +U_BOOT_DRIVER(mtk_tphy) = { + .name = "mtk-tphy", + .id = UCLASS_PHY, + .of_match = mtk_tphy_id_table, + .ops = &mtk_tphy_ops, + .probe = mtk_tphy_probe, + .priv_auto_alloc_size = sizeof(struct mtk_tphy), +}; From 625137da44d260fa690fe73130a4bffaa41ee950 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Thu, 22 Aug 2019 12:26:51 +0200 Subject: [PATCH 14/31] arm: dts: add PCIe controller for MT7623 SoC This adds PCIe and its PHY nodes for MT7623. Tested-by: Frank Wunderlich Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- arch/arm/dts/mt7623.dtsi | 128 +++++++++++++++++++++++ arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 29 +++++ 2 files changed, 157 insertions(+) diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi index 64079c61bfb..3a868ea2ee8 100644 --- a/arch/arm/dts/mt7623.dtsi +++ b/arch/arm/dts/mt7623.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include "skeleton.dtsi" @@ -255,6 +256,133 @@ #reset-cells = <1>; }; + pcie: pcie@1a140000 { + compatible = "mediatek,mt7623-pcie"; + device_type = "pci"; + reg = <0x1a140000 0x1000>, /* PCIe shared registers */ + <0x1a142000 0x1000>, /* Port0 registers */ + <0x1a143000 0x1000>, /* Port1 registers */ + <0x1a144000 0x1000>; /* Port2 registers */ + reg-names = "subsys", "port0", "port1", "port2"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + resets = <&hifsys HIFSYS_PCIE0_RST>, + <&hifsys HIFSYS_PCIE1_RST>, + <&hifsys HIFSYS_PCIE2_RST>; + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phys = <&pcie0_port PHY_TYPE_PCIE>, + <&pcie1_port PHY_TYPE_PCIE>, + <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>; + bus-range = <0x00 0xff>; + status = "disabled"; + ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000 + 0x83000000 0 0x60000000 0x60000000 0 0x10000000>; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; + ranges; + status = "disabled"; + }; + + pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + ranges; + status = "disabled"; + }; + + pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + ranges; + status = "disabled"; + }; + }; + + pcie0_phy: pcie-phy@1a149000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a149000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pcie0_port: pcie-phy@1a149900 { + reg = <0x1a149900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + pcie1_phy: pcie-phy@1a14a000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a14a000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pcie1_port: pcie-phy@1a14a900 { + reg = <0x1a14a900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + u3phy2: usb-phy@1a244000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a244000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + u2port1: usb-phy@1a244800 { + reg = <0x1a244800 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb-phy@1a244900 { + reg = <0x1a244900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt7623-ethsys", "syscon"; reg = <0x1b000000 0x1000>; diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts index 51628bb6399..b0c86219b6c 100644 --- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts @@ -172,6 +172,13 @@ }; }; + pcie_default: pcie-default { + mux { + function = "pcie"; + groups = "pcie0_0_perst", "pcie1_0_perst"; + }; + }; + uart0_pins_a: uart0-default { mux { function = "uart"; @@ -201,6 +208,28 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default>; + status = "okay"; + + pcie@0,0 { + status = "okay"; + }; + + pcie@1,0 { + status = "okay"; + }; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; From 898cc1365c1adedeaf033838ab9e767c4dcdcdcf Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Thu, 22 Aug 2019 12:26:52 +0200 Subject: [PATCH 15/31] arm: dts: split mtk-reset.h into per-chip header This follows the linux header rules to avoid conflict bitfields. Tested-by: Frank Wunderlich Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- arch/arm/dts/mt7623.dtsi | 2 +- arch/arm/dts/mt7629.dtsi | 2 +- .../reset/{mtk-reset.h => mt7623-reset.h} | 4 +-- include/dt-bindings/reset/mt7629-reset.h | 36 +++++++++++++++++++ 4 files changed, 39 insertions(+), 5 deletions(-) rename include/dt-bindings/reset/{mtk-reset.h => mt7623-reset.h} (88%) create mode 100644 include/dt-bindings/reset/mt7629-reset.h diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi index 3a868ea2ee8..1135b1e1ae0 100644 --- a/arch/arm/dts/mt7623.dtsi +++ b/arch/arm/dts/mt7623.dtsi @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include "skeleton.dtsi" / { diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi index 8ff19162f06..b0c843bafde 100644 --- a/arch/arm/dts/mt7629.dtsi +++ b/arch/arm/dts/mt7629.dtsi @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include "skeleton.dtsi" / { diff --git a/include/dt-bindings/reset/mtk-reset.h b/include/dt-bindings/reset/mt7623-reset.h similarity index 88% rename from include/dt-bindings/reset/mtk-reset.h rename to include/dt-bindings/reset/mt7623-reset.h index 78fcdab009d..a859a5b26a4 100644 --- a/include/dt-bindings/reset/mtk-reset.h +++ b/include/dt-bindings/reset/mt7623-reset.h @@ -6,11 +6,9 @@ #ifndef _DT_BINDINGS_MTK_RESET_H_ #define _DT_BINDINGS_MTK_RESET_H_ -/* ETHSYS */ +/* ETHSYS resets */ #define ETHSYS_PPE_RST 31 -#define ETHSYS_EPHY_RST 24 #define ETHSYS_GMAC_RST 23 -#define ETHSYS_ESW_RST 16 #define ETHSYS_FE_RST 6 #define ETHSYS_MCM_RST 2 #define ETHSYS_SYS_RST 0 diff --git a/include/dt-bindings/reset/mt7629-reset.h b/include/dt-bindings/reset/mt7629-reset.h new file mode 100644 index 00000000000..8f1634f7a65 --- /dev/null +++ b/include/dt-bindings/reset/mt7629-reset.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_MTK_RESET_H_ +#define _DT_BINDINGS_MTK_RESET_H_ + +/* PCIe Subsystem resets */ +#define PCIE1_CORE_RST 19 +#define PCIE1_MMIO_RST 20 +#define PCIE1_HRST 21 +#define PCIE1_USER_RST 22 +#define PCIE1_PIPE_RST 23 +#define PCIE0_CORE_RST 27 +#define PCIE0_MMIO_RST 28 +#define PCIE0_HRST 29 +#define PCIE0_USER_RST 30 +#define PCIE0_PIPE_RST 31 + +/* SSUSB Subsystem resets */ +#define SSUSB_PHY_PWR_RST 3 +#define SSUSB_MAC_PWR_RST 4 + +/* ETH Subsystem resets */ +#define ETHSYS_SYS_RST 0 +#define ETHSYS_MCM_RST 2 +#define ETHSYS_HSDMA_RST 5 +#define ETHSYS_FE_RST 6 +#define ETHSYS_ESW_RST 16 +#define ETHSYS_GMAC_RST 23 +#define ETHSYS_EPHY_RST 24 +#define ETHSYS_CRYPTO_RST 29 +#define ETHSYS_PPE_RST 31 + +#endif /* _DT_BINDINGS_MTK_RESET_H_ */ From 825c47ee9d49a39687a3351dced45bbc10fee2f4 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Thu, 22 Aug 2019 12:26:53 +0200 Subject: [PATCH 16/31] dt-bindings: pcie: add a document for MT7623 PCIe controller This adds a document for MT7623 PCIe controller. Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- .../pci/mediatek-pcie.txt | 122 ++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 doc/device-tree-bindings/pci/mediatek-pcie.txt diff --git a/doc/device-tree-bindings/pci/mediatek-pcie.txt b/doc/device-tree-bindings/pci/mediatek-pcie.txt new file mode 100644 index 00000000000..2f9f549b7a3 --- /dev/null +++ b/doc/device-tree-bindings/pci/mediatek-pcie.txt @@ -0,0 +1,122 @@ +MediaTek Gen2 PCIe controller + +Required properties: +- compatible: Should contain one of the following strings: + "mediatek,mt7623-pcie" +- device_type: Must be "pci" +- reg: Base addresses and lengths of the PCIe subsys and root ports. +- reg-names: Names of the above areas to use during resource lookup. +- #address-cells: Address representation for root ports (must be 3) +- #size-cells: Size representation for root ports (must be 2) +- clocks: Must contain an entry for each entry in clock-names. +- clock-names: + Mandatory entries: + - sys_ckN :transaction layer and data link layer clock + Required entries for MT7623: + - free_ck :for reference clock of PCIe subsys + where N starting from 0 to one less than the number of root ports. +- phys: List of PHY specifiers (used by generic PHY framework). +- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the + number of PHYs as specified in *phys* property. +- power-domains: A phandle and power domain specifier pair to the power domain + which is responsible for collapsing and restoring power to the peripheral. +- bus-range: Range of bus numbers associated with this controller. +- ranges: Ranges for the PCI memory and I/O regions. + +Required properties for MT7623: +- #interrupt-cells: Size representation for interrupts (must be 1) +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties + Please refer to the standard PCI bus binding document for a more detailed + explanation. +- resets: Must contain an entry for each entry in reset-names. +- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the + number of root ports. + +In addition, the device tree node must have sub-nodes describing each +PCIe port interface, having the following mandatory properties: + +Required properties: +- device_type: Must be "pci" +- reg: Only the first four bytes are used to refer to the correct bus number + and device number. +- #address-cells: Must be 3 +- #size-cells: Must be 2 +- #interrupt-cells: Must be 1 +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties + Please refer to the standard PCI bus binding document for a more detailed + explanation. +- ranges: Sub-ranges distributed from the PCIe controller node. An empty + property is sufficient. + +Examples for MT7623: + + hifsys: syscon@1a000000 { + compatible = "mediatek,mt7623-hifsys", + "syscon"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pcie: pcie@1a140000 { + compatible = "mediatek,mt7623-pcie"; + device_type = "pci"; + reg = <0x1a140000 0x1000>, /* PCIe shared registers */ + <0x1a142000 0x1000>, /* Port0 registers */ + <0x1a143000 0x1000>, /* Port1 registers */ + <0x1a144000 0x1000>; /* Port2 registers */ + reg-names = "subsys", "port0", "port1", "port2"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + resets = <&hifsys HIFSYS_PCIE0_RST>, + <&hifsys HIFSYS_PCIE1_RST>, + <&hifsys HIFSYS_PCIE2_RST>; + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, + <&pcie2_phy PHY_TYPE_PCIE>; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000 /* I/O space */ + 0x83000000 0 0x60000000 0x60000000 0 0x10000000>; /* memory space */ + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + + pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + + pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + }; From 4024006e528b2f062024796c15293a820409c232 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Thu, 22 Aug 2019 12:26:54 +0200 Subject: [PATCH 17/31] dt-bindings: phy: add a document for MediaTek tphy This adds a document for tphy which supports physical layer functionality for a number of controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA. Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- doc/device-tree-bindings/phy/phy-mtk-tphy.txt | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 doc/device-tree-bindings/phy/phy-mtk-tphy.txt diff --git a/doc/device-tree-bindings/phy/phy-mtk-tphy.txt b/doc/device-tree-bindings/phy/phy-mtk-tphy.txt new file mode 100644 index 00000000000..037c5a4be5c --- /dev/null +++ b/doc/device-tree-bindings/phy/phy-mtk-tphy.txt @@ -0,0 +1,86 @@ +MediaTek T-PHY binding +-------------------------- + +T-phy controller supports physical layer functionality for a number of +controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA. + +Required properties (controller (parent) node): + - compatible : should be one of + "mediatek,generic-tphy-v1" + - clocks : (deprecated, use port's clocks instead) a list of phandle + + clock-specifier pairs, one for each entry in clock-names + - clock-names : (deprecated, use port's one instead) must contain + "u3phya_ref": for reference clock of usb3.0 analog phy. + +Required nodes : a sub-node is required for each port the controller + provides. Address range information including the usual + 'reg' property is used inside these nodes to describe + the controller's topology. + +Optional properties (controller (parent) node): + - reg : offset and length of register shared by multiple ports, + exclude port's private register. + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate + calibrate + - mediatek,src-coef : coefficient for slew rate calibrate, depends on + SoC process + +Required properties (port (child) node): +- reg : address and length of the register set for the port. +- clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names +- clock-names : must contain + "ref": 48M reference clock for HighSpeed analog phy; and 26M + reference clock for SuperSpeed analog phy, sometimes is + 24M, 25M or 27M, depended on platform. +- #phy-cells : should be 1 (See second example) + cell after port phandle is phy type from: + - PHY_TYPE_USB2 + - PHY_TYPE_USB3 + - PHY_TYPE_PCIE + - PHY_TYPE_SATA + +Example: + + u3phy2: usb-phy@1a244000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a244000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + u2port1: usb-phy@1a244800 { + reg = <0x1a244800 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb-phy@1a244900 { + reg = <0x1a244900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + +Specifying phy control of devices +--------------------------------- + +Device nodes should specify the configuration required in their "phys" +property, containing a phandle to the phy port node and a device type; +phy-names for each port are optional. + +Example: + +#include + +usb30: usb@11270000 { + ... + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + phy-names = "usb2-0", "usb3-0"; + ... +}; From 25643a5c3e5cecac1e73bfff04c414d12c302edc Mon Sep 17 00:00:00 2001 From: Oleksandr Rybalko Date: Thu, 22 Aug 2019 12:26:55 +0200 Subject: [PATCH 18/31] ahci-pci: ASM1061 report wrong class, but support AHCI. Tested-by: Frank Wunderlich Signed-off-by: Frank Wunderlich Signed-off-by: Oleksandr Rybalko --- drivers/ata/ahci-pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c index 1ca439d3fa4..11ec98b56f9 100644 --- a/drivers/ata/ahci-pci.c +++ b/drivers/ata/ahci-pci.c @@ -35,6 +35,7 @@ U_BOOT_DRIVER(ahci_pci) = { static struct pci_device_id ahci_pci_supported[] = { { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, ~0) }, + { PCI_DEVICE(0x1b21, 0x0611) }, {}, }; From 5b7a2bf318e1358f978180a51fd5a305723d165b Mon Sep 17 00:00:00 2001 From: Oleksandr Rybalko Date: Thu, 22 Aug 2019 12:26:56 +0200 Subject: [PATCH 19/31] ata: ahci: Don't forget to clear upper address regs. In 32bits mode upper bits need to be set to 0, otherwise controller will try to DMA into not existing memory and stops with error. Tested-by: Frank Wunderlich Signed-off-by: Frank Wunderlich Signed-off-by: Oleksandr Rybalko --- drivers/ata/ahci.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 9a08575053d..21a89eba5af 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -548,6 +548,7 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) { struct ahci_ioports *pp = &(uc_priv->port[port]); void __iomem *port_mmio = pp->port_mmio; + u64 dma_addr; u32 port_status; void __iomem *mem; @@ -593,10 +594,12 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) pp->cmd_tbl_sg = (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); - writel_with_flush((unsigned long)pp->cmd_slot, - port_mmio + PORT_LST_ADDR); - - writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); + dma_addr = (ulong)pp->cmd_slot; + writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR); + writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI); + dma_addr = (ulong)pp->rx_fis; + writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR); + writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI); #ifdef CONFIG_SUNXI_AHCI sunxi_dma_init(port_mmio); From e8e9715df2d408c57d14addff94105001c82f2ac Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 26 Aug 2019 13:50:31 +0200 Subject: [PATCH 20/31] regulator: fixed: Modify enable-active-high behavior Regulator should not be enabled at probe time if regulator-boot-on property is not in the dt node. "enable-active-high" property is only used to indicate the GPIO polarity. See kernel documentation : - Documentation/devicetree/bindings/regulator/fixed-regulator.yaml - Documentation/devicetree/bindings/regulator/gpio-regulator.yaml Signed-off-by: Christophe Kerello Signed-off-by: Patrice Chotard --- drivers/power/regulator/regulator_common.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/power/regulator/regulator_common.c b/drivers/power/regulator/regulator_common.c index 3dabbe2a85a..20410865672 100644 --- a/drivers/power/regulator/regulator_common.c +++ b/drivers/power/regulator/regulator_common.c @@ -12,10 +12,15 @@ int regulator_common_ofdata_to_platdata(struct udevice *dev, struct regulator_common_platdata *dev_pdata, const char *enable_gpio_name) { struct gpio_desc *gpio; + struct dm_regulator_uclass_platdata *uc_pdata; int flags = GPIOD_IS_OUT; int ret; - if (dev_read_bool(dev, "enable-active-high")) + uc_pdata = dev_get_uclass_platdata(dev); + + if (!dev_read_bool(dev, "enable-active-high")) + flags |= GPIOD_ACTIVE_LOW; + if (uc_pdata->boot_on) flags |= GPIOD_IS_OUT_ACTIVE; /* Get optional enable GPIO desc */ From 9243990b17558c6498208061842b2ff4056acde0 Mon Sep 17 00:00:00 2001 From: Mans Rullgard Date: Tue, 3 Sep 2019 16:17:17 +0200 Subject: [PATCH 21/31] spl: mmc: Fix indentation in spl_mmc.c file This fixes a wrongly indented block of code. Signed-off-by: Mans Rullgard [lukma: Make the commit message more verbose] Signed-off-by: Lukasz Majewski --- common/spl/spl_mmc.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index ebc566081ad..fa19aa76b3e 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -355,28 +355,28 @@ int spl_mmc_load(struct spl_image_info *spl_image, err = -EINVAL; switch (boot_mode) { case MMCSD_MODE_EMMCBOOT: - /* - * We need to check what the partition is configured to. - * 1 and 2 match up to boot0 / boot1 and 7 is user data - * which is the first physical partition (0). - */ - part = (mmc->part_config >> 3) & PART_ACCESS_MASK; + /* + * We need to check what the partition is configured to. + * 1 and 2 match up to boot0 / boot1 and 7 is user data + * which is the first physical partition (0). + */ + part = (mmc->part_config >> 3) & PART_ACCESS_MASK; - if (part == 7) - part = 0; + if (part == 7) + part = 0; - if (CONFIG_IS_ENABLED(MMC_TINY)) - err = mmc_switch_part(mmc, part); - else - err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part); + if (CONFIG_IS_ENABLED(MMC_TINY)) + err = mmc_switch_part(mmc, part); + else + err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part); - if (err) { + if (err) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - puts("spl: mmc partition switch failed\n"); + puts("spl: mmc partition switch failed\n"); #endif - return err; - } - /* Fall through */ + return err; + } + /* Fall through */ case MMCSD_MODE_RAW: debug("spl: mmc boot mode: raw\n"); From 17241ea0543a4c998f79bde27b8a6047c8d84d0a Mon Sep 17 00:00:00 2001 From: Mans Rullgard Date: Tue, 3 Sep 2019 16:16:50 +0200 Subject: [PATCH 22/31] spl: mmc: Add option to set eMMC HW boot partition This change allows setting pre-defined eMMC boot partition for SPL eMMC booting. It is necessary in the case when one wants to boot (through falcon boot) from eMMC after loading SPL from other memory (like SPI-NOR). Signed-off-by: Mans Rullgard [lukma: Edit the commit message] Signed-off-by: Lukasz Majewski Acked-by: Andreas Dannenberg --- common/spl/Kconfig | 6 ++++++ common/spl/spl_mmc.c | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 282d246ea38..7862a0128c7 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -325,6 +325,12 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR Address on the MMC to load U-Boot from, when the MMC is being used in raw mode. Units: MMC sectors (1 sector = 512 bytes). +config SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION + int "Number of the eMMC boot partition to use" + default 1 + help + eMMC boot partition number to use when the eMMC in raw mode. + config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION bool "MMC Raw mode: by partition" help diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index fa19aa76b3e..c5cae970991 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -355,6 +355,9 @@ int spl_mmc_load(struct spl_image_info *spl_image, err = -EINVAL; switch (boot_mode) { case MMCSD_MODE_EMMCBOOT: +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION + part = CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION; +#else /* * We need to check what the partition is configured to. * 1 and 2 match up to boot0 / boot1 and 7 is user data @@ -364,6 +367,7 @@ int spl_mmc_load(struct spl_image_info *spl_image, if (part == 7) part = 0; +#endif if (CONFIG_IS_ENABLED(MMC_TINY)) err = mmc_switch_part(mmc, part); From 909d0399a519e1491b3e11e6afae2287e0c08a3f Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 10 Sep 2019 08:51:53 +0000 Subject: [PATCH 23/31] ARM: asm/io.h: kill off confusing #ifdef __mem_pci block No ARM board seems to define __mem_pci - and if it did, one would get tons of ./arch/arm/include/asm/io.h:307:0: warning: "readl" redefined warnings, because readl and friends are unconditionally defined earlier in io.h. Moreover, the redefinitions lack the memory barriers that the first definitions have. So I'm guessing this is practically dead code. Signed-off-by: Rasmus Villemoes --- arch/arm/include/asm/io.h | 41 --------------------------------------- 1 file changed, 41 deletions(-) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index e6d27b69f93..78b183d42f6 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -315,46 +315,6 @@ extern void _memset_io(unsigned long, int, size_t); extern void __readwrite_bug(const char *fn); -/* - * If this architecture has PCI memory IO, then define the read/write - * macros. These should only be used with the cookie passed from - * ioremap. - */ -#ifdef __mem_pci - -#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) - -#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) -#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) -#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) - -#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) -#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) -#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) - -#define eth_io_copy_and_sum(s,c,l,b) \ - eth_copy_and_sum((s),__mem_pci(c),(l),(b)) - -static inline int -check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#else #define memset_io(a, b, c) memset((void *)(a), (b), (c)) #define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) #define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) @@ -373,7 +333,6 @@ out: #define check_signature(io,sig,len) (0) #endif -#endif /* __mem_pci */ /* * If this architecture has ISA IO, then define the isa_read/isa_write From 26c106095188ef29c252c189fbf5261c59b88a10 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 10 Sep 2019 08:51:54 +0000 Subject: [PATCH 24/31] ARM: asm/io.h: remove redundant #if !defined(readb) block readb is unconditionally defined earlier in io.h, so there's no point checking whether it's undefined. Signed-off-by: Rasmus Villemoes --- arch/arm/include/asm/io.h | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 78b183d42f6..723f3cf497d 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -319,21 +319,6 @@ extern void __readwrite_bug(const char *fn); #define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) #define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) -#if !defined(readb) - -#define readb(addr) (__readwrite_bug("readb"),0) -#define readw(addr) (__readwrite_bug("readw"),0) -#define readl(addr) (__readwrite_bug("readl"),0) -#define writeb(v,addr) __readwrite_bug("writeb") -#define writew(v,addr) __readwrite_bug("writew") -#define writel(v,addr) __readwrite_bug("writel") - -#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") - -#define check_signature(io,sig,len) (0) - -#endif - /* * If this architecture has ISA IO, then define the isa_read/isa_write * macros. From 100e75bbdbe3e2c02f004f7d26055ce57e6472eb Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Wed, 11 Sep 2019 15:39:53 +0200 Subject: [PATCH 25/31] cmd: avoid decimal conversion This patch uses auto instead of decimal in simple_strtoul(). Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- cmd/test.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/cmd/test.c b/cmd/test.c index fa0c349f082..258bfd88065 100644 --- a/cmd/test.c +++ b/cmd/test.c @@ -113,28 +113,28 @@ static int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) expr = strcmp(ap[0], ap[2]) > 0; break; case OP_INT_EQ: - expr = simple_strtol(ap[0], NULL, 10) == - simple_strtol(ap[2], NULL, 10); + expr = simple_strtol(ap[0], NULL, 0) == + simple_strtol(ap[2], NULL, 0); break; case OP_INT_NEQ: - expr = simple_strtol(ap[0], NULL, 10) != - simple_strtol(ap[2], NULL, 10); + expr = simple_strtol(ap[0], NULL, 0) != + simple_strtol(ap[2], NULL, 0); break; case OP_INT_LT: - expr = simple_strtol(ap[0], NULL, 10) < - simple_strtol(ap[2], NULL, 10); + expr = simple_strtol(ap[0], NULL, 0) < + simple_strtol(ap[2], NULL, 0); break; case OP_INT_LE: - expr = simple_strtol(ap[0], NULL, 10) <= - simple_strtol(ap[2], NULL, 10); + expr = simple_strtol(ap[0], NULL, 0) <= + simple_strtol(ap[2], NULL, 0); break; case OP_INT_GT: - expr = simple_strtol(ap[0], NULL, 10) > - simple_strtol(ap[2], NULL, 10); + expr = simple_strtol(ap[0], NULL, 0) > + simple_strtol(ap[2], NULL, 0); break; case OP_INT_GE: - expr = simple_strtol(ap[0], NULL, 10) >= - simple_strtol(ap[2], NULL, 10); + expr = simple_strtol(ap[0], NULL, 0) >= + simple_strtol(ap[2], NULL, 0); break; case OP_FILE_EXISTS: expr = file_exists(ap[1], ap[2], ap[3], FS_TYPE_ANY); From 57bbf44de6db8408e2b368475ca33dab3bab638a Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 12 Sep 2019 19:09:26 +0200 Subject: [PATCH 26/31] arm64: print instructions leading to exception If an exception occurs in a loaded image and the relocation offset is unknown, it is helpful to know the instructions pointed to by the program counter. This patch adds the missing output. A possible output is: Code: 910c4021 aa1303e0 f9400662 d63f0040 (e7f7defb) The parentheses indicate the instruction causing the exception. The output can be disassembled using scripts/decodecode: echo 'Code: 90000360 9100b800 94002782 17ffff8f (e7f7defb)' | \ ARCH=arm64 scripts/decodecode Code: 90000360 9100b800 94002782 17ffff8f (e7f7defb) All code ======== 0: 90000360 adrp x0, 0x6c000 4: 9100b800 add x0, x0, #0x2e 8: 94002782 bl 0x9e10 c: 17ffff8f b 0xfffffffffffffe48 10:* e7f7defb .inst 0xe7f7defb ; undefined <-- trapping instruction Code starting with the faulting instruction =========================================== 0: e7f7defb .inst 0xe7f7defb ; undefined We already have implemented the same for armv7. For testing command 'exception undefined' can be used. Signed-off-by: Heinrich Schuchardt --- arch/arm/lib/interrupts_64.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c index 0bfdb8d93d2..a32a4b68684 100644 --- a/arch/arm/lib/interrupts_64.c +++ b/arch/arm/lib/interrupts_64.c @@ -30,6 +30,17 @@ static void show_efi_loaded_images(struct pt_regs *regs) efi_print_image_infos((void *)regs->elr); } +static void dump_instr(struct pt_regs *regs) +{ + u32 *addr = (u32 *)(regs->elr & ~3UL); + int i; + + printf("Code: "); + for (i = -4; i < 1; i++) + printf(i == 0 ? "(%08x) " : "%08x ", addr[i]); + printf("\n"); +} + void show_regs(struct pt_regs *regs) { int i; @@ -44,6 +55,7 @@ void show_regs(struct pt_regs *regs) printf("x%-2d: %016lx x%-2d: %016lx\n", i, regs->regs[i], i+1, regs->regs[i+1]); printf("\n"); + dump_instr(regs); } /* From f18845c27ad86e118b074ce545ce685cb9a97561 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Mon, 9 Sep 2019 12:06:46 +0200 Subject: [PATCH 27/31] spl: Introduce SPL_DM_SPI Kconfig define This define indicates if DM_SPI shall be supported in SPL. This allows proper operation of DM converted SPI drivers in SPL, which use #if !CONFIG_IS_ENABLED(DM_SPI) to also support not yet DM/DTS converted boards. Signed-off-by: Lukasz Majewski --- common/spl/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 7862a0128c7..562eafe2e5b 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -697,6 +697,13 @@ config SPL_UBI Enable support for loading payloads from UBI. See README.ubispl for more info. +if SPL_DM +config SPL_DM_SPI + bool "Support SPI DM drivers in SPL" + help + Enable support for SPI DM drivers in SPL. + +endif if SPL_UBI config SPL_UBI_LOAD_BY_VOLNAME bool "Support loading volumes by name" From ee8da596eba60dcf55dcb30b5288336c53919c99 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 11 Oct 2019 16:28:47 -0400 Subject: [PATCH 28/31] sandbox: Remove sandbox_noblk build At this point, all drivers that do not use CONFIG_BLK are past their migration deadlines, so remove this config as it's no longer helpful and hinders enhancing block drivers. Reviewed-by: Simon Glass Signed-off-by: Tom Rini --- board/sandbox/MAINTAINERS | 7 -- configs/sandbox_noblk_defconfig | 178 -------------------------------- doc/arch/sandbox.rst | 7 +- 3 files changed, 1 insertion(+), 191 deletions(-) delete mode 100644 configs/sandbox_noblk_defconfig diff --git a/board/sandbox/MAINTAINERS b/board/sandbox/MAINTAINERS index df29abe7aa7..433be48a6f1 100644 --- a/board/sandbox/MAINTAINERS +++ b/board/sandbox/MAINTAINERS @@ -13,13 +13,6 @@ F: board/sandbox/ F: include/configs/sandbox.h F: configs/sandbox64_defconfig -SANDBOX_NOBLK BOARD -M: Simon Glass -S: Maintained -F: board/sandbox/ -F: include/configs/sandbox.h -F: configs/sandbox_noblk_defconfig - SANDBOX SPL BOARD M: Simon Glass S: Maintained diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig deleted file mode 100644 index 381bad2003e..00000000000 --- a/configs/sandbox_noblk_defconfig +++ /dev/null @@ -1,178 +0,0 @@ -CONFIG_SYS_TEXT_BASE=0 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_BOOTSTAGE_STASH_ADDR=0x0 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_BOOTSTAGE=y -CONFIG_BOOTSTAGE_REPORT=y -CONFIG_BOOTSTAGE_FDT=y -CONFIG_BOOTSTAGE_STASH=y -CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_CONSOLE_RECORD=y -CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 -CONFIG_SILENT_CONSOLE=y -CONFIG_DISPLAY_BOARDINFO_LATE=y -# CONFIG_AVB_VERIFY is not set -CONFIG_CMD_CPU=y -CONFIG_CMD_LICENSE=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_ELF is not set -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_ENV_CALLBACK=y -CONFIG_CMD_ENV_FLAGS=y -CONFIG_LOOPW=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_MX_CYCLIC=y -CONFIG_CMD_DEMO=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_IDE=y -CONFIG_CMD_I2C=y -CONFIG_CMD_OSD=y -CONFIG_CMD_PCI=y -CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TFTPSRV=y -CONFIG_CMD_RARP=y -CONFIG_CMD_CDP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DNS=y -CONFIG_CMD_LINK_LOCAL=y -CONFIG_CMD_BMP=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_SOUND=y -CONFIG_CMD_BOOTSTAGE=y -CONFIG_CMD_PMIC=y -CONFIG_CMD_REGULATOR=y -CONFIG_CMD_TPM=y -CONFIG_CMD_TPM_TEST=y -CONFIG_CMD_CBFS=y -CONFIG_CMD_CRAMFS=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_MAC_PARTITION=y -CONFIG_AMIGA_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_OF_HOSTFILE=y -CONFIG_DEFAULT_DEVICE_TREE="sandbox" -CONFIG_NETCONSOLE=y -CONFIG_IP_DEFRAG=y -CONFIG_REGMAP=y -CONFIG_SYSCON=y -CONFIG_DEVRES=y -CONFIG_DEBUG_DEVRES=y -CONFIG_ADC=y -CONFIG_ADC_SANDBOX=y -# CONFIG_BLK is not set -CONFIG_CLK=y -CONFIG_CPU=y -CONFIG_DM_DEMO=y -CONFIG_DM_DEMO_SIMPLE=y -CONFIG_DM_DEMO_SHAPE=y -CONFIG_BOARD=y -CONFIG_BOARD_SANDBOX=y -CONFIG_PM8916_GPIO=y -CONFIG_SANDBOX_GPIO=y -CONFIG_I2C_CROS_EC_TUNNEL=y -CONFIG_I2C_CROS_EC_LDO=y -CONFIG_DM_I2C_GPIO=y -CONFIG_SYS_I2C_SANDBOX=y -CONFIG_I2C_MUX=y -CONFIG_SPL_I2C_MUX=y -CONFIG_I2C_ARB_GPIO_CHALLENGE=y -CONFIG_CROS_EC_KEYB=y -CONFIG_I8042_KEYB=y -CONFIG_LED=y -CONFIG_LED_BLINK=y -CONFIG_LED_GPIO=y -CONFIG_CROS_EC=y -CONFIG_CROS_EC_I2C=y -CONFIG_CROS_EC_LPC=y -CONFIG_CROS_EC_SANDBOX=y -CONFIG_CROS_EC_SPI=y -CONFIG_PWRSEQ=y -CONFIG_SPL_PWRSEQ=y -# CONFIG_MMC is not set -CONFIG_SPI_FLASH_SANDBOX=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DM_ETH=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCI_SANDBOX=y -CONFIG_PHY=y -CONFIG_PHY_SANDBOX=y -CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_SANDBOX=y -CONFIG_DM_PMIC=y -CONFIG_PMIC_ACT8846=y -CONFIG_DM_PMIC_PFUZE100=y -CONFIG_DM_PMIC_MAX77686=y -CONFIG_PMIC_PM8916=y -CONFIG_PMIC_RK8XX=y -CONFIG_PMIC_S2MPS11=y -CONFIG_DM_PMIC_SANDBOX=y -CONFIG_PMIC_S5M8767=y -CONFIG_PMIC_TPS65090=y -CONFIG_DM_REGULATOR=y -CONFIG_REGULATOR_ACT8846=y -CONFIG_DM_REGULATOR_PFUZE100=y -CONFIG_DM_REGULATOR_MAX77686=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_REGULATOR_RK8XX=y -CONFIG_REGULATOR_S5M8767=y -CONFIG_DM_REGULATOR_SANDBOX=y -CONFIG_REGULATOR_TPS65090=y -CONFIG_DM_PWM=y -CONFIG_PWM_SANDBOX=y -CONFIG_RAM=y -CONFIG_REMOTEPROC_SANDBOX=y -CONFIG_DM_RTC=y -CONFIG_SANDBOX_SERIAL=y -CONFIG_SOUND=y -CONFIG_SOUND_SANDBOX=y -CONFIG_SANDBOX_SPI=y -CONFIG_SPMI=y -CONFIG_SPMI_SANDBOX=y -CONFIG_SYSRESET=y -CONFIG_TIMER=y -CONFIG_TIMER_EARLY=y -CONFIG_SANDBOX_TIMER=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_EMUL=y -CONFIG_USB_KEYBOARD=y -CONFIG_DM_VIDEO=y -CONFIG_CONSOLE_ROTATION=y -CONFIG_CONSOLE_TRUETYPE=y -CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y -CONFIG_VIDEO_SANDBOX_SDL=y -CONFIG_OSD=y -CONFIG_SANDBOX_OSD=y -# CONFIG_VIRTIO_BLK is not set -CONFIG_FS_CBFS=y -CONFIG_FS_CRAMFS=y -CONFIG_CMD_DHRYSTONE=y -CONFIG_TPM=y -CONFIG_LZ4=y -CONFIG_ERRNO_STR=y -CONFIG_UNIT_TEST=y -CONFIG_UT_TIME=y -CONFIG_UT_DM=y diff --git a/doc/arch/sandbox.rst b/doc/arch/sandbox.rst index 54933b56759..e1f4dde6f86 100644 --- a/doc/arch/sandbox.rst +++ b/doc/arch/sandbox.rst @@ -209,17 +209,12 @@ sandbox_flattree: We need this build so that we can test those inline functions, and we cannot build with both the inline functions and the non-inline functions since they are named the same. -sandbox_noblk: - builds without CONFIG_BLK, which means the legacy block - drivers are used. We cannot use both the legacy and driver-model block - drivers since they implement the same functions sandbox_spl: builds sandbox with SPL support, so you can run spl/u-boot-spl and it will start up and then load ./u-boot. It is also possible to run ./u-boot directly. -Of these sandbox_noblk can be removed once CONFIG_BLK is used everwhere, and -sandbox_spl can probably be removed since it is a superset of sandbox. +Of these sandbox_spl can probably be removed since it is a superset of sandbox. Most of the config options should be identical between these variants. From c7a86d1645325697372b404f0b8cadac8a722ce9 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 12 Sep 2019 19:19:29 +0200 Subject: [PATCH 29/31] fs: fat: treat invalid FAT clusters as errors When hitting an invalid FAT cluster while reading a file always print an error message and return an error code. Signed-off-by: Heinrich Schuchardt --- fs/fat/fat.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 29cae8d3914..2a5300d5019 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -301,10 +301,20 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) return 0; } -/* +/** + * get_contents() - read from file + * * Read at most 'maxsize' bytes from 'pos' in the file associated with 'dentptr' - * into 'buffer'. - * Update the number of bytes read in *gotsize or return -1 on fatal errors. + * into 'buffer'. Update the number of bytes read in *gotsize or return -1 on + * fatal errors. + * + * @mydata: file system description + * @dentprt: directory entry pointer + * @pos: position from where to read + * @buffer: buffer into which to read + * @maxsize: maximum number of bytes to read + * @gotsize: number of bytes actually read + * Return: -1 on error, otherwise 0 */ static int get_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos, __u8 *buffer, loff_t maxsize, loff_t *gotsize) @@ -335,8 +345,8 @@ static int get_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos, curclust = get_fatent(mydata, curclust); if (CHECK_CLUST(curclust, mydata->fatsize)) { debug("curclust: 0x%x\n", curclust); - debug("Invalid FAT entry\n"); - return 0; + printf("Invalid FAT entry\n"); + return -1; } actsize += bytesperclust; } @@ -374,8 +384,8 @@ static int get_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos, curclust = get_fatent(mydata, curclust); if (CHECK_CLUST(curclust, mydata->fatsize)) { debug("curclust: 0x%x\n", curclust); - debug("Invalid FAT entry\n"); - return 0; + printf("Invalid FAT entry\n"); + return -1; } } @@ -390,8 +400,8 @@ static int get_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos, goto getit; if (CHECK_CLUST(newclust, mydata->fatsize)) { debug("curclust: 0x%x\n", newclust); - debug("Invalid FAT entry\n"); - return 0; + printf("Invalid FAT entry\n"); + return -1; } endclust = newclust; actsize += bytesperclust; @@ -418,7 +428,7 @@ getit: if (CHECK_CLUST(curclust, mydata->fatsize)) { debug("curclust: 0x%x\n", curclust); printf("Invalid FAT entry\n"); - return 0; + return -1; } actsize = bytesperclust; endclust = curclust; From f13683816b9d0aada2546343d77bb87925505c46 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 12 Sep 2019 19:19:30 +0200 Subject: [PATCH 30/31] fs: fat: get_contents() always returns -1 for errors If out of memory, return -1 and not -ENOMEM from get_contents(). Signed-off-by: Heinrich Schuchardt --- fs/fat/fat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 2a5300d5019..9e1b842dac6 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -364,7 +364,7 @@ static int get_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos, tmp_buffer = malloc_cache_aligned(actsize); if (!tmp_buffer) { debug("Error: allocating buffer\n"); - return -ENOMEM; + return -1; } if (get_cluster(mydata, curclust, tmp_buffer, actsize) != 0) { From 7d2dc6af540fad77bff2a3ff16cdc2f9d9df72eb Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 2 Oct 2019 12:24:46 +0200 Subject: [PATCH 31/31] cmd: itest: add support for .q size specifier Add support for quad (64bits) memory access specifier. Signed-off-by: Marek Szyprowski Acked-by: Lukasz Majewski --- cmd/itest.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/cmd/itest.c b/cmd/itest.c index 8b630d71e62..e21e1f1b1bf 100644 --- a/cmd/itest.c +++ b/cmd/itest.c @@ -73,6 +73,11 @@ static long evalexp(char *s, int w) case 4: l = (long)(*(u32 *)buf); break; +#ifdef CONFIG_PHYS_64BIT + case 8: + l = (long)(*(unsigned long *)buf); + break; +#endif } unmap_physmem(buf, w); return l; @@ -186,6 +191,9 @@ static int do_itest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) case 1: case 2: case 4: +#ifdef CONFIG_PHYS_64BIT + case 8: +#endif value = binary_test (argv[2], argv[1], argv[3], w); break; case -2: @@ -204,5 +212,9 @@ static int do_itest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( itest, 4, 0, do_itest, "return true/false on integer compare", +#ifdef CONFIG_PHYS_64BIT + "[.b, .w, .l, .q, .s] [*]value1 [*]value2" +#else "[.b, .w, .l, .s] [*]value1 [*]value2" +#endif );