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ddr: altera: Clean up of delay_for_n_mem_clocks() part 4

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Simplify the loop code, optimizing compiler can deal with this.
No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut
2015-07-26 11:44:54 +02:00
parent 6a39be6ca9
commit 0c1b81bdf3
1 changed files with 5 additions and 12 deletions
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17
drivers/ddr/altera/sequencer.c
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@@ -822,18 +822,11 @@ static void delay_for_n_mem_clocks(const u32 clocks)
writel(RW_MGR_IDLE_LOOP2, writel(RW_MGR_IDLE_LOOP2,
&sdr_rw_load_jump_mgr_regs->load_jump_add1); &sdr_rw_load_jump_mgr_regs->load_jump_add1);
/* hack to get around compiler not being smart enough */ do {
if (afi_clocks <= 0x10000) { writel(RW_MGR_IDLE_LOOP2,
/* only need to run once */ SDR_PHYGRP_RWMGRGRP_ADDRESS |
writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET);
RW_MGR_RUN_SINGLE_GROUP_OFFSET); } while (c_loop-- != 0);
} else {
do {
writel(RW_MGR_IDLE_LOOP2,
SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} while (c_loop-- != 0);
}
} }
debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks); debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
} }