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imx: imx6sx-sabreauto: convert to use DM QSPI driver

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To support DM QSPI driver:
 - Add -u-boot.dtsi to modify n25q256a@0 and n25q256a@1 compatible string
   to "spi-flash" and add "num-cs" property.
 - Enable DM SPI and DM SPI FLASH configurations
 - Remove iomux settings of qspi1 in board codes which is not needed
   for DM driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
This commit is contained in:
Ye Li
2018-06-27 19:27:00 -07:00
committed by Stefano Babic
parent 536c5c7a33
commit 0925ee2185
4 changed files with 58 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi Normal file
View File

@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
&qspi1 {
num-cs = <2>;
flash0: n25q256a@0 {
compatible = "spi-flash";
};
flash1: n25q256a@1 {
compatible = "spi-flash";
};
};

40
arch/arm/dts/imx6sx-sabreauto.dts
View File

@@ -96,6 +96,29 @@
}; };
}; };
&qspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_1>;
status = "okay";
ddrsmp=<2>;
flash0: n25q256a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a";
spi-max-frequency = <29000000>;
reg = <0>;
};
flash1: n25q256a@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a";
spi-max-frequency = <29000000>;
reg = <1>;
};
};
&iomuxc { &iomuxc {
imx6x-sabreauto { imx6x-sabreauto {
pinctrl_i2c2_1: i2c2grp-1 { pinctrl_i2c2_1: i2c2grp-1 {
@@ -112,6 +135,23 @@
>; >;
}; };
pinctrl_qspi1_1: qspi1grp_1 {
fsl,pins = <
MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1
MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1
MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1
MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1
MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1
MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1
MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1
MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1
MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1
MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1
MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1
MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1
>;
};
pinctrl_uart1: uart1grp { pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1

24
board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
View File

@@ -218,32 +218,8 @@ int board_early_init_f(void)
} }
#ifdef CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI
#define QSPI_PAD_CTRL1 \
(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
static iomux_v3_cfg_t const quadspi_pads[] = {
MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
};
int board_qspi_init(void) int board_qspi_init(void)
{ {
/* Set the iomux */
imx_iomux_v3_setup_multiple_pads(quadspi_pads,
ARRAY_SIZE(quadspi_pads));
/* Set the clock */ /* Set the clock */
enable_qspi_clk(0); enable_qspi_clk(0);

2
configs/mx6sxsabreauto_defconfig
View File

@@ -36,6 +36,8 @@ CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y CONFIG_FSL_ESDHC=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_MXS=y CONFIG_NAND_MXS=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_STMICRO=y