From 3b441cf4e403f5ac1c56b048be5cda1caf5ce6db Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Fri, 29 Oct 2021 13:11:43 +0200 Subject: [PATCH 01/36] zynqmp: gpio: Add support for zynqmp gpio modepin driver ZynqMP modepin driver has capability to get/set/check status of modepin gpios. These modepins are accessed using xilinx firmware. In modepin register, [3:0] bits set direction, [7:4] bits read IO, [11:8] bits set/clear IO. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/2d802d98fd56d95d764532a33e844d935e0cebb3.1635505900.git.michal.simek@xilinx.com --- MAINTAINERS | 1 + arch/arm/Kconfig | 1 + drivers/gpio/Kconfig | 9 ++ drivers/gpio/Makefile | 1 + drivers/gpio/zynqmp_gpio_modepin.c | 153 +++++++++++++++++++++++++++++ 5 files changed, 165 insertions(+) create mode 100644 drivers/gpio/zynqmp_gpio_modepin.c diff --git a/MAINTAINERS b/MAINTAINERS index e718ad2135..b3b5c1c170 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -602,6 +602,7 @@ F: drivers/clk/clk_zynqmp.c F: driver/firmware/firmware-zynqmp.c F: drivers/fpga/zynqpl.c F: drivers/gpio/zynq_gpio.c +F: drivers/gpio/zynqmp_gpio_modepin.c F: drivers/i2c/i2c-cdns.c F: drivers/i2c/muxes/pca954x.c F: drivers/i2c/zynq_i2c.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f7f03837fe..23d57ca10c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1214,6 +1214,7 @@ config ARCH_ZYNQMP imply FAT_WRITE imply MP imply DM_USB_GADGET + imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB config ARCH_TEGRA bool "NVIDIA Tegra" diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 40abc33772..8192ce5f67 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -523,4 +523,13 @@ config NOMADIK_GPIO into a number of banks each with 32 GPIOs. The GPIOs for a device are defined in the device tree with one node for each bank. +config ZYNQMP_GPIO_MODEPIN + bool "ZynqMP gpio modepin" + depends on DM_GPIO + help + This config enables the ZynqMP gpio modepin driver. ZynqMP modepin + driver will set and get the status of PS_MODE pins. These modepins + are accessed using xilinx firmware. In modepin register, [3:0] bits + set direction, [7:4] bits read IO, [11:8] bits set/clear IO. + endif diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 3c851b38c7..3eb77f58c1 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -69,3 +69,4 @@ obj-$(CONFIG_NX_GPIO) += nx_gpio.o obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o +obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o diff --git a/drivers/gpio/zynqmp_gpio_modepin.c b/drivers/gpio/zynqmp_gpio_modepin.c new file mode 100644 index 0000000000..078fd83395 --- /dev/null +++ b/drivers/gpio/zynqmp_gpio_modepin.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ZynqMP GPIO modepin driver + * + * Copyright (C) 2021 Xilinx, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define OUTEN(pin) (BIT(0) << (pin)) +#define INVAL(pin) (BIT(4) << (pin)) +#define OUTVAL(pin) (BIT(8) << (pin)) + +#define ZYNQMP_CRL_APB_BOOTPIN_CTRL_MASK 0xF0F +#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL (ZYNQMP_CRL_APB_BASEADDR + \ + (0x250U)) + +static int get_gpio_modepin(u32 *ret_payload) +{ + return xilinx_pm_request(PM_MMIO_READ, ZYNQMP_CRL_APB_BOOT_PIN_CTRL, + 0, 0, 0, ret_payload); +} + +static int set_gpio_modepin(int val) +{ + return xilinx_pm_request(PM_MMIO_WRITE, ZYNQMP_CRL_APB_BOOT_PIN_CTRL, + ZYNQMP_CRL_APB_BOOTPIN_CTRL_MASK, + val, 0, NULL); +} + +static int modepin_gpio_direction_input(struct udevice *dev, + unsigned int offset) +{ + return 0; +} + +static int modepin_gpio_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + u32 out_val = 0; + int ret; + + ret = get_gpio_modepin(ret_payload); + if (value) + out_val = OUTVAL(offset) | ret_payload[1]; + else + out_val = ~OUTVAL(offset) & ret_payload[1]; + + return set_gpio_modepin(out_val); +} + +static int modepin_gpio_direction_output(struct udevice *dev, + unsigned int offset, int value) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + u32 out_en = 0; + int ret; + + ret = get_gpio_modepin(ret_payload); + if (ret) + return ret; + + if (value) + out_en = OUTEN(offset) | ret_payload[1]; + else + out_en = ~OUTEN(offset) & ret_payload[1]; + + ret = set_gpio_modepin(out_en); + if (ret) + return ret; + + return modepin_gpio_set_value(dev, offset, value); +} + +static int modepin_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct ofnode_phandle_args *args) +{ + desc->offset = args->args[0]; + + return 0; +} + +static int modepin_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + ret = get_gpio_modepin(ret_payload); + if (ret) + return ret; + + return (INVAL(offset) & ret_payload[1]) ? 1 : 0; +} + +static int modepin_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + ret = get_gpio_modepin(ret_payload); + if (ret) + return ret; + + return (OUTEN(offset) & ret_payload[1]) ? GPIOF_OUTPUT : GPIOF_INPUT; +} + +static const struct dm_gpio_ops modepin_gpio_ops = { + .direction_input = modepin_gpio_direction_input, + .direction_output = modepin_gpio_direction_output, + .get_value = modepin_gpio_get_value, + .set_value = modepin_gpio_set_value, + .get_function = modepin_gpio_get_function, + .xlate = modepin_gpio_xlate, +}; + +static int modepin_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + const void *label_ptr; + + label_ptr = dev_read_prop(dev, "label", NULL); + if (label_ptr) { + uc_priv->bank_name = strdup(label_ptr); + if (!uc_priv->bank_name) + return -ENOMEM; + } else { + uc_priv->bank_name = dev->name; + } + + uc_priv->gpio_count = 4; + + return 0; +} + +static const struct udevice_id modepin_gpio_ids[] = { + { .compatible = "xlnx,zynqmp-gpio-modepin",}, + { } +}; + +U_BOOT_DRIVER(modepin_gpio) = { + .name = "modepin_gpio", + .id = UCLASS_GPIO, + .ops = &modepin_gpio_ops, + .of_match = modepin_gpio_ids, + .probe = modepin_gpio_probe, +}; From e959ade02c58c17ebbd65733e63bc154c0ed732d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 29 Oct 2021 13:13:37 +0200 Subject: [PATCH 02/36] clk: zynqmp: Add support for setting up clock for USB USB range is not enabled but for setting up frequency it is needed. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c55c423f48ca8f953a2dfbdcb25068278d8e5ad6.1635506016.git.michal.simek@xilinx.com --- drivers/clk/clk_zynqmp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 52fecec7a7..ca36df6640 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -699,6 +699,7 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate) switch (id) { case gem0_ref ... gem3_ref: case qspi_ref ... can1_ref: + case usb0_bus_ref ... usb3_dual_ref: return zynqmp_clk_set_peripheral_rate(priv, id, rate, two_divs); default: From 0e789d26b73febdf6562017a004aceadfe737e8a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 29 Oct 2021 13:13:38 +0200 Subject: [PATCH 03/36] clk: zynqmp: Fix gem tx/rx/ref clock handling gemX_ref clock IDs starts at number 104. Till now it was at gemX_tx location which wasn't correct. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d073e159b6316707306092a62bccb876cd89a602.1635506016.git.michal.simek@xilinx.com --- drivers/clk/clk_zynqmp.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index ca36df6640..9038fb8bef 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -130,8 +130,8 @@ enum zynqmp_clk { csu_spb, csu_pll, pcap, iou_switch, gem_tsu_ref, gem_tsu, - gem0_ref, gem1_ref, gem2_ref, gem3_ref, gem0_tx, gem1_tx, gem2_tx, gem3_tx, + gem0_rx, gem1_rx, gem2_rx, gem3_rx, qspi_ref, sdio0_ref, sdio1_ref, uart0_ref, uart1_ref, @@ -144,6 +144,8 @@ enum zynqmp_clk { ams_ref, pl0, pl1, pl2, pl3, wdt, + gem0_ref = 104, + gem1_ref, gem2_ref, gem3_ref, clk_max, }; @@ -161,14 +163,18 @@ static const char * const clk_names[clk_max] = { "usb1_bus_ref", "usb3_dual_ref", "usb0", "usb1", "cpu_r5", "cpu_r5_core", "csu_spb", "csu_pll", "pcap", "iou_switch", "gem_tsu_ref", - "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref", - "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx", - "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref", + "gem_tsu", "gem0_tx", "gem1_tx", "gem2_tx", + "gem3_tx", "gem0_rx", "gem1_rx", "gem2_rx", + "gem3_rx", "qspi_ref", "sdio0_ref", "sdio1_ref", "uart0_ref", "uart1_ref", "spi0_ref", "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref", "can0_ref", "can1_ref", "can0", "can1", "dll_ref", "adma_ref", "timestamp_ref", - "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt" + "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt", + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, "gem0_ref", "gem1_ref", "gem2_ref", "gem3_ref", }; static const u32 pll_src[][4] = { @@ -258,12 +264,16 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id) return CRL_APB_USB3_DUAL_REF_CTRL; case gem_tsu_ref: return CRL_APB_GEM_TSU_REF_CTRL; + case gem0_tx: case gem0_ref: return CRL_APB_GEM0_REF_CTRL; + case gem1_tx: case gem1_ref: return CRL_APB_GEM1_REF_CTRL; + case gem2_tx: case gem2_ref: return CRL_APB_GEM2_REF_CTRL; + case gem3_tx: case gem3_ref: return CRL_APB_GEM3_REF_CTRL; case usb0_bus_ref: @@ -665,6 +675,7 @@ static ulong zynqmp_clk_get_rate(struct clk *clk) case gem_tsu_ref: case pl0 ... pl3: case gem0_ref ... gem3_ref: + case gem0_tx ... gem3_tx: case qspi_ref ... can1_ref: case usb0_bus_ref ... usb3_dual_ref: two_divs = true; @@ -698,6 +709,7 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate) switch (id) { case gem0_ref ... gem3_ref: + case gem0_tx ... gem3_tx: case qspi_ref ... can1_ref: case usb0_bus_ref ... usb3_dual_ref: return zynqmp_clk_set_peripheral_rate(priv, id, @@ -809,6 +821,7 @@ static int zynqmp_clk_enable(struct clk *clk) clkact_shift = 25; mask = 0x1; break; + case gem0_tx ... gem3_tx: case gem0_ref ... gem3_ref: clkact_shift = 25; mask = 0x3; From 19645a11debf54c66e4a782a1fdf04752dfaec60 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 18 Nov 2021 13:40:31 +0100 Subject: [PATCH 04/36] arm64: zynqmp: Add u-boot,dm-pre-reloc to dpsub node u-boot,dm-pre-reloc is necessary for DP driver to allocate enough space for framebuffer before relocation. Power domain driver is called when video console is used for example by loading BMP image. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5e93acee1746913a6e42741e5e797f0b4ab98d44.1637239230.git.michal.simek@xilinx.com --- arch/arm/dts/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 1332f5373f..07d4d4b912 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -961,6 +961,7 @@ }; zynqmp_dpsub: display@fd4a0000 { + u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, From 87b50f9aeaed91ebdcbb1375ea6523821e8b4510 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 18 Nov 2021 13:42:27 +0100 Subject: [PATCH 05/36] arm64: zynqmp: Add resets to all GEMs There is a need to get IP out of reset to operate properly. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/041362197e8de8e9c696da64429107505bdc0c73.1637239345.git.michal.simek@xilinx.com --- arch/arm/dts/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 07d4d4b912..2264a80e33 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -533,6 +533,7 @@ #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; + resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; }; gem1: ethernet@ff0c0000 { @@ -547,6 +548,7 @@ #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; + resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; }; gem2: ethernet@ff0d0000 { @@ -561,6 +563,7 @@ #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; + resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; }; gem3: ethernet@ff0e0000 { @@ -575,6 +578,7 @@ #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; + resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; }; gpio: gpio@ff0a0000 { From ca442169412ae74c1c45b4da5432bdbe74c6e890 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 18 Nov 2021 13:42:28 +0100 Subject: [PATCH 06/36] arm64: zynqmp: Remove clock-names from GEM in zynqmp-clk-ccf.dtsi Remove clock-names from GEM nodes from clk-ccf because they should be only present in zynqmp.dtsi. And as is visible both clock-names defined didn't really match. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d6045d81b3e7e97df0ba3eeacb9f3f75ed7cff18.1637239345.git.michal.simek@xilinx.com --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 4 ---- arch/arm/dts/zynqmp.dtsi | 8 ++++---- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index b27b0aaf7c..664e65896d 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -169,28 +169,24 @@ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; - clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; - clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; - clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; - clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gpio { diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 2264a80e33..015a582d7a 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -527,7 +527,7 @@ interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk"; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; @@ -542,7 +542,7 @@ interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk"; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; @@ -557,7 +557,7 @@ interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk"; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; @@ -572,7 +572,7 @@ interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk"; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; From 5f4e1ff7f9b0a589a39359def30b5d2f11866449 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Thu, 18 Nov 2021 12:57:20 +0100 Subject: [PATCH 07/36] xilinx: versal: Fix sdhci node name as per DT Fix the sdhci node name in versal board file as per the name in device tree and also check for sdhci node as part of backward compatibility. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/9110ecdabcabcef63fffd4719095acf4326a26e4.1637236638.git.michal.simek@xilinx.com --- board/xilinx/versal/board.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 6045eb2baa..03604d730a 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -151,6 +151,8 @@ int board_late_init(void) case EMMC_MODE: puts("EMMC_MODE\n"); if (uclass_get_device_by_name(UCLASS_MMC, + "mmc@f1050000", &dev) && + uclass_get_device_by_name(UCLASS_MMC, "sdhci@f1050000", &dev)) { puts("Boot from EMMC but without SD1 enabled!\n"); return -1; @@ -162,6 +164,8 @@ int board_late_init(void) case SD_MODE: puts("SD_MODE\n"); if (uclass_get_device_by_name(UCLASS_MMC, + "mmc@f1040000", &dev) && + uclass_get_device_by_name(UCLASS_MMC, "sdhci@f1040000", &dev)) { puts("Boot from SD0 but without SD0 enabled!\n"); return -1; @@ -177,6 +181,8 @@ int board_late_init(void) case SD_MODE1: puts("SD_MODE1\n"); if (uclass_get_device_by_name(UCLASS_MMC, + "mmc@f1050000", &dev) && + uclass_get_device_by_name(UCLASS_MMC, "sdhci@f1050000", &dev)) { puts("Boot from SD1 but without SD1 enabled!\n"); return -1; From 67bf8888506150c7e72d5edfef1856976832a005 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 18 Nov 2021 12:58:15 +0100 Subject: [PATCH 08/36] arm64: zynqmp: Switch SOM to shared psu configuration Previous psu init was targeting SOM + KV260 carrier card and also contain configurations for other devices on carrier card. This config is removing all expected configurations for CC and let U-Boot to handle all of it self. This configuration is designed for SOM itself (and I would bet without eMMC). Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5782131058dc372befd3fdb4dceabeea5ba56606.1637236693.git.michal.simek@xilinx.com --- .../zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c | 200 ++++++------------ 1 file changed, 70 insertions(+), 130 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c index c448f2abb1..ed025790bc 100644 --- a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c @@ -9,33 +9,31 @@ static unsigned long psu_pll_init_data(void) { psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014000U); psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); mask_poll(0xFF5E0040, 0x00000002U); psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U); psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); - psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); - psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4E2C62U); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00013C00U); psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); mask_poll(0xFF5E0040, 0x00000001U); psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000200U); psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00015000U); psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); mask_poll(0xFD1A0044, 0x00000001U); psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x80000033U); psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); @@ -43,58 +41,43 @@ static unsigned long psu_pll_init_data(void) psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); mask_poll(0xFD1A0044, 0x00000002U); psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); - psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); mask_poll(0xFD1A0044, 0x00000004U); psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U); return 1; } static unsigned long psu_clock_init_data(void) { - psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); - psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); - psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); - psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U); - psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); - psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U); - psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); - psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U); - psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U); - psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); - psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); - psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); - psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); - psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); - psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U); - psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010A00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010A00U); + psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000402U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000500U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000202U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000A02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000402U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000202U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010A00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010A00U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011402U); psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); - psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); - psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U); - psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U); - psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000A00U); psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); - psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000300U); psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); @@ -133,8 +116,8 @@ static unsigned long psu_ddr_init_data(void) psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); - psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102411U); - psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102412U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU); psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU); psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); @@ -234,14 +217,14 @@ static unsigned long psu_ddr_init_data(void) psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E4U); psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); - psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07221008U); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07241008U); psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U); psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01762B07U); - psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00311008U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00331008U); psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E10U); psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); @@ -407,90 +390,63 @@ static unsigned long psu_mio_init_data(void) psu_mask_write(0xFF180028, 0x000000FEU, 0x00000080U); psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000080U); psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U); psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U); psu_mask_write(0xFF180068, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U); - psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U); - psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U); - psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000008U); psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); psu_mask_write(0xFF180090, 0x000000FEU, 0x000000C0U); psu_mask_write(0xFF180094, 0x000000FEU, 0x000000C0U); psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U); psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xD4000000U); - psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02020U); - psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); - psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x84000000U); + psu_mask_write(0xFF180208, 0x000FFFFFU, 0x00000020U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x00000000U); psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x00080835U); psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x03F7F7CAU); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x00FC000BU); psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x0357FFFFU); - psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x0303FFF4U); psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); return 1; @@ -506,24 +462,15 @@ static unsigned long psu_peripherals_pre_init_data(void) static unsigned long psu_peripherals_init_data(void) { - psu_mask_write(0xFD1A0100, 0x0001007EU, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x0000807CU, 0x00000000U); psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); - psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U); - psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U); - psu_mask_write(0xFF180320, 0x33843384U, 0x02841284U); - psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U); - psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U); - psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); - psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U); - psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000010U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000004U, 0x00000000U); psu_mask_write(0xFF010034, 0x000000FFU, 0x00000006U); psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000007CU); @@ -536,13 +483,6 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00040000U); - psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00040000U); - psu_mask_write(0xFF0A000C, 0x03FF03FFU, 0x03FB0004U); - mask_delay(1); - psu_mask_write(0xFF0A000C, 0x03FF03FFU, 0x03FB0000U); - mask_delay(5); - psu_mask_write(0xFF0A000C, 0x03FF03FFU, 0x03FB0004U); return 1; } From 380bd08370b363a4bfe76e70fbbaead10541445b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 18 Nov 2021 13:00:02 +0100 Subject: [PATCH 09/36] xilinx: firmware: Move dcache handling directly to pmufw load config Core function should make sure that data is stored properly that's why move cache operations directly to zynqmp_pmufw_load_config_object() to be able to call it from other functions. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8c92edd3650ce34a3cfd1c1e4e9103980830b1fa.1637236800.git.michal.simek@xilinx.com --- board/xilinx/zynqmp/cmds.c | 1 - drivers/firmware/firmware-zynqmp.c | 3 +++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index b15c0f599b..5a277c712f 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -211,7 +211,6 @@ static int do_zynqmp_pmufw(struct cmd_tbl *cmdtp, int flag, int argc, addr = hextoul(argv[2], NULL); size = hextoul(argv[3], NULL); - flush_dcache_range((ulong)addr, (ulong)(addr + size)); zynqmp_pmufw_load_config_object((const void *)(uintptr_t)addr, (size_t)size); diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index b44fede307..aa20e33b40 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -99,6 +100,8 @@ void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size) printf("Loading new PMUFW cfg obj (%ld bytes)\n", size); + flush_dcache_range((ulong)cfg_obj, (ulong)(cfg_obj + size)); + err = xilinx_pm_request(PM_SET_CONFIGURATION, (u32)(u64)cfg_obj, 0, 0, 0, ret_payload); if (err == XST_PM_NO_ACCESS) { From edf0f9b15eeaa6ca3d7bf69fa3163dcfa812d168 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Tue, 30 Nov 2021 18:33:49 +0200 Subject: [PATCH 10/36] microblaze: u-boot.lds: replace __end symbol with _end board_fdt_blob_setup() uses the _end symbol to find the dtb in the non-spl case. In order to allow microblaze builds to compile successfully with CONFIG_OF_SEPARATE, the _end symbol must be defined. Align microblaze with the other architectures and use _end symbol rather than __end to mark the end of the u-boot binary. Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20211130163358.2531677-2-ovidiu.panait@windriver.com Signed-off-by: Michal Simek --- arch/microblaze/cpu/start.S | 4 ++-- arch/microblaze/cpu/u-boot-spl.lds | 4 ++-- arch/microblaze/cpu/u-boot.lds | 2 +- arch/microblaze/include/asm/processor.h | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 9479737aa2..463e0feba4 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -15,7 +15,7 @@ _start: mts rmsr, r0 /* disable cache */ - addi r8, r0, __end + addi r8, r0, _end mts rslr, r8 #if defined(CONFIG_SPL_BUILD) @@ -270,7 +270,7 @@ relocate_code: add r23, r0, r7 /* Move reloc addr to r23 */ /* Relocate text and data - r12 temp value */ addi r21, r0, _start - addi r22, r0, __end - 4 /* Include BSS too */ + addi r22, r0, _end - 4 /* Include BSS too */ rsub r6, r21, r22 or r5, r0, r0 diff --git a/arch/microblaze/cpu/u-boot-spl.lds b/arch/microblaze/cpu/u-boot-spl.lds index 3387eb7189..7883a64b15 100644 --- a/arch/microblaze/cpu/u-boot-spl.lds +++ b/arch/microblaze/cpu/u-boot-spl.lds @@ -53,10 +53,10 @@ SECTIONS . = ALIGN(4); __bss_end = .; } - __end = . ; + _end = . ; } #if defined(CONFIG_SPL_MAX_FOOTPRINT) -ASSERT(__end - _start <= (CONFIG_SPL_MAX_FOOTPRINT), \ +ASSERT(_end - _start <= (CONFIG_SPL_MAX_FOOTPRINT), \ "SPL image plus BSS too big"); #endif diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds index 5dc09dbad2..2b316cc7f5 100644 --- a/arch/microblaze/cpu/u-boot.lds +++ b/arch/microblaze/cpu/u-boot.lds @@ -56,5 +56,5 @@ SECTIONS . = ALIGN(4); __bss_end = .; } - __end = . ; + _end = . ; } diff --git a/arch/microblaze/include/asm/processor.h b/arch/microblaze/include/asm/processor.h index 16e0d0ef0a..958018c190 100644 --- a/arch/microblaze/include/asm/processor.h +++ b/arch/microblaze/include/asm/processor.h @@ -8,7 +8,7 @@ /* References to section boundaries */ -extern char __end[]; +extern char _end[]; extern char __text_start[]; /* Microblaze board initialization function */ From b3fe1e8ff394d62b4c80117b8aa3cd82f7c364b1 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Tue, 30 Nov 2021 18:33:50 +0200 Subject: [PATCH 11/36] microblaze: spl: add board_boot_order() implementation Microblaze has three boot modes defined in microblaze/include/asm/spl.h, but only booting from NOR flash is currently useable. Add a custom board_boot_order() implementation so that RAM and SPI boot modes can also be selected if the corresponding load-image support is present. Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20211130163358.2531677-3-ovidiu.panait@windriver.com Signed-off-by: Michal Simek --- arch/microblaze/cpu/spl.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index 86522f8447..06d4af99b2 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -15,9 +15,11 @@ bool boot_linux; -u32 spl_boot_device(void) +void board_boot_order(u32 *spl_boot_list) { - return BOOT_DEVICE_NOR; + spl_boot_list[0] = BOOT_DEVICE_NOR; + spl_boot_list[1] = BOOT_DEVICE_RAM; + spl_boot_list[2] = BOOT_DEVICE_SPI; } /* Board initialization after bss clearance */ From 7a971dfbebf639a4a2fdf75909d6d50670c69545 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Tue, 30 Nov 2021 18:33:51 +0200 Subject: [PATCH 12/36] microblaze: Kconfig: SPL dependencies fixup Enable SPL_LIBCOMMON_SUPPORT and SPL_LIBGENERIC_SUPPORT if CONFIG_SPL=y, in order to fix the following link failures: common/spl/spl.o: in function `board_init_r': common/spl/spl.c:755: undefined reference to `puts' ... common/spl/spl.o: in function `board_init_r': common/spl/spl.c:756: undefined reference to `hang' common/spl/spl.c:740: undefined reference to `memset' Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20211130163358.2531677-4-ovidiu.panait@windriver.com Signed-off-by: Michal Simek --- arch/microblaze/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 99a17bccb3..a25a95a013 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -15,6 +15,8 @@ config TARGET_MICROBLAZE_GENERIC select DM_SERIAL select OF_CONTROL select SUPPORT_SPL + select SPL_LIBCOMMON_SUPPORT if SPL + select SPL_LIBGENERIC_SUPPORT if SPL select SYSRESET select DM_SPI select DM_SPI_FLASH From 48039c333f057a8f95420e1ddf33c77ac974a113 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Tue, 30 Nov 2021 18:33:52 +0200 Subject: [PATCH 13/36] microblaze: start.S: use stack space as scratch memory for endian offset To simpify the code, use stack space as scratch memory for endian offset calculation, rather than saving/restoring the first unused MB vector. Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20211130163358.2531677-5-ovidiu.panait@windriver.com Signed-off-by: Michal Simek --- arch/microblaze/cpu/start.S | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 463e0feba4..a1c06108d7 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -125,10 +125,8 @@ __setup_exceptions: * 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3 */ addik r6, r0, 0x2 /* BIG/LITTLE endian offset */ - lwi r7, r0, 0x28 - swi r6, r0, 0x28 /* used first unused MB vector */ - lbui r10, r0, 0x28 /* used first unused MB vector */ - swi r7, r0, 0x28 + sw r6, r1, r0 + lbu r10, r1, r0 /* add opcode instruction for 32bit jump - 2 instruction imm & brai */ addi r2, r0, 0xb0000000 /* hex b000 opcode imm */ From 70c68712ef0b6b6433cf48ac3f561b5896388554 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Tue, 30 Nov 2021 18:33:53 +0200 Subject: [PATCH 14/36] microblaze: drop CONFIG_SYS_RESET_ADDRESS macro Microblaze is one the last two users of the CONFIG_SYS_RESET_ADDRESS macro (the other is arch/powerpc/cpu/mpc8xx/cpu.c, but the macro is not defined anywhere in powerpc code, so it should be removed there too). Replace CONFIG_SYS_RESET_ADDRESS usage in start.S with CONFIG_SYS_TEXT_BASE. If the reset address should really be user-configurable, a new Kconfig option could be added. Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20211130163358.2531677-6-ovidiu.panait@windriver.com Signed-off-by: Michal Simek --- arch/microblaze/cpu/start.S | 4 +--- include/configs/microblaze-generic.h | 3 --- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index a1c06108d7..74ed998c55 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -132,19 +132,17 @@ __setup_exceptions: addi r2, r0, 0xb0000000 /* hex b000 opcode imm */ addi r3, r0, 0xb8080000 /* hew b808 opcode brai */ -#ifdef CONFIG_SYS_RESET_ADDRESS /* reset address */ swi r2, r0, 0x0 /* reset address - imm opcode */ swi r3, r0, 0x4 /* reset address - brai opcode */ - addik r6, r0, CONFIG_SYS_RESET_ADDRESS + addik r6, r0, CONFIG_SYS_TEXT_BASE sw r6, r1, r0 lhu r7, r1, r10 rsubi r8, r10, 0x2 sh r7, r0, r8 rsubi r8, r10, 0x6 sh r6, r0, r8 -#endif #ifdef CONFIG_SYS_USR_EXCEP /* user_vector_exception */ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index e7882fb607..975580e4d4 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -21,9 +21,6 @@ # define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -/* setting reset address */ -/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ - /* Stack location before relocation */ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \ CONFIG_SYS_MALLOC_F_LEN) From 83b175be16893c25509f6d2959f1b457101fbcf9 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Tue, 30 Nov 2021 18:33:54 +0200 Subject: [PATCH 15/36] microblaze: migrate CONFIG_SYS_USR_EXCEP to Kconfig Migrate CONFIG_SYS_USR_EXCEP to Kconfig. Also, rename it to XILINX_MICROBLAZE0_USR_EXCEP in order to match the naming convention of microblaze-generic Kconfig options. Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20211130163358.2531677-7-ovidiu.panait@windriver.com Signed-off-by: Michal Simek --- arch/microblaze/cpu/exception.c | 2 +- arch/microblaze/cpu/start.S | 2 +- board/xilinx/microblaze-generic/Kconfig | 9 +++++++++ include/configs/microblaze-generic.h | 2 -- scripts/config_whitelist.txt | 1 - 5 files changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c index b8dedc4e19..e9476abedb 100644 --- a/arch/microblaze/cpu/exception.c +++ b/arch/microblaze/cpu/exception.c @@ -55,7 +55,7 @@ void _hw_exception_handler (void) hang(); } -#ifdef CONFIG_SYS_USR_EXCEP +#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP) void _exception_handler (void) { puts("User vector_exception\n"); diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 74ed998c55..68f97f426c 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -144,7 +144,7 @@ __setup_exceptions: rsubi r8, r10, 0x6 sh r6, r0, r8 -#ifdef CONFIG_SYS_USR_EXCEP +#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP) /* user_vector_exception */ swi r2, r0, 0x8 /* user vector exception - imm opcode */ swi r3, r0, 0xC /* user vector exception - brai opcode */ diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig index f2fa0f72b1..3e3eca0e80 100644 --- a/board/xilinx/microblaze-generic/Kconfig +++ b/board/xilinx/microblaze-generic/Kconfig @@ -38,4 +38,13 @@ config XILINX_MICROBLAZE0_HW_VER string "Core version number" default "7.10.d" +config XILINX_MICROBLAZE0_USR_EXCEP + bool "MicroBlaze user exception support" + default y + help + Enable this option in order to install the user exception handler + (_exception_handler routine from arch/microblaze/cpu/exception.c) in + the exception vector table. The user exception vector is located at + C_BASE_VECTORS + 0x8 address. + endif diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 975580e4d4..28f67e30d5 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -54,8 +54,6 @@ #define CONFIG_HOSTNAME "microblaze-generic" /* architecture dependent code */ -#define CONFIG_SYS_USR_EXCEP /* user exception */ - #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) #else diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index b9c1c61e13..c53c2c3801 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2870,7 +2870,6 @@ CONFIG_SYS_USE_MMC CONFIG_SYS_USE_NAND CONFIG_SYS_USE_NANDFLASH CONFIG_SYS_USE_NORFLASH -CONFIG_SYS_USR_EXCEP CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT From b6aef109799614f1efa921bdb8a73e461d9bcbdd Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Tue, 30 Nov 2021 18:33:55 +0200 Subject: [PATCH 16/36] microblaze: add Kconfig symbol for the vector base address MicroBlaze vector base address is configurable (hdl C_BASE_VECTORS configuration parameter). Current code assumes that the reset vector location is always 0x0. Add the XILINX_MICROBLAZE0_VECTOR_BASE_ADDR Kconfig option so the user can adjust the reset vector address. Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20211130163358.2531677-8-ovidiu.panait@windriver.com Signed-off-by: Michal Simek --- board/xilinx/microblaze-generic/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig index 3e3eca0e80..e31257d335 100644 --- a/board/xilinx/microblaze-generic/Kconfig +++ b/board/xilinx/microblaze-generic/Kconfig @@ -47,4 +47,11 @@ config XILINX_MICROBLAZE0_USR_EXCEP the exception vector table. The user exception vector is located at C_BASE_VECTORS + 0x8 address. +config XILINX_MICROBLAZE0_VECTOR_BASE_ADDR + hex "Location of MicroBlaze vectors" + default 0x0 + help + Memory address location of the exception vector table. It is + configurable via the C_BASE_VECTORS hdl parameter. + endif From f149ee4c36dd907de496ff1a370adcdea5cb17ce Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Tue, 30 Nov 2021 18:33:56 +0200 Subject: [PATCH 17/36] microblaze: start.S: add support for configurable vector base address Current code assumes that the vector base address is always at 0x0. However, this value is configurable for MicroBlaze, so update the __setup_exceptions routine to work with any vector base address. The r4 register is reserved for the vector base address inside __setup_exceptions and the function prologe/epilogue are also updated to save and restore r4. Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20211130163358.2531677-9-ovidiu.panait@windriver.com Signed-off-by: Michal Simek --- arch/microblaze/cpu/start.S | 58 ++++++++++++++++++++----------------- 1 file changed, 32 insertions(+), 26 deletions(-) diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 68f97f426c..645f7cb038 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -105,15 +105,17 @@ clear_bss: * r10: Stores little/big endian offset for vectors * r2: Stores imm opcode * r3: Stores brai opcode + * r4: Stores the vector base address */ __setup_exceptions: - addik r1, r1, -28 + addik r1, r1, -32 swi r2, r1, 4 swi r3, r1, 8 - swi r6, r1, 12 - swi r7, r1, 16 - swi r8, r1, 20 - swi r10, r1, 24 + swi r4, r1, 12 + swi r6, r1, 16 + swi r7, r1, 20 + swi r8, r1, 24 + swi r10, r1, 28 /* Find-out if u-boot is running on BIG/LITTLE endian platform * There are some steps which is necessary to keep in mind: @@ -132,22 +134,25 @@ __setup_exceptions: addi r2, r0, 0xb0000000 /* hex b000 opcode imm */ addi r3, r0, 0xb8080000 /* hew b808 opcode brai */ + /* Store the vector base address in r4 */ + addi r4, r0, CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR + /* reset address */ - swi r2, r0, 0x0 /* reset address - imm opcode */ - swi r3, r0, 0x4 /* reset address - brai opcode */ + swi r2, r4, 0x0 /* reset address - imm opcode */ + swi r3, r4, 0x4 /* reset address - brai opcode */ addik r6, r0, CONFIG_SYS_TEXT_BASE sw r6, r1, r0 lhu r7, r1, r10 rsubi r8, r10, 0x2 - sh r7, r0, r8 + sh r7, r4, r8 rsubi r8, r10, 0x6 - sh r6, r0, r8 + sh r6, r4, r8 #if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP) /* user_vector_exception */ - swi r2, r0, 0x8 /* user vector exception - imm opcode */ - swi r3, r0, 0xC /* user vector exception - brai opcode */ + swi r2, r4, 0x8 /* user vector exception - imm opcode */ + swi r3, r4, 0xC /* user vector exception - brai opcode */ addik r6, r5, _exception_handler sw r6, r1, r0 @@ -173,42 +178,43 @@ __setup_exceptions: */ lhu r7, r1, r10 rsubi r8, r10, 0xa - sh r7, r0, r8 + sh r7, r4, r8 rsubi r8, r10, 0xe - sh r6, r0, r8 + sh r6, r4, r8 #endif /* interrupt_handler */ - swi r2, r0, 0x10 /* interrupt - imm opcode */ - swi r3, r0, 0x14 /* interrupt - brai opcode */ + swi r2, r4, 0x10 /* interrupt - imm opcode */ + swi r3, r4, 0x14 /* interrupt - brai opcode */ addik r6, r5, _interrupt_handler sw r6, r1, r0 lhu r7, r1, r10 rsubi r8, r10, 0x12 - sh r7, r0, r8 + sh r7, r4, r8 rsubi r8, r10, 0x16 - sh r6, r0, r8 + sh r6, r4, r8 /* hardware exception */ - swi r2, r0, 0x20 /* hardware exception - imm opcode */ - swi r3, r0, 0x24 /* hardware exception - brai opcode */ + swi r2, r4, 0x20 /* hardware exception - imm opcode */ + swi r3, r4, 0x24 /* hardware exception - brai opcode */ addik r6, r5, _hw_exception_handler sw r6, r1, r0 lhu r7, r1, r10 rsubi r8, r10, 0x22 - sh r7, r0, r8 + sh r7, r4, r8 rsubi r8, r10, 0x26 - sh r6, r0, r8 + sh r6, r4, r8 - lwi r10, r1, 24 - lwi r8, r1, 20 - lwi r7, r1, 16 - lwi r6, r1, 12 + lwi r10, r1, 28 + lwi r8, r1, 24 + lwi r7, r1, 20 + lwi r6, r1, 16 + lwi r4, r1, 12 lwi r3, r1, 8 lwi r2, r1, 4 - addik r1, r1, 28 + addik r1, r1, 32 rtsd r15, 8 or r0, r0, r0 From fc7220f0c4ed2ce7bc89f50c33f37e39b77e2690 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Tue, 30 Nov 2021 18:33:57 +0200 Subject: [PATCH 18/36] microblaze: branch to base vector address on reset Current code assumes that the vector base address is always at 0x0. However, this value is configurable for MicroBlaze using the CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR Kconfig option. Update the reset routines to branch to this location instead. Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20211130163358.2531677-10-ovidiu.panait@windriver.com Signed-off-by: Michal Simek --- arch/microblaze/cpu/spl.c | 6 ++++-- drivers/sysreset/sysreset_microblaze.c | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index 06d4af99b2..cea6d56f16 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -12,6 +12,7 @@ #include #include #include +#include bool boot_linux; @@ -54,8 +55,9 @@ int spl_start_uboot(void) int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - __asm__ __volatile__ ("mts rmsr, r0;" \ - "bra r0"); + __asm__ __volatile__ ( + "mts rmsr, r0;" \ + "brai " __stringify(CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR)); return 0; } diff --git a/drivers/sysreset/sysreset_microblaze.c b/drivers/sysreset/sysreset_microblaze.c index 514c95817f..83a7f77ac4 100644 --- a/drivers/sysreset/sysreset_microblaze.c +++ b/drivers/sysreset/sysreset_microblaze.c @@ -8,13 +8,15 @@ #include #include #include +#include static int microblaze_sysreset_request(struct udevice *dev, enum sysreset_t type) { puts("Microblaze soft reset sysreset\n"); - __asm__ __volatile__ (" mts rmsr, r0;" \ - "bra r0"); + __asm__ __volatile__ ( + "mts rmsr, r0;" \ + "brai " __stringify(CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR)); return -EINPROGRESS; } From bb113ce313214cb754365baf4615b4d57910279f Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Thu, 2 Dec 2021 21:56:56 +0200 Subject: [PATCH 19/36] xilinx: Kconfig: add XILINX_OF_BOARD_DTB_ADDR default value for microblaze The xilinx board_fdt_blob_setup() implementation makes use of XILINX_OF_BOARD_DTB_ADDR, but no default value is currently defined for microblaze. Add one so that microblaze could also work with CONFIG_OF_SEPARATE. Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20211202195657.246723-1-ovidiu.panait@windriver.com Signed-off-by: Michal Simek --- board/xilinx/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 64507b5d84..1788066173 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -43,6 +43,7 @@ endif config XILINX_OF_BOARD_DTB_ADDR hex "Default DTB pickup address" default 0x1000 if ARCH_VERSAL + default 0x8000 if MICROBLAZE default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP depends on OF_BOARD || OF_SEPARATE help From bf97c460a403fa884320643f065fff4758dcf54e Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Wed, 24 Nov 2021 12:16:55 +0100 Subject: [PATCH 20/36] versal: Return ENVL_NOWHERE instead of ENVL_UNKNOWN The system fails to boot without any environment location, so return ENVL_NOWHERE when there's nowhere to store the environment instead of ENVL_UNKNOWN. The same change was also done by commit 50918d0df5cb ("xilinx: Return ENVL_NOWHERE instead of ENVL_UNKNOWN") for zynq and zynqmp. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e4ed36408f10159677ed8060bfd5289f3e0691fa.1637752614.git.michal.simek@xilinx.com --- board/xilinx/versal/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 03604d730a..299e128f7b 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -269,13 +269,13 @@ enum env_location env_get_location(enum env_operation op, int prio) return ENVL_FAT; if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4)) return ENVL_EXT4; - return ENVL_UNKNOWN; + return ENVL_NOWHERE; case OSPI_MODE: case QSPI_MODE_24BIT: case QSPI_MODE_32BIT: if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) return ENVL_SPI_FLASH; - return ENVL_UNKNOWN; + return ENVL_NOWHERE; case JTAG_MODE: default: return ENVL_NOWHERE; From ac64f536af078a2e5a9dce984b0e42d92e87f87e Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Tue, 30 Nov 2021 13:56:58 +0100 Subject: [PATCH 21/36] dt-bindings: versal: Add new PM_DEV_I2C_PMC macro Add new macro for PMC I2C power domain. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/0bf164f937df551d689dda2a35f9489c2e46b4ab.1638277017.git.michal.simek@xilinx.com --- include/dt-bindings/power/xlnx-versal-power.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/power/xlnx-versal-power.h b/include/dt-bindings/power/xlnx-versal-power.h index 1b75175edc..4a727754ad 100644 --- a/include/dt-bindings/power/xlnx-versal-power.h +++ b/include/dt-bindings/power/xlnx-versal-power.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 - 2020 Xilinx, Inc. + * Copyright (C) 2019 - 2021 Xilinx, Inc. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H @@ -26,6 +26,7 @@ #define PM_DEV_OSPI (0x1822402aU) #define PM_DEV_QSPI (0x1822402bU) #define PM_DEV_GPIO_PMC (0x1822402cU) +#define PM_DEV_I2C_PMC (0x1822402dU) #define PM_DEV_SDIO_0 (0x1822402eU) #define PM_DEV_SDIO_1 (0x1822402fU) #define PM_DEV_RTC (0x18224034U) From 12133b11a7ff817fd96210eeb7e84ff9f871e714 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 6 Dec 2021 14:53:17 +0100 Subject: [PATCH 22/36] net: zynq: Add support for mdio bus address decoding Xilinx DTS files are using two way how to describe ethernet phy. The first (already supported) has phy as subnode of gem node. eth { phy-handle = <&phy0>; phy0: ethernet-phy@21 { ... }; }; The second has mdio subnode (with mdio name) which has phy subnode. This structure allow hadling MDIO reset signal (based on Linux mdio.yaml) eth { phy-handle = <&phy0>; mdio { phy0: ethernet-phy@21 { ... }; }; }; This patch adds support for the second case where mdio subnode is found driver will look at its parent to find out which gem is handling MDIO bus. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/6748007f0b6db9554d7a4b52352dce23ca403f9d.1638798796.git.michal.simek@xilinx.com --- drivers/net/zynq_gem.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index c309c3c954..de61321072 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -802,6 +802,9 @@ static int zynq_gem_of_to_plat(struct udevice *dev) SPEED_1000); parent = ofnode_get_parent(phandle_args.node); + if (ofnode_name_eq(parent, "mdio")) + parent = ofnode_get_parent(parent); + addr = ofnode_get_addr(parent); if (addr != FDT_ADDR_T_NONE) { debug("MDIO bus not found %s\n", dev->name); From b5ffc9f758a7a25c4aeabe8a6e889febc989bb4c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 6 Dec 2021 16:25:20 +0100 Subject: [PATCH 23/36] net: zynq: Add support for GEM reset Perform reset before core initialization. Standard flow which close to 99% users are using getting all IPs out of reset that there is no need to reset IP again. This is because of all low level initialization is done in previous bootloader stage. In SOM case these IPs are not touched by previous bootloader stage that's why reset needs to be called before IP is accessed to make sure that it is in correct state. Signed-off-by: Michal Simek Reviewed-by: Ramon Fried Link: https://lore.kernel.org/r/5ae1c85b282d632bb62030f1f24a0065661b9153.1638804318.git.michal.simek@xilinx.com --- drivers/net/zynq_gem.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index de61321072..56f668c249 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -215,6 +216,7 @@ struct zynq_gem_priv { bool int_pcs; bool dma_64bit; u32 clk_en_info; + struct reset_ctl_bulk resets; }; static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, @@ -686,12 +688,36 @@ static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, return phywrite(priv, addr, reg, value); } +static int zynq_gem_reset_init(struct udevice *dev) +{ + struct zynq_gem_priv *priv = dev_get_priv(dev); + int ret; + + ret = reset_get_bulk(dev, &priv->resets); + if (ret == -ENOTSUPP || ret == -ENOENT) + return 0; + else if (ret) + return ret; + + ret = reset_deassert_bulk(&priv->resets); + if (ret) { + reset_release_bulk(&priv->resets); + return ret; + } + + return 0; +} + static int zynq_gem_probe(struct udevice *dev) { void *bd_space; struct zynq_gem_priv *priv = dev_get_priv(dev); int ret; + ret = zynq_gem_reset_init(dev); + if (ret) + return ret; + /* Align rxbuffers to ARCH_DMA_MINALIGN */ priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); if (!priv->rxbuffers) From 10c50b1facbfccbc70099adef629b5a988ec2bb2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 15 Dec 2021 11:00:01 +0100 Subject: [PATCH 24/36] net: zynq: Add support for PHY configuration in SGMII mode SGMII configuration depends on proper GT setting that's why when node has phys property call PSGTR driver to configure it properly. Signed-off-by: Michal Simek Reviewed-by: Sean Anderson Link: https://lore.kernel.org/r/bbc8d7ed9d308199168e4455c7a3e3a5ac0890e7.1639562397.git.michal.simek@xilinx.com --- drivers/net/zynq_gem.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 56f668c249..336d569b37 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -713,6 +714,19 @@ static int zynq_gem_probe(struct udevice *dev) void *bd_space; struct zynq_gem_priv *priv = dev_get_priv(dev); int ret; + struct phy phy; + + if (priv->interface == PHY_INTERFACE_MODE_SGMII) { + ret = generic_phy_get_by_index(dev, 0, &phy); + if (!ret) { + ret = generic_phy_init(&phy); + if (ret) + return ret; + } else if (ret != -ENOENT) { + debug("could not get phy (err %d)\n", ret); + return ret; + } + } ret = zynq_gem_reset_init(dev); if (ret) @@ -769,6 +783,12 @@ static int zynq_gem_probe(struct udevice *dev) if (ret) goto err3; + if (priv->interface == PHY_INTERFACE_MODE_SGMII && phy.dev) { + ret = generic_phy_power_on(&phy); + if (ret) + return ret; + } + return ret; err3: From 2a9caba1ceff85c7c07dcb43d48b4c8cf8c79f5e Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Thu, 18 Nov 2021 13:05:24 +0100 Subject: [PATCH 25/36] net: gem: Reduce timeout of mdio phy idle status check Timeout for checking mdio phy idle status is 20seconds. In case of errors this timeout will be too much. Reduce it to 100ms. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Reviewed-by: Ramon Fried Link: https://lore.kernel.org/r/1b73aa57b77587391e1bcd6d9f0480163367ed1b.1637237121.git.michal.simek@xilinx.com --- drivers/net/zynq_gem.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 336d569b37..b751d28e61 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -112,6 +112,8 @@ #define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23) +#define MDIO_IDLE_TIMEOUT_MS 100 + /* Use MII register 1 (MII status register) to detect PHY */ #define PHY_DETECT_REG 1 @@ -228,7 +230,7 @@ static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, int err; err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, - true, 20000, false); + true, MDIO_IDLE_TIMEOUT_MS, false); if (err) return err; @@ -241,7 +243,7 @@ static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, writel(mgtcr, ®s->phymntnc); err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, - true, 20000, false); + true, MDIO_IDLE_TIMEOUT_MS, false); if (err) return err; From 381e6e5494d422a2adcede3da9f967c22c6ad123 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 11 Jan 2022 10:28:09 +0100 Subject: [PATCH 26/36] net: uclass: Save generated ethernet MAC addresses to the environment When a MAC address is randomly generated we currently only update the appropriate data structure. For consistency and to re-align with historic usage, it should be also saved to the appropriate environment variable as well. Cc: Wolfgang Denk Signed-off-by: Michal Simek Reviewed-by: Ramon Fried [trini: Update Kconfig, handle legacy networking case as well] Signed-off-by: Tom Rini Acked-by: Ramon Fried Link: https://lore.kernel.org/r/1a2518e3cc19c14a41875ef64c5acc1f16edc813.1641893287.git.michal.simek@xilinx.com --- net/Kconfig | 9 +++++---- net/eth-uclass.c | 2 ++ net/eth_legacy.c | 2 ++ 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/net/Kconfig b/net/Kconfig index 7a2d145018..cabe93c6bd 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -27,10 +27,11 @@ config BOOTP_SEND_HOSTNAME config NET_RANDOM_ETHADDR bool "Random ethaddr if unset" help - Selecting this will allow the Ethernet interface to function - even when the ethaddr variable for that interface is unset. - A new MAC address will be generated on every boot and it will - not be added to the environment. + Selecting this will allow the Ethernet interface to function even + when the ethaddr variable for that interface is unset. In this case, + a random MAC address in the locally administered address space is + generated. It will be saved to the appropriate environment variable, + too. config NETCONSOLE bool "NetConsole support" diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 0da0e85be0..58c308f332 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -583,6 +583,8 @@ static int eth_post_probe(struct udevice *dev) net_random_ethaddr(pdata->enetaddr); printf("\nWarning: %s (eth%d) using random MAC address - %pM\n", dev->name, dev_seq(dev), pdata->enetaddr); + eth_env_set_enetaddr_by_index("eth", dev_seq(dev), + pdata->enetaddr); #else printf("\nError: %s address not set.\n", dev->name); diff --git a/net/eth_legacy.c b/net/eth_legacy.c index f383ccce0b..0b282d918b 100644 --- a/net/eth_legacy.c +++ b/net/eth_legacy.c @@ -164,6 +164,8 @@ int eth_write_hwaddr(struct eth_device *dev, const char *base_name, net_random_ethaddr(dev->enetaddr); printf("\nWarning: %s (eth%d) using random MAC address - %pM\n", dev->name, eth_number, dev->enetaddr); + eth_env_set_enetaddr_by_index("eth", eth_number, + dev->enetaddr); #else printf("\nError: %s address not set.\n", dev->name); From 28880b68d4e4760ebe54806eeff49ff61961ff8e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 11 Jan 2022 13:55:19 +0100 Subject: [PATCH 27/36] serial: zynq: Add missing xlnx,zynqmp-uart compatible Based on Linux kernel DT binding xlnx,zynqmp-uart is another compatible string which can be used for this driver. That's why also list it here. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/959a4cbbdd06a7fca2d9251ff0f535863a562b96.1641905717.git.michal.simek@xilinx.com --- drivers/serial/serial_zynq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 2f49f594a4..fd999368ab 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -272,6 +272,7 @@ static const struct udevice_id zynq_serial_ids[] = { { .compatible = "xlnx,xuartps" }, { .compatible = "cdns,uart-r1p8" }, { .compatible = "cdns,uart-r1p12" }, + { .compatible = "xlnx,zynqmp-uart" }, { } }; From 1d78d68349621316ddff95a0d0d3ab9360061a9a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 6 Jan 2022 09:49:41 +0100 Subject: [PATCH 28/36] phy: zynqmp: Add serdes/psgtr driver Add PSGTR driver for Xilinx ZynqMP. The most of configurations are taken from Linux kernel psgtr driver. USB3.0 and SGMII configurations are tested on SOM. In SGMII case also IOU_SLCR reg is updated to get proper clock setup and signal detection configuration. Signed-off-by: Michal Simek Reviewed-by: Simon Glass Link: https://lore.kernel.org/r/36e6e9d3baf8511af1916e91e4887032ca2b6c20.1641458978.git.michal.simek@xilinx.com --- MAINTAINERS | 1 + drivers/phy/Kconfig | 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-zynqmp.c | 754 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 763 insertions(+) create mode 100644 drivers/phy/phy-zynqmp.c diff --git a/MAINTAINERS b/MAINTAINERS index b3b5c1c170..5f633b56e6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -611,6 +611,7 @@ F: drivers/mmc/zynq_sdhci.c F: drivers/mtd/nand/raw/zynq_nand.c F: drivers/net/phy/xilinx_phy.c F: drivers/net/zynq_gem.c +F: drivers/phy/phy-zynqmp.c F: drivers/serial/serial_zynq.c F: drivers/reset/reset-zynqmp.c F: drivers/rtc/zynqmp_rtc.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 4767d215f3..d79798429b 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -281,6 +281,13 @@ config PHY_IMX8MQ_USB help Support the USB3.0 PHY in NXP i.MX8MQ SoC +config PHY_XILINX_ZYNQMP + tristate "Xilinx ZynqMP PHY driver" + depends on PHY && ARCH_ZYNQMP + help + Enable this to support ZynqMP High Speed Gigabit Transceiver + that is part of ZynqMP SoC. + source "drivers/phy/rockchip/Kconfig" source "drivers/phy/cadence/Kconfig" source "drivers/phy/ti/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 13a8ade891..bf9b40932f 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -38,5 +38,6 @@ obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o +obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o obj-y += cadence/ obj-y += ti/ diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c new file mode 100644 index 0000000000..9dc3d426a3 --- /dev/null +++ b/drivers/phy/phy-zynqmp.c @@ -0,0 +1,754 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT. + * + * Copyright (C) 2018-2021 Xilinx Inc. + * + * Author: Anurag Kumar Vulisha + * Author: Subbaraya Sundeep + * Author: Laurent Pinchart + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Lane Registers + */ + +/* TX De-emphasis parameters */ +#define L0_TX_ANA_TM_18 0x0048 +#define L0_TX_ANA_TM_118 0x01d8 +#define L0_TX_ANA_TM_118_FORCE_17_0 BIT(0) + +/* DN Resistor calibration code parameters */ +#define L0_TXPMA_ST_3 0x0b0c +#define L0_DN_CALIB_CODE 0x3f + +/* PMA control parameters */ +#define L0_TXPMD_TM_45 0x0cb4 +#define L0_TXPMD_TM_48 0x0cc0 +#define L0_TXPMD_TM_45_OVER_DP_MAIN BIT(0) +#define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1) +#define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2) +#define L0_TXPMD_TM_45_ENABLE_DP_POST1 BIT(3) +#define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4) +#define L0_TXPMD_TM_45_ENABLE_DP_POST2 BIT(5) + +/* PCS control parameters */ +#define L0_TM_DIG_6 0x106c +#define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f +#define L0_TX_DIG_61 0x00f4 +#define L0_TM_DISABLE_SCRAMBLE_ENCODER 0x0f + +/* PLL Test Mode register parameters */ +#define L0_TM_PLL_DIG_37 0x2094 +#define L0_TM_COARSE_CODE_LIMIT 0x10 + +/* PLL SSC step size offsets */ +#define L0_PLL_SS_STEPS_0_LSB 0x2368 +#define L0_PLL_SS_STEPS_1_MSB 0x236c +#define L0_PLL_SS_STEP_SIZE_0_LSB 0x2370 +#define L0_PLL_SS_STEP_SIZE_1 0x2374 +#define L0_PLL_SS_STEP_SIZE_2 0x2378 +#define L0_PLL_SS_STEP_SIZE_3_MSB 0x237c +#define L0_PLL_STATUS_READ_1 0x23e4 + +/* SSC step size parameters */ +#define STEP_SIZE_0_MASK 0xff +#define STEP_SIZE_1_MASK 0xff +#define STEP_SIZE_2_MASK 0xff +#define STEP_SIZE_3_MASK 0x3 +#define STEP_SIZE_SHIFT 8 +#define FORCE_STEP_SIZE 0x10 +#define FORCE_STEPS 0x20 +#define STEPS_0_MASK 0xff +#define STEPS_1_MASK 0x07 + +/* Reference clock selection parameters */ +#define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4) +#define L0_REF_CLK_SEL_MASK 0x8f + +/* Calibration digital logic parameters */ +#define L3_TM_CALIB_DIG19 0xec4c +#define L3_CALIB_DONE_STATUS 0xef14 +#define L3_TM_CALIB_DIG18 0xec48 +#define L3_TM_CALIB_DIG19_NSW 0x07 +#define L3_TM_CALIB_DIG18_NSW 0xe0 +#define L3_TM_OVERRIDE_NSW_CODE 0x20 +#define L3_CALIB_DONE 0x02 +#define L3_NSW_SHIFT 5 +#define L3_NSW_PIPE_SHIFT 4 +#define L3_NSW_CALIB_SHIFT 3 + +#define PHY_REG_OFFSET 0x4000 + +/* + * Global Registers + */ + +/* Refclk selection parameters */ +#define PLL_REF_SEL(n) (0x10000 + (n) * 4) +#define PLL_FREQ_MASK 0x1f +#define PLL_STATUS_LOCKED 0x10 + +/* Inter Connect Matrix parameters */ +#define ICM_CFG0 0x10010 +#define ICM_CFG1 0x10014 +#define ICM_CFG0_L0_MASK 0x07 +#define ICM_CFG0_L1_MASK 0x70 +#define ICM_CFG1_L2_MASK 0x07 +#define ICM_CFG2_L3_MASK 0x70 +#define ICM_CFG_SHIFT 4 + +/* Inter Connect Matrix allowed protocols */ +#define ICM_PROTOCOL_PD 0x0 +#define ICM_PROTOCOL_PCIE 0x1 +#define ICM_PROTOCOL_SATA 0x2 +#define ICM_PROTOCOL_USB 0x3 +#define ICM_PROTOCOL_DP 0x4 +#define ICM_PROTOCOL_SGMII 0x5 + +/* Test Mode common reset control parameters */ +#define TM_CMN_RST 0x10018 +#define TM_CMN_RST_EN 0x1 +#define TM_CMN_RST_SET 0x2 +#define TM_CMN_RST_MASK 0x3 + +/* Bus width parameters */ +#define TX_PROT_BUS_WIDTH 0x10040 +#define RX_PROT_BUS_WIDTH 0x10044 +#define PROT_BUS_WIDTH_10 0x0 +#define PROT_BUS_WIDTH_20 0x1 +#define PROT_BUS_WIDTH_40 0x2 +#define PROT_BUS_WIDTH_MASK 0x3 +#define PROT_BUS_WIDTH_SHIFT 2 + +/* Number of GT lanes */ +#define NUM_LANES 4 + +/* SIOU SATA control register */ +#define SATA_CONTROL_OFFSET 0x0100 + +/* Total number of controllers */ +#define CONTROLLERS_PER_LANE 5 + +/* Protocol Type parameters */ +enum { + XPSGTR_TYPE_USB0 = 0, /* USB controller 0 */ + XPSGTR_TYPE_USB1 = 1, /* USB controller 1 */ + XPSGTR_TYPE_SATA_0 = 2, /* SATA controller lane 0 */ + XPSGTR_TYPE_SATA_1 = 3, /* SATA controller lane 1 */ + XPSGTR_TYPE_PCIE_0 = 4, /* PCIe controller lane 0 */ + XPSGTR_TYPE_PCIE_1 = 5, /* PCIe controller lane 1 */ + XPSGTR_TYPE_PCIE_2 = 6, /* PCIe controller lane 2 */ + XPSGTR_TYPE_PCIE_3 = 7, /* PCIe controller lane 3 */ + XPSGTR_TYPE_DP_0 = 8, /* Display Port controller lane 0 */ + XPSGTR_TYPE_DP_1 = 9, /* Display Port controller lane 1 */ + XPSGTR_TYPE_SGMII0 = 10, /* Ethernet SGMII controller 0 */ + XPSGTR_TYPE_SGMII1 = 11, /* Ethernet SGMII controller 1 */ + XPSGTR_TYPE_SGMII2 = 12, /* Ethernet SGMII controller 2 */ + XPSGTR_TYPE_SGMII3 = 13, /* Ethernet SGMII controller 3 */ +}; + +/* Timeout values */ +#define TIMEOUT_US 1000 + +#define IOU_SLCR_GEM_CLK_CTRL 0x308 +#define GEM_CTRL_GEM_SGMII_MODE BIT(2) +#define GEM_CTRL_GEM_REF_SRC_SEL BIT(1) + +#define IOU_SLCR_GEM_CTRL 0x360 +#define GEM_CTRL_GEM_SGMII_SD BIT(0) + +/** + * struct xpsgtr_ssc - structure to hold SSC settings for a lane + * @refclk_rate: PLL reference clock frequency + * @pll_ref_clk: value to be written to register for corresponding ref clk rate + * @steps: number of steps of SSC (Spread Spectrum Clock) + * @step_size: step size of each step + */ +struct xpsgtr_ssc { + u32 refclk_rate; + u8 pll_ref_clk; + u32 steps; + u32 step_size; +}; + +/** + * struct xpsgtr_phy - representation of a lane + * @dev: pointer to the xpsgtr_dev instance + * @refclk: reference clock index + * @type: controller which uses this lane + * @lane: lane number + * @protocol: protocol in which the lane operates + */ +struct xpsgtr_phy { + struct xpsgtr_dev *dev; + unsigned int refclk; + u8 type; + u8 lane; + u8 protocol; +}; + +/** + * struct xpsgtr_dev - representation of a ZynMP GT device + * @dev: pointer to device + * @serdes: serdes base address + * @siou: siou base address + * @phys: PHY lanes + * @refclk_sscs: spread spectrum settings for the reference clocks + * @clk: reference clocks + */ +struct xpsgtr_dev { + struct udevice *dev; + u8 *serdes; + u8 *siou; + struct xpsgtr_phy phys[NUM_LANES]; + const struct xpsgtr_ssc *refclk_sscs[NUM_LANES]; + struct clk clk[NUM_LANES]; +}; + +/* Configuration Data */ +/* lookup table to hold all settings needed for a ref clock frequency */ +static const struct xpsgtr_ssc ssc_lookup[] = { + { 19200000, 0x05, 608, 264020 }, + { 20000000, 0x06, 634, 243454 }, + { 24000000, 0x07, 760, 168973 }, + { 26000000, 0x08, 824, 143860 }, + { 27000000, 0x09, 856, 86551 }, + { 38400000, 0x0a, 1218, 65896 }, + { 40000000, 0x0b, 634, 243454 }, + { 52000000, 0x0c, 824, 143860 }, + { 100000000, 0x0d, 1058, 87533 }, + { 108000000, 0x0e, 856, 86551 }, + { 125000000, 0x0f, 992, 119497 }, + { 135000000, 0x10, 1070, 55393 }, + { 150000000, 0x11, 792, 187091 } +}; + +/* I/O Accessors */ +static u32 xpsgtr_read(struct xpsgtr_dev *gtr_dev, u32 reg) +{ + return readl(gtr_dev->serdes + reg); +} + +static void xpsgtr_write(struct xpsgtr_dev *gtr_dev, u32 reg, u32 value) +{ + writel(value, gtr_dev->serdes + reg); +} + +static void xpsgtr_clr_set(struct xpsgtr_dev *gtr_dev, u32 reg, + u32 clr, u32 set) +{ + u32 value = xpsgtr_read(gtr_dev, reg); + + value &= ~clr; + value |= set; + xpsgtr_write(gtr_dev, reg, value); +} + +static u32 xpsgtr_read_phy(struct xpsgtr_phy *gtr_phy, u32 reg) +{ + void __iomem *addr = gtr_phy->dev->serdes + + gtr_phy->lane * PHY_REG_OFFSET + reg; + + return readl(addr); +} + +static void xpsgtr_write_phy(struct xpsgtr_phy *gtr_phy, + u32 reg, u32 value) +{ + void __iomem *addr = gtr_phy->dev->serdes + + gtr_phy->lane * PHY_REG_OFFSET + reg; + + writel(value, addr); +} + +static void xpsgtr_clr_set_phy(struct xpsgtr_phy *gtr_phy, + u32 reg, u32 clr, u32 set) +{ + void __iomem *addr = gtr_phy->dev->serdes + + gtr_phy->lane * PHY_REG_OFFSET + reg; + + writel((readl(addr) & ~clr) | set, addr); +} + +/* Configure PLL and spread-sprectrum clock. */ +static void xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy) +{ + const struct xpsgtr_ssc *ssc; + u32 step_size; + + ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk]; + step_size = ssc->step_size; + + xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane), + PLL_FREQ_MASK, ssc->pll_ref_clk); + + /* Enable lane clock sharing, if required */ + if (gtr_phy->refclk != gtr_phy->lane) { + /* Lane3 Ref Clock Selection Register */ + xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), + L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk); + } + + /* SSC step size [7:0] */ + xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_0_LSB, + STEP_SIZE_0_MASK, step_size & STEP_SIZE_0_MASK); + + /* SSC step size [15:8] */ + step_size >>= STEP_SIZE_SHIFT; + xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_1, + STEP_SIZE_1_MASK, step_size & STEP_SIZE_1_MASK); + + /* SSC step size [23:16] */ + step_size >>= STEP_SIZE_SHIFT; + xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_2, + STEP_SIZE_2_MASK, step_size & STEP_SIZE_2_MASK); + + /* SSC steps [7:0] */ + xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_0_LSB, + STEPS_0_MASK, ssc->steps & STEPS_0_MASK); + + /* SSC steps [10:8] */ + xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_1_MSB, + STEPS_1_MASK, + (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK); + + /* SSC step size [24:25] */ + step_size >>= STEP_SIZE_SHIFT; + xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_3_MSB, + STEP_SIZE_3_MASK, (step_size & STEP_SIZE_3_MASK) | + FORCE_STEP_SIZE | FORCE_STEPS); +} + +/* Configure the lane protocol. */ +static void xpsgtr_lane_set_protocol(struct xpsgtr_phy *gtr_phy) +{ + struct xpsgtr_dev *gtr_dev = gtr_phy->dev; + u8 protocol = gtr_phy->protocol; + + switch (gtr_phy->lane) { + case 0: + xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L0_MASK, protocol); + break; + case 1: + xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L1_MASK, + protocol << ICM_CFG_SHIFT); + break; + case 2: + xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L0_MASK, protocol); + break; + case 3: + xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L1_MASK, + protocol << ICM_CFG_SHIFT); + break; + default: + /* We already checked 0 <= lane <= 3 */ + break; + } +} + +/* Bypass (de)scrambler and 8b/10b decoder and encoder. */ +static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy) +{ + xpsgtr_write_phy(gtr_phy, L0_TM_DIG_6, L0_TM_DIS_DESCRAMBLE_DECODER); + xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER); +} + +/* SGMII-specific initialization. */ +static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy) +{ + struct xpsgtr_dev *gtr_dev = gtr_phy->dev; + u32 shift = gtr_phy->lane * PROT_BUS_WIDTH_SHIFT; + + /* Set SGMII protocol TX and RX bus width to 10 bits. */ + xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, PROT_BUS_WIDTH_MASK << shift, + PROT_BUS_WIDTH_10 << shift); + + xpsgtr_clr_set(gtr_dev, RX_PROT_BUS_WIDTH, PROT_BUS_WIDTH_MASK << shift, + PROT_BUS_WIDTH_10 << shift); + + xpsgtr_bypass_scrambler_8b10b(gtr_phy); + + /* + * Below code is just temporary solution till we have a way how to + * do it via firmware interface in sync with Linux. Till that happen + * this is the most sensible thing to do here. + */ + /* GEM I/O Clock Control */ + clrsetbits_le32(ZYNQMP_IOU_SLCR_BASEADDR + IOU_SLCR_GEM_CLK_CTRL, + 0xf << shift, + (GEM_CTRL_GEM_SGMII_MODE | GEM_CTRL_GEM_REF_SRC_SEL) << + shift); + + /* Setup signal detect */ + clrsetbits_le32(ZYNQMP_IOU_SLCR_BASEADDR + IOU_SLCR_GEM_CTRL, + PROT_BUS_WIDTH_MASK << shift, + GEM_CTRL_GEM_SGMII_SD << shift); +} + +static int xpsgtr_init(struct phy *x) +{ + struct xpsgtr_dev *gtr_dev = dev_get_priv(x->dev); + struct xpsgtr_phy *gtr_phy; + u32 phy_lane = x->id; + + gtr_phy = >r_dev->phys[phy_lane]; + + /* Enable coarse code saturation limiting logic. */ + xpsgtr_write_phy(gtr_phy, L0_TM_PLL_DIG_37, L0_TM_COARSE_CODE_LIMIT); + + /* + * Configure the PLL, the lane protocol, and perform protocol-specific + * initialization. + */ + xpsgtr_configure_pll(gtr_phy); + xpsgtr_lane_set_protocol(gtr_phy); + + switch (gtr_phy->protocol) { + case ICM_PROTOCOL_SGMII: + xpsgtr_phy_init_sgmii(gtr_phy); + break; + case ICM_PROTOCOL_DP: + case ICM_PROTOCOL_SATA: + return -EINVAL; + } + + dev_dbg(gtr_dev->dev, "lane %u (type %u, protocol %u): init done\n", + gtr_phy->lane, gtr_phy->type, gtr_phy->protocol); + + return 0; +} + +/* Wait for the PLL to lock (with a timeout). */ +static int xpsgtr_wait_pll_lock(struct phy *phy) +{ + struct xpsgtr_dev *gtr_dev = dev_get_priv(phy->dev); + struct xpsgtr_phy *gtr_phy; + u32 phy_lane = phy->id; + int ret = 0; + unsigned int timeout = TIMEOUT_US; + + gtr_phy = >r_dev->phys[phy_lane]; + + dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n"); + + while (1) { + u32 reg = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1); + + if ((reg & PLL_STATUS_LOCKED) == PLL_STATUS_LOCKED) { + ret = 0; + break; + } + + if (--timeout == 0) { + ret = -ETIMEDOUT; + break; + } + + udelay(1); + } + + if (ret == -ETIMEDOUT) + dev_err(gtr_dev->dev, + "lane %u (type %u, protocol %u): PLL lock timeout\n", + gtr_phy->lane, gtr_phy->type, gtr_phy->protocol); + + return ret; +} + +static int xpsgtr_power_on(struct phy *phy) +{ + struct xpsgtr_dev *gtr_dev = dev_get_priv(phy->dev); + struct xpsgtr_phy *gtr_phy; + u32 phy_lane = phy->id; + int ret = 0; + + gtr_phy = >r_dev->phys[phy_lane]; + + /* + * Wait for the PLL to lock. For DP, only wait on DP0 to avoid + * cumulating waits for both lanes. The user is expected to initialize + * lane 0 last. + */ + if (gtr_phy->protocol != ICM_PROTOCOL_DP || + gtr_phy->type == XPSGTR_TYPE_DP_0) + ret = xpsgtr_wait_pll_lock(phy); + + return ret; +} + +/* + * OF Xlate Support + */ + +/* Set the lane type and protocol based on the PHY type and instance number. */ +static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type, + unsigned int phy_instance) +{ + unsigned int num_phy_types; + const int *phy_types; + + switch (phy_type) { + case PHY_TYPE_SATA: { + static const int types[] = { + XPSGTR_TYPE_SATA_0, + XPSGTR_TYPE_SATA_1, + }; + + phy_types = types; + num_phy_types = ARRAY_SIZE(types); + gtr_phy->protocol = ICM_PROTOCOL_SATA; + break; + } + case PHY_TYPE_USB3: { + static const int types[] = { + XPSGTR_TYPE_USB0, + XPSGTR_TYPE_USB1, + }; + + phy_types = types; + num_phy_types = ARRAY_SIZE(types); + gtr_phy->protocol = ICM_PROTOCOL_USB; + break; + } + case PHY_TYPE_DP: { + static const int types[] = { + XPSGTR_TYPE_DP_0, + XPSGTR_TYPE_DP_1, + }; + + phy_types = types; + num_phy_types = ARRAY_SIZE(types); + gtr_phy->protocol = ICM_PROTOCOL_DP; + break; + } + case PHY_TYPE_PCIE: { + static const int types[] = { + XPSGTR_TYPE_PCIE_0, + XPSGTR_TYPE_PCIE_1, + XPSGTR_TYPE_PCIE_2, + XPSGTR_TYPE_PCIE_3, + }; + + phy_types = types; + num_phy_types = ARRAY_SIZE(types); + gtr_phy->protocol = ICM_PROTOCOL_PCIE; + break; + } + case PHY_TYPE_SGMII: { + static const int types[] = { + XPSGTR_TYPE_SGMII0, + XPSGTR_TYPE_SGMII1, + XPSGTR_TYPE_SGMII2, + XPSGTR_TYPE_SGMII3, + }; + + phy_types = types; + num_phy_types = ARRAY_SIZE(types); + gtr_phy->protocol = ICM_PROTOCOL_SGMII; + break; + } + default: + return -EINVAL; + } + + if (phy_instance >= num_phy_types) + return -EINVAL; + + gtr_phy->type = phy_types[phy_instance]; + return 0; +} + +/* + * Valid combinations of controllers and lanes (Interconnect Matrix). + */ +static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = { + { XPSGTR_TYPE_PCIE_0, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0, + XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII0 }, + { XPSGTR_TYPE_PCIE_1, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB0, + XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII1 }, + { XPSGTR_TYPE_PCIE_2, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0, + XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII2 }, + { XPSGTR_TYPE_PCIE_3, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB1, + XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII3 } +}; + +/* Translate OF phandle and args to PHY instance. */ +static int xpsgtr_of_xlate(struct phy *x, + struct ofnode_phandle_args *args) +{ + struct xpsgtr_dev *gtr_dev = dev_get_priv(x->dev); + struct xpsgtr_phy *gtr_phy; + struct udevice *dev = x->dev; + unsigned int phy_instance; + unsigned int phy_lane; + unsigned int phy_type; + unsigned int refclk; + unsigned int i; + int ret; + + if (args->args_count != 4) { + dev_err(dev, "Invalid number of cells in 'phy' property\n"); + return -EINVAL; + } + + /* + * Get the PHY parameters from the OF arguments and derive the lane + * type. + */ + phy_lane = args->args[0]; + if (phy_lane >= NUM_LANES) { + dev_err(dev, "Invalid lane number %u\n", phy_lane); + return -EINVAL; + } + + gtr_phy = >r_dev->phys[phy_lane]; + phy_type = args->args[1]; + phy_instance = args->args[2]; + + ret = xpsgtr_set_lane_type(gtr_phy, phy_type, phy_instance); + if (ret) { + dev_err(dev, "Invalid PHY type and/or instance\n"); + return ret; + } + + refclk = args->args[3]; + if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) || + !gtr_dev->refclk_sscs[refclk]) { + dev_err(dev, "Invalid reference clock number %u\n", refclk); + return -EINVAL; + } + + gtr_phy->refclk = refclk; + + /* This is difference compare to Linux */ + gtr_phy->dev = gtr_dev; + gtr_phy->lane = phy_lane; + + /* + * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type + * is allowed to operate on the lane. + */ + for (i = 0; i < CONTROLLERS_PER_LANE; i++) { + if (icm_matrix[phy_lane][i] == gtr_phy->type) { + x->id = phy_lane; + return 0; + } + } + + return -EINVAL; +} + +/* + * Probe & Platform Driver + */ +static int xpsgtr_get_ref_clocks(struct udevice *dev) +{ + unsigned int refclk; + struct xpsgtr_dev *gtr_dev = dev_get_priv(dev); + int ret; + + for (refclk = 0; refclk < NUM_LANES; ++refclk) { + int i; + u32 rate; + char name[8]; + struct clk *clk = >r_dev->clk[refclk]; + + snprintf(name, sizeof(name), "ref%u", refclk); + dev_dbg(dev, "Checking name: %s\n", name); + ret = clk_get_by_name(dev, name, clk); + if (ret == -ENODATA) { + dev_dbg(dev, "%s clock not specified (err %d)\n", + name, ret); + continue; + } else if (ret) { + dev_dbg(dev, "couldn't get clock %s (err %d)\n", + name, ret); + return ret; + } + + rate = clk_get_rate(clk); + + dev_dbg(dev, "clk rate %d\n", rate); + + ret = clk_enable(clk); + if (ret) { + dev_err(dev, "failed to enable refclk %d clock\n", + refclk); + return ret; + } + + for (i = 0 ; i < ARRAY_SIZE(ssc_lookup); i++) { + if (rate == ssc_lookup[i].refclk_rate) { + gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i]; + dev_dbg(dev, "Found rate %d\n", i); + break; + } + } + + if (i == ARRAY_SIZE(ssc_lookup)) { + dev_err(dev, + "Invalid rate %u for reference clock %u\n", + rate, refclk); + return -EINVAL; + } + } + + return 0; +} + +static int xpsgtr_probe(struct udevice *dev) +{ + struct xpsgtr_dev *gtr_dev = dev_get_priv(dev); + + gtr_dev->serdes = dev_remap_addr_name(dev, "serdes"); + if (!gtr_dev->serdes) + return -EINVAL; + + gtr_dev->siou = dev_remap_addr_name(dev, "siou"); + if (!gtr_dev->siou) + return -EINVAL; + + gtr_dev->dev = dev; + + return xpsgtr_get_ref_clocks(dev); +} + +static const struct udevice_id xpsgtr_phy_ids[] = { + { .compatible = "xlnx,zynqmp-psgtr-v1.1", }, + { } +}; + +static const struct phy_ops xpsgtr_phy_ops = { + .init = xpsgtr_init, + .of_xlate = xpsgtr_of_xlate, + .power_on = xpsgtr_power_on, +}; + +U_BOOT_DRIVER(psgtr_phy) = { + .name = "psgtr_phy", + .id = UCLASS_PHY, + .of_match = xpsgtr_phy_ids, + .ops = &xpsgtr_phy_ops, + .probe = xpsgtr_probe, + .priv_auto = sizeof(struct xpsgtr_dev), +}; From a2d5f3d133b4ce4e7cb0fcf1d761c75c4f1b2f8d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 14 Jan 2022 13:15:48 +0100 Subject: [PATCH 29/36] Revert "net: gem: Disable broadcast setting" This reverts commit eafdcda4a854932c0319656de7bf3f017f17ae67. The main reason is that QEMU is using BOOTP protocol which is sending DHCP Offer to a broadcast address that's why it can't be disabled. DHCP protocol has no issue because it returns directly to client MAC address. Both of these options are described in RFC951 (https://datatracker.ietf.org/doc/html/rfc951#section-4) Signed-off-by: Michal Simek Reviewed-by: Ramon Fried Link: https://lore.kernel.org/r/fc5f5e2aeca77847ed4ca6a263890375ab9f5163.1642162545.git.michal.simek@xilinx.com --- drivers/net/zynq_gem.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index b751d28e61..2c27ffd770 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -62,7 +62,6 @@ #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ -#define ZYNQ_GEM_NWCFG_NO_BRDC BIT(5) /* No broadcast */ #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ @@ -80,7 +79,6 @@ #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ ZYNQ_GEM_NWCFG_FDEN | \ - ZYNQ_GEM_NWCFG_NO_BRDC | \ ZYNQ_GEM_NWCFG_FSREM | \ ZYNQ_GEM_NWCFG_MDCCLKDIV) From ca994327ce424f8cc433753bf3f135f6006199f0 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Fri, 14 Jan 2022 13:08:07 +0100 Subject: [PATCH 30/36] net: gem: Workaround gmii2rgmii bridge DT node issue For configurations with gmii2rgmii and external phy the DT nodes link should be gem->gmii2rgmii->phy. But due to limitation in Linux driver the DT is mentioned as gem->phy and gmii2rgmii->phy as shown in below DT. ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem\0cdns,gem"; status = "okay"; interrupt-parent = <0x04>; interrupts = <0x00 0x3b 0x04 0x00 0x3b 0x04>; reg = <0x00 0xff0c0000 0x00 0x1000>; clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; #address-cells = <0x01>; #size-cells = <0x00>; #stream-id-cells = <0x01>; iommus = <0x0d 0x875>; power-domains = <0x0c 0x1e>; clocks = <0x03 0x1f 0x03 0x69 0x03 0x2e 0x03 0x32 0x03 0x2c>; phy-handle = <0x0e>; phy-mode = "gmii"; xlnx,ptp-enet-clock = <0x00>; local-mac-address = [ff ff ff ff ff ff]; phandle = <0x4d>; mdio { #address-cells = <0x01>; #size-cells = <0x00>; phandle = <0x4e>; ethernet-phy@1 { reg = <0x01>; rxc-skew-ps = <0x708>; txc-skew-ps = <0x708>; phandle = <0x0e>; }; gmii_to_rgmii_0@8 { compatible = "xlnx,gmii-to-rgmii-1.0"; phy-handle = <0x0e>; reg = <0x08>; phandle = <0x4f>; }; }; }; Since same DT is used in Linux and U-Boot we need to workaround this issue by using the gmii2rgmii node which points to phy and we should ignore the gem pointing to phy directly. Do this workaround by updating priv->phydev->node value with priv->phy_of_node only if it is not valid node. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Reviewed-by: Ramon Fried Link: https://lore.kernel.org/r/641eb13425ffe80e0743f60cf90d0f940577b9e9.1642162085.git.michal.simek@xilinx.com --- drivers/net/zynq_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 2c27ffd770..3118d14726 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -336,7 +336,8 @@ static int zynq_phy_init(struct udevice *dev) ADVERTISED_Asym_Pause; priv->phydev->advertising = priv->phydev->supported; - priv->phydev->node = priv->phy_of_node; + if (!ofnode_valid(priv->phydev->node)) + priv->phydev->node = priv->phy_of_node; return phy_config(priv->phydev); } From 59b21d2aea89d07166bf61cd7d639a58aba1b1cc Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 14 Jan 2022 12:43:05 +0100 Subject: [PATCH 31/36] arm64: zynqmp: Change compatible strings for cadence uart Based on Linux kernel DT binding there should be different compatible strings used that's why align zynqmp.dtsi with it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e2404ccd22fd97fe6020be0b3b6eb3c8677f55b0.1642160583.git.michal.simek@xilinx.com --- arch/arm/dts/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 015a582d7a..300a2189f6 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -824,7 +824,7 @@ uart0: serial@ff000000 { u-boot,dm-pre-reloc; - compatible = "cdns,uart-r1p12", "xlnx,xuartps"; + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; @@ -835,7 +835,7 @@ uart1: serial@ff010000 { u-boot,dm-pre-reloc; - compatible = "cdns,uart-r1p12", "xlnx,xuartps"; + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; From 1d70cc7789c2d65ac655a9c6154d1455452e76ff Mon Sep 17 00:00:00 2001 From: Manish Narani Date: Fri, 14 Jan 2022 12:43:35 +0100 Subject: [PATCH 32/36] arm64: zynqmp: Update USB node handle from dwc3 to usb The DWC3 bindings require all USB node handles to be '^usb@[0-9a-f]+$'. Update the same in ZynqMP device tree. Signed-off-by: Manish Narani Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/26fc2777eeb92cb5cb1d558d7c19cfb54ac42d0c.1642160613.git.michal.simek@xilinx.com --- arch/arm/dts/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 300a2189f6..1331cec36f 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -858,7 +858,7 @@ reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; - dwc3_0: dwc3@fe200000 { + dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; @@ -890,7 +890,7 @@ reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; - dwc3_1: dwc3@fe300000 { + dwc3_1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; From d10807a06b0792ce07eed6ec41d70cfc8998d2b0 Mon Sep 17 00:00:00 2001 From: Shravya Kumbham Date: Fri, 14 Jan 2022 12:44:06 +0100 Subject: [PATCH 33/36] arm64: xilinx: dts: Add dma properties to fix dtbs_check warnings Update dma name and add #dma-cells properties to fix dtbs_check warnings. Signed-off-by: Shravya Kumbham Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/fedbf83fd5c682b4d61905d2cb790d33c2f079d6.1642160644.git.michal.simek@xilinx.com --- arch/arm/dts/zynqmp.dtsi | 48 ++++++++++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 1331cec36f..755a4ed2e5 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -265,7 +265,7 @@ }; /* GDMA */ - fpd_dma_chan1: dma@fd500000 { + fpd_dma_chan1: dma-controller@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; @@ -276,9 +276,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; + #dma-cells = <1>; }; - fpd_dma_chan2: dma@fd510000 { + fpd_dma_chan2: dma-controller@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; @@ -289,9 +290,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; + #dma-cells = <1>; }; - fpd_dma_chan3: dma@fd520000 { + fpd_dma_chan3: dma-controller@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; @@ -302,9 +304,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; + #dma-cells = <1>; }; - fpd_dma_chan4: dma@fd530000 { + fpd_dma_chan4: dma-controller@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; @@ -315,9 +318,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; + #dma-cells = <1>; }; - fpd_dma_chan5: dma@fd540000 { + fpd_dma_chan5: dma-controller@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; @@ -328,9 +332,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; + #dma-cells = <1>; }; - fpd_dma_chan6: dma@fd550000 { + fpd_dma_chan6: dma-controller@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; @@ -341,9 +346,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; + #dma-cells = <1>; }; - fpd_dma_chan7: dma@fd560000 { + fpd_dma_chan7: dma-controller@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; @@ -354,9 +360,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; + #dma-cells = <1>; }; - fpd_dma_chan8: dma@fd570000 { + fpd_dma_chan8: dma-controller@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; @@ -367,6 +374,7 @@ #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; + #dma-cells = <1>; }; gic: interrupt-controller@f9010000 { @@ -396,7 +404,7 @@ * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ - lpd_dma_chan1: dma@ffa80000 { + lpd_dma_chan1: dma-controller@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; @@ -407,9 +415,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x868>; power-domains = <&zynqmp_firmware PD_ADMA>; + #dma-cells = <1>; }; - lpd_dma_chan2: dma@ffa90000 { + lpd_dma_chan2: dma-controller@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; @@ -420,9 +429,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x869>; power-domains = <&zynqmp_firmware PD_ADMA>; + #dma-cells = <1>; }; - lpd_dma_chan3: dma@ffaa0000 { + lpd_dma_chan3: dma-controller@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; @@ -433,9 +443,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x86a>; power-domains = <&zynqmp_firmware PD_ADMA>; + #dma-cells = <1>; }; - lpd_dma_chan4: dma@ffab0000 { + lpd_dma_chan4: dma-controller@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; @@ -446,9 +457,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x86b>; power-domains = <&zynqmp_firmware PD_ADMA>; + #dma-cells = <1>; }; - lpd_dma_chan5: dma@ffac0000 { + lpd_dma_chan5: dma-controller@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; @@ -459,9 +471,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x86c>; power-domains = <&zynqmp_firmware PD_ADMA>; + #dma-cells = <1>; }; - lpd_dma_chan6: dma@ffad0000 { + lpd_dma_chan6: dma-controller@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; @@ -472,9 +485,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x86d>; power-domains = <&zynqmp_firmware PD_ADMA>; + #dma-cells = <1>; }; - lpd_dma_chan7: dma@ffae0000 { + lpd_dma_chan7: dma-controller@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; @@ -485,9 +499,10 @@ #stream-id-cells = <1>; iommus = <&smmu 0x86e>; power-domains = <&zynqmp_firmware PD_ADMA>; + #dma-cells = <1>; }; - lpd_dma_chan8: dma@ffaf0000 { + lpd_dma_chan8: dma-controller@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; @@ -498,6 +513,7 @@ #stream-id-cells = <1>; iommus = <&smmu 0x86f>; power-domains = <&zynqmp_firmware PD_ADMA>; + #dma-cells = <1>; }; mc: memory-controller@fd070000 { From 71efd45a5fc70e29e391e0b57c700de8708ae6d9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 14 Jan 2022 13:08:42 +0100 Subject: [PATCH 34/36] arm64: zynqmp: Change firmware dependency In case of mini U-Boot configurations there is no need to enable firmware driver which just consume space for nothing. That's why add an option to disable it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d439399160ff3374f2b39f54f7dd70fa8c8bfea0.1642162121.git.michal.simek@xilinx.com --- arch/arm/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 23d57ca10c..635cea6131 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1193,7 +1193,7 @@ config ARCH_ZYNQMP select DM_SERIAL select DM_SPI if SPI select DM_SPI_FLASH if DM_SPI - select FIRMWARE + imply FIRMWARE select GICV2 select GPIO_EXTRA_HEADER select OF_CONTROL @@ -1203,7 +1203,7 @@ config ARCH_ZYNQMP select SPL_DM_SPI if SPI && SPL_DM select SPL_DM_SPI_FLASH if SPL_DM_SPI select SPL_DM_MAILBOX if SPL - select SPL_FIRMWARE if SPL + imply SPL_FIRMWARE if SPL select SPL_SEPARATE_BSS if SPL select SUPPORT_SPL select ZYNQMP_IPI From 12662e7034b4b6e070830e074f1cfab139dd21d6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 14 Jan 2022 13:25:36 +0100 Subject: [PATCH 35/36] firmware: zynqmp: Move loading message to debug Power domain driver is using this function for every IP which is PD listed. This can end up with a lot of messages which end up in boot log. That's why show it only in EL3 as was used in past. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d73fc8bc663110b6e8d5e70fdb6435d1199e9db8.1642163135.git.michal.simek@xilinx.com --- drivers/firmware/firmware-zynqmp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index aa20e33b40..18a092c7b4 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -98,7 +98,8 @@ void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size) int err; u32 ret_payload[PAYLOAD_ARG_CNT]; - printf("Loading new PMUFW cfg obj (%ld bytes)\n", size); + if (IS_ENABLED(CONFIG_SPL_BUILD)) + printf("Loading new PMUFW cfg obj (%ld bytes)\n", size); flush_dcache_range((ulong)cfg_obj, (ulong)(cfg_obj + size)); From 11c07719d58d4627e21fc59f5ab58f85edd5c024 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 14 Jan 2022 13:25:37 +0100 Subject: [PATCH 36/36] firmware: zynqmp: Do not report error if node is already configured Power domain driver sends PM fragment to PMUFW. It is sent for every node which is listed in DT. But some nodes could be already enabled but driver is not capable to find it out. That's why it blinly sents request for every listed IP. When PMUFW response by XST_PM_ALREADY_CONFIGURED error code there is no need to show any error message because node is already enabled. That's why cover this case with message when DEBUG is enabled. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8c15ef0b68cf191f693d3d010f70ac24cfd8171f.1642163135.git.michal.simek@xilinx.com --- drivers/firmware/firmware-zynqmp.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 18a092c7b4..839203ec82 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -20,6 +20,7 @@ #define PMUFW_PAYLOAD_ARG_CNT 8 #define XST_PM_NO_ACCESS 2002L +#define XST_PM_ALREADY_CONFIGURED 2009L struct zynqmp_power { struct mbox_chan tx_chan; @@ -110,6 +111,11 @@ void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size) return; } + if (err == XST_PM_ALREADY_CONFIGURED) { + debug("PMUFW Node is already configured\n"); + return; + } + if (err) printf("Cannot load PMUFW configuration object (%d)\n", err);