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driver/ddr/fsl: Add support for multiple DDR clocks

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Controller number is passed for function calls to support individual
DDR clock, depending on SoC implementation. It is backward compatible
with exising platforms. Multiple clocks have been verifyed on LS2085A
emulator.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun
2015-01-06 13:18:50 -08:00
parent b87e6f88e9
commit 03e664d8f4
14 changed files with 190 additions and 159 deletions
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4
drivers/ddr/fsl/mpc85xx_ddr_gen3.c
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@@ -426,7 +426,7 @@ step2:
bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
(get_ddr_freq(0) >> 20)) << 1;
(get_ddr_freq(ctrl_num) >> 20)) << 1;
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
timeout_save = timeout;
#endif
@@ -538,12 +538,14 @@ step2:
case 1:
out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
break;
#if CONFIG_CHIP_SELECTS_PER_CTRL > 2
case 2:
out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
break;
case 3:
out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
break;
#endif
}
clrbits_be32(&ddr->sdram_cfg, 0x2);
}