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https://github.com/linux-sunxi/meta-sunxi.git
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Merge pull request #383 from ludiazv/opiz2_dts
Add usb support for orange pi zero 2
This commit is contained in:
commit
4bf7be7650
@ -0,0 +1,184 @@
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From ab35c98369d50766eb20920a93a2dca927935481 Mon Sep 17 00:00:00 2001
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From: OpenEmbedded <oe.patch@oe>
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Date: Fri, 19 May 2023 23:01:14 +0200
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Subject: [PATCH] Add usb support to h616. This is not needed from kernel 6.2
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Signed-off-by: OpenEmbedded <oe.patch@oe>
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---
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.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++
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1 file changed, 160 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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index 04cdec7e2..a1d872e74 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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@@ -504,6 +504,166 @@ mdio0: mdio {
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};
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};
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+ usbotg: usb@5100000 {
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+ compatible = "allwinner,sun50i-h616-musb",
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+ "allwinner,sun8i-h3-musb";
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+ reg = <0x05100000 0x0400>;
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+ clocks = <&ccu CLK_BUS_OTG>;
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+ resets = <&ccu RST_BUS_OTG>;
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+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "mc";
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+ phys = <&usbphy 0>;
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+ phy-names = "usb";
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+ extcon = <&usbphy 0>;
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+ status = "disabled";
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+ };
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+
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+ usbphy: phy@5100400 {
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+ compatible = "allwinner,sun50i-h616-usb-phy";
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+ reg = <0x05100400 0x24>,
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+ <0x05101800 0x14>,
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+ <0x05200800 0x14>,
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+ <0x05310800 0x14>,
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+ <0x05311800 0x14>;
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+ reg-names = "phy_ctrl",
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+ "pmu0",
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+ "pmu1",
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+ "pmu2",
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+ "pmu3";
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+ clocks = <&ccu CLK_USB_PHY0>,
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+ <&ccu CLK_USB_PHY1>,
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+ <&ccu CLK_USB_PHY2>,
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+ <&ccu CLK_USB_PHY3>,
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+ <&ccu CLK_BUS_EHCI2>;
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+ clock-names = "usb0_phy",
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+ "usb1_phy",
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+ "usb2_phy",
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+ "usb3_phy",
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+ "pmu2_clk";
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+ resets = <&ccu RST_USB_PHY0>,
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+ <&ccu RST_USB_PHY1>,
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+ <&ccu RST_USB_PHY2>,
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+ <&ccu RST_USB_PHY3>;
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+ reset-names = "usb0_reset",
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+ "usb1_reset",
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+ "usb2_reset",
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+ "usb3_reset";
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+ status = "disabled";
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+ #phy-cells = <1>;
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+ };
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+
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+ ehci0: usb@5101000 {
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+ compatible = "allwinner,sun50i-h616-ehci",
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+ "generic-ehci";
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+ reg = <0x05101000 0x100>;
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+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_OHCI0>,
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+ <&ccu CLK_BUS_EHCI0>,
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+ <&ccu CLK_USB_OHCI0>;
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+ resets = <&ccu RST_BUS_OHCI0>,
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+ <&ccu RST_BUS_EHCI0>;
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+ phys = <&usbphy 0>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ ohci0: usb@5101400 {
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+ compatible = "allwinner,sun50i-h616-ohci",
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+ "generic-ohci";
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+ reg = <0x05101400 0x100>;
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+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_OHCI0>,
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+ <&ccu CLK_USB_OHCI0>;
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+ resets = <&ccu RST_BUS_OHCI0>;
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+ phys = <&usbphy 0>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ ehci1: usb@5200000 {
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+ compatible = "allwinner,sun50i-h616-ehci",
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+ "generic-ehci";
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+ reg = <0x05200000 0x100>;
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+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_OHCI1>,
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+ <&ccu CLK_BUS_EHCI1>,
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+ <&ccu CLK_USB_OHCI1>;
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+ resets = <&ccu RST_BUS_OHCI1>,
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+ <&ccu RST_BUS_EHCI1>;
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+ phys = <&usbphy 1>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ ohci1: usb@5200400 {
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+ compatible = "allwinner,sun50i-h616-ohci",
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+ "generic-ohci";
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+ reg = <0x05200400 0x100>;
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+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_OHCI1>,
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+ <&ccu CLK_USB_OHCI1>;
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+ resets = <&ccu RST_BUS_OHCI1>;
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+ phys = <&usbphy 1>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ ehci2: usb@5310000 {
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+ compatible = "allwinner,sun50i-h616-ehci",
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+ "generic-ehci";
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+ reg = <0x05310000 0x100>;
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+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_OHCI2>,
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+ <&ccu CLK_BUS_EHCI2>,
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+ <&ccu CLK_USB_OHCI2>;
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+ resets = <&ccu RST_BUS_OHCI2>,
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+ <&ccu RST_BUS_EHCI2>;
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+ phys = <&usbphy 2>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ ohci2: usb@5310400 {
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+ compatible = "allwinner,sun50i-h616-ohci",
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+ "generic-ohci";
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+ reg = <0x05310400 0x100>;
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+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_OHCI2>,
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+ <&ccu CLK_USB_OHCI2>;
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+ resets = <&ccu RST_BUS_OHCI2>;
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+ phys = <&usbphy 2>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ ehci3: usb@5311000 {
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+ compatible = "allwinner,sun50i-h616-ehci",
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+ "generic-ehci";
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+ reg = <0x05311000 0x100>;
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+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_OHCI3>,
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+ <&ccu CLK_BUS_EHCI3>,
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+ <&ccu CLK_USB_OHCI3>;
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+ resets = <&ccu RST_BUS_OHCI3>,
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+ <&ccu RST_BUS_EHCI3>;
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+ phys = <&usbphy 3>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ ohci3: usb@5311400 {
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+ compatible = "allwinner,sun50i-h616-ohci",
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+ "generic-ohci";
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+ reg = <0x05311400 0x100>;
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+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_OHCI3>,
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+ <&ccu CLK_USB_OHCI3>;
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+ resets = <&ccu RST_BUS_OHCI3>;
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+ phys = <&usbphy 3>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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rtc: rtc@7000000 {
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compatible = "allwinner,sun50i-h616-rtc";
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reg = <0x07000000 0x400>;
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--
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2.40.1
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@ -0,0 +1,84 @@
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From 038441bbe0f6dab3e701061c514a8d776dbe6523 Mon Sep 17 00:00:00 2001
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From: OpenEmbedded <oe.patch@oe>
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Date: Sat, 20 May 2023 14:07:47 +0200
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Subject: [PATCH] DTS orange pi zero2 enable usb
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Signed-off-by: OpenEmbedded <oe.patch@oe>
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---
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.../allwinner/sun50i-h616-orangepi-zero2.dts | 42 +++++++++++++++++++
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1 file changed, 42 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
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index 88234a139..3b836296b 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
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@@ -50,6 +50,16 @@ reg_vcc5v: vcc5v {
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regulator-always-on;
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};
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+ reg_usb1_vbus: regulator-usb1-vbus {
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+ compatible = "regulator-fixed";
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+ regulator-name = "usb1-vbus";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ vin-supply = <®_vcc5v>;
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+ enable-active-high;
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+ gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
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+ };
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+
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reg_vcc33_wifi: vcc33-wifi {
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/* Always on 3.3V regulator for WiFi and BT */
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compatible = "regulator-fixed";
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@@ -79,6 +89,12 @@ wifi_pwrseq: wifi-pwrseq {
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};
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};
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+&ehci1 {
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+ status = "okay";
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+};
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+
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+/* USB 2 & 3 are on headers only. */
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+
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&mmc1 {
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vmmc-supply = <®_vcc33_wifi>;
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vqmmc-supply = <®_vcc_wifi_io>;
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@@ -123,6 +139,11 @@ &mmc0 {
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status = "okay";
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};
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+
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+&ohci1 {
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+ status = "okay";
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+};
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+
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&r_rsb {
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status = "okay";
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@@ -258,3 +279,24 @@ &uart0 {
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pinctrl-0 = <&uart0_ph_pins>;
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status = "okay";
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};
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+
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+&usbotg {
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+ /*
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+ * PHY0 pins are connected to a USB-C socket, but a role switch
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+ * is not implemented: both CC pins are pulled to GND.
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+ * The VBUS pins power the device, so a fixed peripheral mode
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+ * is the best choice.
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+ * The board can be powered via GPIOs, in this case port0 *can*
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+ * act as a host (with a cable/adapter ignoring CC), as VBUS is
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+ * then provided by the GPIOs. Any user of this setup would
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+ * need to adjust the DT accordingly: dr_mode set to "host",
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+ * enabling OHCI0 and EHCI0.
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+ */
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+ dr_mode = "peripheral";
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+ status = "okay";
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+};
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+
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+&usbphy {
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+ usb1_vbus-supply = <®_usb1_vbus>;
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+ status = "okay";
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+};
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--
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2.40.1
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@ -18,4 +18,6 @@ SRC_URI:append:orange-pi-zero2 = " \
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file://0008-drv-add-sunxi-addr-driver.patch \
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file://0008-drv-add-sunxi-addr-driver.patch \
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file://0009-dts-add-addr_mgt-device-tree-node.patch \
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file://0009-dts-add-addr_mgt-device-tree-node.patch \
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file://0010-dts-add-wifi-power-regulator.patch \
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file://0010-dts-add-wifi-power-regulator.patch \
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file://0011-dts-add-usb-to-h616.patch \
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file://0012-dts-orange-pi-zero2.patch \
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"
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"
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